SIR638DP-T1-GE3

SiR638DP www.vishay.com Vishay Siliconix N-Channel 40 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 40 RDS(on) () (MAX.) ID (A) a, g 0.00088 at VGS = 10 V 100 0.00116 at VGS = 4.5 V 100 Qg (TYP.) 63 nC D 5 D 6 • 100 % Rg and UIS tested • Qgd / Qgs ratio < 1 optimizes switching characteristics PowerPAK® SO-8 Single D 7 • TrenchFET® Gen IV power MOSFET • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 D 8 APPLICATIONS D • Synchronous rectification 6. 15 m m 1 5 5.1 mm Top View 3 S 4 G Bottom View 2 S 1 S • ORing • High power density DC/DC G • VRMs and embedded DC/DC • DC/AC inverters Ordering Information: SiR638DP-T1-GE3 (lead (Pb)-free and halogen-free) • Load switch S N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 40 Gate-Source Voltage VGS +20, -16 TC = 70 °C TA = 25 °C 100 g ID 62.8 b, c 50.2 b, c TA = 70 °C Pulsed Drain Current (t = 100 μs) Continuous Source-Drain Diode Current Single Pulse Avalanche Current Single Pulse Avalanche Energy IDM TC = 25 °C TA = 25 °C L = 0.1 mH TC = 70 °C TA = 25 °C 94.5 IS 5.6 b, c IAS 50 EAS 125 mJ 104 66.6 PD W 6.25 b, c 4 b, c TA = 70 °C Operating Junction and Storage Temperature Range A 400 TC = 25 °C Maximum Power Dissipation V 100 g TC = 25 °C Continuous Drain Current (TJ = 150 °C) UNIT TJ, Tstg -55 to +150 Soldering Recommendations (Peak Temperature) d, e °C 260 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICAL MAXIMUM Maximum Junction-to-Ambient b, f t  10 s RthJA 15 20 Maximum Junction-to-Case (Drain) Steady State RthJC 0.9 1.2 UNIT °C/W Notes a. Based on TC = 25 °C. b. Surface mounted on 1" x 1" FR4 board. c. t = 10 s. d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 54 °C/W. g. Package limited. S16-0332-Rev. A, 29-Feb-16 Document Number: 64430 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiR638DP www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 40 - - V - 24 - - -5.4 - Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS/TJ VGS(th) Temperature Coefficient VGS(th)/TJ Gate-Source Threshold Voltage ID = 250 μA mV/°C VGS(th) VDS = VGS, ID = 250 μA 1.1 - 2.3 V Gate-Source Leakage IGSS VDS = 0 V, VGS = +20, -16 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS On-State Drain Current a ID(on) Drain-Source On-State Resistance a Forward Transconductance a RDS(on) gfs VDS = 40 V, VGS = 0 V - - 1 VDS = 40 V, VGS = 0 V, TJ = 55 °C - - 10 VDS  5 V, VGS = 10 V 50 - - VGS = 10 V, ID = 20 A - 0.00073 0.00088 VGS = 4.5 V, ID = 15 A - 0.00096 0.00116 VDS = 10 V, ID = 20 A - 147 - μA A  S Dynamic b Input Capacitance Ciss - 10 500 - Output Capacitance Coss - 1530 - Reverse Transfer Capacitance Crss - 250 - - 0.024 0.048 - 136 204 - 63 95 - 30.5 - - 10.6 - VDS = 20 V, VGS = 0 V, f = 1 MHz Crss/Ciss Ratio VDS = 20 V, VGS = 10 V, ID = 20 A Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Output Charge Qoss VDS = 20 V, VGS = 0 V - 75 - Rg f = 1 MHz 0.3 0.88 1.5 - 20 40 - 21 42 100 Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time VDS = 20 V, VGS = 4.5 V, ID = 20 A td(on) tr td(off) VDD = 20 V, RL = 1  ID  20 A, VGEN = 10 V, Rg = 1  pF nC  - 52 tf - 10 20 td(on) - 70 140 - 16 32 - 43 86 - 19 38 - - 100 - - 400 - 0.73 1.1 V - 59 118 ns - 85 170 nC - 34 - - 25 - tr td(off) VDD = 20 V, RL = 1  ID  20 A, VGEN = 4.5 V, Rg = 1  tf ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Current (tp = 100 μs) ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C IS = 10 A IF = 20 A, dI/dt = 100 A/μs, TJ = 25 °C A ns Notes a. Pulse test; pulse width  300 μs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S16-0332-Rev. A, 29-Feb-16 Document Number: 64430 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiR638DP www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Axis Title Axis Title 150 150 10000 10000 VGS = 10 V thru 4 V 60 100 30 1000 90 1st line 2nd line 1000 VGS = 3 V TC = 25 °C 60 100 TC = 125 °C 30 TC = -55 °C VGS = 2 V 0 0 10 0 0.5 1 1.5 2 2.5 10 0 1 2 VGS - Gate-to-Source Voltage (V) 2nd line Output Characteristics Transfer Characteristics 10000 Ciss 12000 0.0008 100 0.0007 1000 9000 1st line 2nd line 1000 VGS = 4.5 V 2nd line C - Capacitance (pF) 0.001 1st line 2nd line 2nd line RDS(on) - On-Resistance (Ω) 15000 10000 0.0009 6000 Coss 3000 0.0006 0 10 40 60 80 100 Crss VGS = 10 V 20 10 0 100 8 16 32 VDS - Drain-to-Source Voltage (V) 2nd line On-Resistance vs. Drain Current Capacitance 2.0 ID = 20 A 8 VDS = 20 V 1000 1st line 2nd line 6 VDS = 10 V 4 100 VDS = 30 V 2 0 10 90 120 150 2nd line RDS(on) - On-Resistance (Normalized) 10000 60 40 Axis Title Axis Title 10 2nd line VGS - Gate-to-Source Voltage (V) 24 ID - Drain Current (A) 2nd line 30 5 Axis Title Axis Title 0 4 VDS - Drain-to-Source Voltage (V) 2nd line 0.0011 0 3 10000 ID = 20 A 1.7 VGS = 10 V VGS = 4.5 V 1.1 100 0.8 0.5 10 -50 -25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) 2nd line TJ - Junction Temperature (°C) 2nd line Gate Charge On-Resistance vs. Junction Temperature S16-0332-Rev. A, 29-Feb-16 1000 1.4 1st line 2nd line 90 2nd line ID - Drain Current (A) 120 1st line 2nd line 2nd line ID - Drain Current (A) 120 Document Number: 64430 3 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiR638DP www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Axis Title Axis Title 0.005 2nd line RDS(on) - On-Resistance (Ω) 10000 TJ = 150 °C 1000 1 TJ = 25 °C 1st line 2nd line 2nd line IS - Source Current (A) 10 0.1 100 0.01 10000 0.004 1000 0.003 1st line 2nd line 100 0.002 TJ = 125 °C 100 0.001 TJ = 25 °C 0.001 0 10 0 0.2 0.4 0.6 0.8 1.0 10 0 1.2 2 4 8 10 VSD - Source-to-Drain Voltage (V) 2nd line VGS - Gate-to-Source Voltage (V) 2nd line Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage Axis Title Axis Title 0.5 100 10000 0.2 10000 80 1000 1000 2nd line Power (W) ID = 5 mA -0.4 60 1st line 2nd line -0.1 1st line 2nd line 2nd line VGS(th) - Variance (V) 6 40 100 ID = 250 μA 100 -0.7 20 -1.0 10 -50 -25 0 25 50 75 0 0.001 100 125 150 10 0.01 0.1 1 10 TJ - Temperature (°C) 2nd line Time (s) 2nd line Threshold Voltage Single Pulse Power, Junction-to-Ambient Axis Title 1000 100 100 μs ID limited 1 ms1000 10 Limited by RDS(on) (1) 10 ms 1 100 ms 1s 1st line 2nd line 2nd line ID - Drain Current (A) 10000 IDM limited 100 10 s 0.1 TA = 25 °C Single pulse 0.01 0.01 (1) DC BVDSS limited 10 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) VGS > minimum VGS at which RDS(on) is specified Safe Operating Area S16-0332-Rev. A, 29-Feb-16 Document Number: 64430 4 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiR638DP www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Axis Title 300 10000 1000 180 1st line 2nd line 2nd line ID - Drain Current (A) 240 Package limited 120 100 60 0 10 0 25 50 75 100 125 150 TC - Case Temperature (°C) 2nd line Current Derating a Axis Title Axis Title 125 3.0 10000 100 10000 2.4 1.8 1st line 2nd line 50 2nd line Power (W) 1000 1st line 2nd line 2nd line Power (W) 1000 75 1.2 100 25 100 0.6 0 10 0 25 50 75 100 125 150 0 10 0 25 50 75 100 125 TC - Case Temperature (°C) 2nd line TA - Ambient Temperature (°C) 2nd line Power, Junction-to-Case Power, Junction-to-Ambient 150 Note a. The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. S16-0332-Rev. A, 29-Feb-16 Document Number: 64430 5 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiR638DP www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Axis Title 10000 Duty Cycle = 0.5 Notes: 0.2 PDM 0.1 0.1 1000 1st line 2nd line Normalized Effective Transient Thermal Impedance 1 t1 0.05 t2 t 1. Duty cycle, D = t1 2 2. Per unit base = RthJA = 54 °C/W 0.02 Single pulse 3. TJM - TA = PDMZthJA 100 (t) 4. Surface mounted 0.01 0.0001 0.001 0.01 0.1 1 10 100 10 1000 Square Wave Pulse Duration (s) 2nd line Normalized Thermal Transient Impedance, Junction-to-Ambient Axis Title 10000 1 0.2 0.1 1000 0.05 1st line 2nd line Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.02 0.1 Single pulse 100 0.01 0.0001 10 0.001 0.01 0.1 1 10 Square Wave Pulse Duration (s) 2nd line Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64430. S16-0332-Rev. A, 29-Feb-16 Document Number: 64430 6 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix PowerPAK® SO-8, (Single/Dual) L H E2 K E4 θ D4 W 1 M 1 Z 2 D5 D2 e 2 D1 D 2 D 3 4 θ 4 b 3 L1 E3 θ A1 Backside View of Single Pad H K E2 E4 L 1 D1 D5 2 D2 Detail Z K1 2 E1 E D3 (2x) D4 c A θ 3 4 Notes 1. Inch will govern. 2 Dimensions exclusive of mold gate burrs. 3. Dimensions exclusive of mold flash and cutting burrs. DIM. A A1 b c D D1 D2 D3 D4 D5 E E1 E2 E3 E4 e K K1 H L L1  W M b D2 E3 Backside View of Dual Pad MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. 0.97 1.04 0.41 0.28 5.15 4.90 3.76 1.50 0.57 typ. 3.98 typ. 6.15 5.89 3.66 3.78 0.75 typ. 1.27 BSC 1.27 typ. 0.61 0.61 0.13 0.25 0.125 typ. 1.12 0.05 0.51 0.33 5.26 5.00 3.91 1.68 0.038 0 0.013 0.009 0.199 0.189 0.140 0.052 0.044 0.002 0.020 0.013 0.207 0.197 0.154 0.066 6.25 5.99 3.84 3.91 0.238 0.228 0.137 0.145 0.71 0.71 0.20 12° 0.36 0.022 0.020 0.020 0.002 0° 0.006 0.041 0.016 0.011 0.203 0.193 0.148 0.059 0.0225 typ. 0.157 typ. 0.242 0.232 0.144 0.149 0.030 typ. 0.050 BSC 0.050 typ. 0.024 0.024 0.005 0.010 0.005 typ. 0.33 0.23 5.05 4.80 3.56 1.32 6.05 5.79 3.48 3.68 0.56 0.51 0.51 0.06 0° 0.15 0.246 0.236 0.151 0.154 0.028 0.028 0.008 12° 0.014 ECN: S17-0173-Rev. L, 13-Feb-17 DWG: 5881 Revison: 13-Feb-17 1 Document Number: 71655 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VISHAY SILICONIX www.vishay.com Power MOSFETs Application Note AN821 PowerPAK® SO-8 Mounting and Thermal Considerations by Wharton McDaniel MOSFETs for switching applications are now available with die on resistances around 1 m and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. In this application note, PowerPAK’s construction is described. Following this mounting information is presented including land patterns and soldering profiles for maximum reliability. Finally, thermal and electrical performance is discussed. PowerPAK SO-8 SINGLE MOUNTING The PowerPAK single is simple to use. The pin arrangement (drain, source, gate pins) and the pin dimensions are the same as standard SO-8 devices (see figure 2). Therefore, the PowerPAK connection pads match directly to those of the SO-8. The only difference is the extended drain connection area. To take immediate advantage of the PowerPAK SO-8 single devices, they can be mounted to existing SO-8 land patterns. THE PowerPAK PACKAGE The PowerPAK package was developed around the SO-8 package (figure 1). The PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the standard SO-8. This allows PowerPAK to be substituted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8 utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard SO-8. In fact, this larger die is slightly larger than a full sized DPAK die. The bottom of the die attach pad is exposed for the purpose of providing a direct, low resistance thermal path to the substrate the device is mounted on. Finally, the package height is lower than the standard SO-8, making it an excellent choice for applications with space constraints. Standard SO-8 PowerPAK SO-8 Fig. 2 The minimum land pattern recommended to take full advantage of the PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK SO-8 single in the index of this document. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. Fig. 1 Revision: 16-Mai-13 PowerPAK 1212 Devices Document Number: 71622 1 For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight and layer stack, experiments have found that more than about 0.25 in2 to 0.5 in2 of additional copper (in addition to the drain land) will yield little improvement in thermal performance. Application Note AN821 www.vishay.com Vishay Siliconix PowerPAK® SO-8 Mounting and Thermal Considerations PowerPAK SO-8 DUAL The pin arrangement (drain, source, gate pins) and the pin dimensions of the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore, the PowerPAK device connection pads match directly to those of the SO-8. As in the single-channel package, the only exception is the extended drain connection area. Manufacturers can likewise take immediate advantage of the PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land patterns. For the lead (Pb)-free www.vishay.com/doc?73257. solder profile, see To take the advantage of the dual PowerPAK SO-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document. The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the PowerPAK SO-8 dual package. Fig. 3 Solder Reflow Temperature Profile REFLOW SOLDERING Ramp-Up Rate Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in figures 3 and 4. Temperature at 150 - 200 °C + 3 °C /s max. 120 s max. Temperature Above 217 °C 60 - 150 s Maximum Temperature 255 + 5/- 0 °C Time at Maximum Temperature 30 s Ramp-Down Rate + 6 °C/s max. 30 s 260 °C 3 °C(max) 6 °C/s (max.) 217 °C 150 - 200 °C APPLICATION NOTE 150 s (max.) 60 s (min.) Pre-Heating Zone Reflow Zone Maximum peak temperature at 240 °C is allowed. Fig. 4 Solder Reflow Temperatures and Time Durations Revision: 16-Mai-13 Document Number: 71622 2 For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note AN821 www.vishay.com Vishay Siliconix PowerPAK® SO-8 Mounting and Thermal Considerations THERMAL PERFORMANCE Introduction A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, RthJC, or the junction-to-foot thermal resistance, RthJF This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the DPAK, PowerPAK SO-8, and standard SO-8. The PowerPAK has thermal performance equivalent to the DPAK, while having an order of magnitude better thermal performance over the SO-8. TABLE 1 - DPAK AND POWERPAK SO-8 EQUIVALENT STEADY STATE PERFORMANCE Thermal Resistance RthJC DPAK PowerPAK SO-8 Standard SO-8 1.2 °C/W 1 °C/W 16 °C/W Thermal Performance on Standard SO-8 Pad Pattern Because of the common footprint, a PowerPAK SO-8 can be mounted on an existing standard SO-8 pad pattern. The question then arises as to the thermal performance of the PowerPAK device under these conditions. A characterization was made comparing a standard SO-8 and a PowerPAK device on a board with a trough cut out underneath the PowerPAK drain pad. This configuration restricted the heat flow to the SO-8 land pads. The results are shown in figure 5. Because of the presence of the trough, this result suggests a minimum performance improvement of 10 °C/W by using a PowerPAK SO-8 in a standard SO-8 PC board mount. The only concern when mounting a PowerPAK on a standard SO-8 pad pattern is that there should be no traces running between the body of the MOSFET. Where the standard SO-8 body is spaced away from the pc board, allowing traces to run underneath, the PowerPAK sits directly on the pc board. Thermal Performance - Spreading Copper Designers may add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. Figure 6 shows the thermal resistance of a PowerPAK SO-8 device mounted on a 2-in. 2-in., four-layer FR-4 PC board. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.3 to 0.4 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed. Rth vs. Spreading Copper (0 %, 50 %, 100 % Back Copper) 56 Si4874DY vs. Si7446DP PPAK on a 4-Layer Board SO-8 Pattern, Trough Under Drain Impedance (C/watts) 60 Impedance (C/watts) APPLICATION NOTE 50 40 Si4874DY 30 51 46 100 % 41 Si7446DP 0% 20 50 % 36 10 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Spreading Copper (sq in) 0 0.0001 0.01 1 100 10000 Fig. 6 Spreading Copper Junction-to-Ambient Performance Pulse Duration (sec) Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path Revision: 16-Mai-13 Document Number: 71622 3 For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note AN821 www.vishay.com Vishay Siliconix PowerPAK® SO-8 Mounting and Thermal Considerations SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8 In any design, one must take into account the change in MOSFET RDS(on) with temperature (figure 7). On-Resistance vs. Junction Temperature R DS(on) - On-Resistance ( ) (Normalized) 1.8 VGS = 10 V ID = 23 A 1.6 1.2 Minimizing the thermal rise above the board temperature by using PowerPAK has not only eased the thermal design but it has allowed the device to run cooler, keep rDS(on) low, and permits the device to handle more current than the same MOSFET die in the standard SO-8 package. 1.0 CONCLUSIONS 1.4 PowerPAK SO-8 has been shown to have the same thermal performance as the DPAK package while having the same footprint as the standard SO-8 package. The PowerPAK SO-8 can hold larger die approximately equal in size to the maximum that the DPAK can accommodate implying no sacrifice in performance because of package limitations. 0.8 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) Fig. 7 MOSFET RDS(on) vs. Temperature A MOSFET generates internal heat due to the current passing through the channel. This self-heating raises the junction temperature of the device above that of the PC board to which it is mounted, causing increased power dissipation in the device. A major source of this problem lies in the large values of the junction-to-foot thermal resistance of the SO-8 package. PowerPAK SO-8 minimizes the junction-to-board thermal resistance to where the MOSFET die temperature is very close to the temperature of the PC board. Consider two devices mounted on a PC board heated to 105 °C by other components on the board (figure 8). PowerPAK SO-8 APPLICATION NOTE Suppose each device is dissipating 2.7 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK SO-8 and the standard SO-8, the die temperature is determined to be 107 °C for the PowerPAK (and for DPAK) and 148 °C for the standard SO-8. This is a 2 °C rise above the board temperature for the PowerPAK and a 43 °C rise for the standard SO-8. Referring to figure 7, a 2 °C difference has minimal effect on RDS(on) whereas a 43 °C difference has a significant effect on RDS(on). Recommended PowerPAK SO-8 land patterns are provided to aid in PC board layout for designs using this new package. Thermal considerations have indicated that significant advantages can be gained by using PowerPAK SO-8 devices in designs where the PC board was laid out for the standard SO-8. Applications experimental data gave thermal performance data showing minimum and typical thermal performance in a SO-8 environment, plus information on the optimum thermal performance obtainable including spreading copper. This further emphasized the DPAK equivalency. PowerPAK SO-8 therefore has the desired small size characteristics of the SO-8 combined with the attractive thermal characteristics of the DPAK package. Standard SO-8 107 °C 0.8 °C/W 148 °C 16 C/W PC Board at 105 °C Fig. 8 Temperature of Devices on a PC Board Revision: 16-Mai-13 Document Number: 71622 4 For technical questions, contact: powermosfettechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single 0.260 (6.61) 0.150 (3.81) 0.050 0.174 (4.42) 0.154 (1.27) 0.026 (0.66) (3.91) 0.024 (0.61) 0.050 0.032 0.040 (1.27) (0.82) (1.02) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72599 Revision: 21-Jan-08 www.vishay.com 15 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000