New Product
SiS414DN
Vishay Siliconix
N-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
RDS(on) (Ω)
ID (A)a, g
0.016 at VGS = 4.5 V
20
0.020 at VGS = 2.5 V
20
VDS (V)
30
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• 100 % UIS Tested
• Compliant to RoHS Directive 2002/95/EC
Qg (Typ.)
8.2 nC
PowerPAK® 1212-8
S
3.30 mm
APPLICATIONS
3.30 mm
1
2
S
3
D
• Synchronous DC/DC Converter
• System Power, Load Switch for
Notebook
S
G
4
D
8
D
G
7
D
6
D
5
Bottom View
S
N-Channel MOSFET
Ordering Information: SiS414DN-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Symbol
VDS
Limit
Gate-Source Voltage
VGS
± 12
TC = 70 °C
20g
ID
TA = 25 °C
10.8b, c
Pulsed Drain Current
IDM
50
Avalanche Current
IAS
10
Continuous Source-Drain Diode Current
L = 0.1 mH
EAS
TC = 25 °C
IS
TA = 25 °C
A
3.0b, c
31
TC = 70 °C
20
PD
TA = 25 °C
W
3.4b, c
2.2b, c
TA = 70 °C
Operating Junction and Storage Temperature Range
mJ
5
20g
TC = 25 °C
Maximum Power Dissipation
A
8.7b, c
TA = 70 °C
Avalanche Energy
V
20g
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
Unit
30
TJ, Tstg
- 55 to 150
Soldering Recommendations (Peak Temperature)d, e
°C
260
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Case (Drain)
Symbol
Typical
Maximum
t ≤ 10 s
RthJA
29
36
Steady State
RthJC
3.3
4.0
Unit
°C/W
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See solder profile (www.vishay.com/ppg?73257). The PowerPAK 1212 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 81 °C/W.
g. Package limited.
Document Number: 66588
S10-1047-Rev. A, 03-May-10
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1
New Product
SiS414DN
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 250 µA
30
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
ΔVDS/TJ
ID = 250 µA
VGS(th) Temperature Coefficient
ΔVGS(th)/TJ
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS , ID = 250 µA
IGSS
Gate-Source Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
Forward Transconductancea
RDS(on)
gfs
V
32
mV/°C
- 3.5
1.5
V
VDS = 0 V, VGS = ± 12 V
± 100
nA
VDS = 30 V, VGS = 0 V
1
VDS = 30 V, VGS = 0 V, TJ = 55 °C
5
VDS ≥ 5 V, VGS = 4.5 V
0.6
20
µA
A
VGS = 4.5 V, ID = 10 A
0.013
0.016
VGS = 2.5 V, ID = 6 A
0.016
0.020
VDS = 15 V, ID = 10 A
50
VDS = 15 V, VGS = 0 V, f = 1 MHz
135
VDS = 15 V, VGS = 10 V, ID = 10 A
22
33
8.2
13
Ω
S
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Rg
795
67
VDS = 15 V, VGS = 4.5 V, ID = 10 A
1.3
f = 1 MHz
VDD = 15 V, RL = 1.5 Ω
ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω
0.5
2.7
5.4
7
14
13
26
21
40
tf
8
16
td(on)
12
24
td(off)
tr
td(off)
nC
1.9
td(on)
tr
pF
VDD = 15 V, RL = 1.5 Ω
ID ≅ 10 A, VGEN = 4.5 V, Rg = 1 Ω
tf
54
100
26
50
10
20
Ω
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
TC = 25 °C
20
50
IS = 5 A, VGS = 0 V
0.77
1.1
A
V
Body Diode Reverse Recovery Time
trr
13
26
ns
Body Diode Reverse Recovery Charge
Qrr
5
10
nC
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
IF = 5 A, dI/dt = 100 A/µs, TJ = 25 °C
7
6
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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2
Document Number: 66588
S10-1047-Rev. A, 03-May-10
New Product
SiS414DN
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
50
V GS = 5 V thru 2.5 V
8
I D - Drain Current (A)
I D - Drain Current (A)
40
V GS = 2 V
30
20
6
T C = 25 °C
4
2
10
T C = 125 °C
V GS = 1.5 V
T C = - 55 °C
0
0.0
0.5
1.0
1.5
2.0
0
0.0
2.5
0.5
2.0
2.5
Transfer Characteristics
0.030
1200
0.026
960
Ciss
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
Output Characteristics
0.022
V GS = 2.5 V
720
480
Coss
V GS = 4.5 V
0.014
1.5
V GS - Gate-to-Source Voltage (V)
V DS - Drain-to-Source Voltage (V)
0.018
1.0
240
Crss
0
0.010
0
10
20
30
40
0
50
12
18
24
ID - Drain Current (A)
V DS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
10
ID = 10 A
1.6
V DS = 10 V
6
V DS = 15 V
V DS = 20 V
4
2
V GS = 4.5 V
1.4
(Normalized)
R DS(on) - On-Resistance
8
0
0.0
30
1.8
ID = 10 A
VGS - Gate-to-Source Voltage (V)
6
V GS = 2.5 V
1.2
1.0
0.8
4.4
8.8
13.2
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 66588
S10-1047-Rev. A, 03-May-10
17.6
22.0
0.6
- 50
- 25
0
25
50
75
100
125
150
T J - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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New Product
SiS414DN
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
0.070
10
0.056
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
ID = 10 A
T J = 150 °C
1
T J = 25 °C
0.1
0.01
0.028
T J = 125 °C
0.4
0.6
0.8
1.0
1.2
0
1
2
3
4
V SD - Source-to-Drain Voltage (V)
V GS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.4
100
0.2
80
0
60
ID = 5 mA
- 0.2
- 0.4
- 0.6
- 50
T J = 25 °C
0.014
0.000
0.2
0
25
50
75
100
5
40
20
ID = 250 μA
- 25
Power (W)
VGS(th) Variance (V)
0.001
0.0
0.042
125
150
0
0.001
0.01
0.1
1
10
Time (s)
T J - Temperature (°C)
Single Pulse Power (Junction-to-Ambient)
Threshold Voltage
100
Limited by RDS(on) *
I D - Drain Current (A)
10
1 ms
10 ms
1
100 ms
0.1
1s
10 s
TA = 25 °C
Single Pulse
DC
BVDSS Limited
0.01
0.1
1
10
100
V DS - Drain-to-Source Voltage (V)
* V GS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
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4
Document Number: 66588
S10-1047-Rev. A, 03-May-10
New Product
SiS414DN
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
40
I D - Drain Current (A)
32
24
Package Limited
16
8
0
0
25
50
75
100
125
150
T C - Case Temperature (°C)
40
2.0
32
1.6
24
1.2
Power (W)
Power (W)
Current Derating*
16
0.8
0.4
8
0.0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
T C - Case Temperature (°C)
TA - Ambient Temperature (°C)
Power, Junction-to-Case
Power, Junction-to-Ambient
150
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 66588
S10-1047-Rev. A, 03-May-10
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5
New Product
SiS414DN
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 81 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
Single Pulse
0.01
10 -4
10 -3
4. Surface Mounted
10 -2
10 -1
1
100
10
1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?66588.
www.vishay.com
6
Document Number: 66588
S10-1047-Rev. A, 03-May-10
Package Information
www.vishay.com
Vishay Siliconix
D4
PowerPAK® 1212-8, (Single / Dual)
W
H
E2
E4
L
K
M
θ
e
1
Z
D5
D
D2
2
2
D1
8
1
5
4
θ
4
b
3
L1
E3
A1
Backside view of single pad
H
2
E1
E
Detail Z
L
K
E2
E4
D2 D3(2x) D4
c
A
H
1
D1
2
K1
Notes
1. Inch will govern
2 Dimensions exclusive of mold gate burrs
3. Dimensions exclusive of mold flash and cutting burrs
D2
3
4
b
θ
D5
θ
E3
Backside view of dual pad
DIM.
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.97
1.04
1.12
0.038
0.041
0.044
A1
0.00
-
0.05
0.000
-
0.002
b
0.23
0.30
0.41
0.009
0.012
0.016
c
0.23
0.28
0.33
0.009
0.011
0.013
D
3.20
3.30
3.40
0.126
0.130
0.134
D1
2.95
3.05
3.15
0.116
0.120
0.124
D2
1.98
2.11
2.24
0.078
0.083
0.088
D3
0.48
-
0.89
0.019
-
0.035
D4
0.47 typ.
D5
2.3 typ.
0.0185 typ
0.090 typ
E
3.20
3.30
3.40
0.126
0.130
0.134
E1
2.95
3.05
3.15
0.116
0.120
0.124
E2
1.47
1.60
1.73
0.058
0.063
0.068
E3
1.75
1.85
1.98
0.069
0.073
0.078
E4
0.034 typ.
0.013 typ.
e
0.65 BSC
0.026 BSC
K
0.86 typ.
K1
0.35
-
0.034 typ.
-
0.014
-
-
H
0.30
0.41
0.51
0.012
0.016
0.020
L
0.30
0.43
0.56
0.012
0.017
0.022
L1
0.06
0.13
0.20
0.002
0.005
0.008
0°
-
12°
0°
-
12°
W
0.15
0.25
0.36
0.006
0.010
0.014
M
0.125 typ.
0.005 typ.
ECN: S16-2667-Rev. M, 09-Jan-17
DWG: 5882
Revison: 09-Jan-17
Document Number: 71656
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN822
Vishay Siliconix
PowerPAK® 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvious that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.
Figure 1. PowerPAK 1212 Devices
Document Number 71681
03-Mar-06
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1
AN822
Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance.
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera-
Ramp-Up Rate
+ 6 °C /Second Maximum
Temperature at 155 ± 15 °C
120 Seconds Maximum
Temperature Above 180 °C
70 - 180 Seconds
Maximum Temperature
240 + 5/- 0 °C
Time at Maximum Temperature
20 - 40 Seconds
Ramp-Down Rate
+ 6 °C/Second Maximum
Figure 2. Solder Reflow Temperature Profile
10 s (max)
210 - 220 °C
3 ° C/s (max)
4 ° C/s (max)
183 °C
140 - 170 °C
50 s (max)
3° C/s (max)
60 s (min)
Pre-Heating Zone
Reflow Zone
Maximum peak temperature at 240 °C is allowed.
Figure 3. Solder Reflow Temperatures and Time Durations
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2
Document Number 71681
03-Mar-06
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
SO-8
TSSOP-8
TSOP-8
PPAK 1212
PPAK SO-8
Configuration
Single
Dual
Single
Dual
Single
Dual
Single
Dual
Single
Dual
Thermal Resiatance RthJC(C/W)
20
40
52
83
40
90
2.4
5.5
1.8
5.5
PowerPAK 1212
Standard SO-8
49.8 °C
2.4 °C/W
Standard TSSOP-8
85 °C
20 °C/W
TSOP-6
149 °C
52 °C/W
125 °C
40 °C/W
PC Board at 45 °C
Figure 4. Temperature of Devices on a PC Board
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4).
Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many applications. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No significant effect was observed.
Document Number 71681
03-Mar-06
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3
AN822
Vishay Siliconix
130
105
Spreading Copper (sq. in.)
Spreading Copper (sq. in.)
120
95
110
100
RthJ A (°C/W)
RthJA (°C/W)
85
75
65
90
80
50 %
100 %
70
100 %
55
0%
60
50 %
0%
50
45
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Figure 5. Spreading Copper - Si7401DN
Figure 6. Spreading Copper - Junction-to-Ambient Performance
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
1212-8 uses the same packaging technology and has
been shown to have the same level of thermal performance while having a footprint that is more than 40 %
smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal
rise above the board temperature, PowerPAK simplifies
thermal design considerations, allows the device to run
cooler, keeps rDS(ON) low, and permits the device to
handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages.
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4
Document Number 71681
03-Mar-06
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single
0.152
(3.860)
0.039
0.068
(0.990)
(1.725)
0.010
(0.255)
(2.390)
0.094
0.088
(2.235)
0.016
(0.405)
0.026
(0.660)
0.025
0.030
(0.635)
(0.760)
Recommended Minimum Pads
Dimensions in Inches/(mm)
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APPLICATION NOTE
Document Number: 72597
Revision: 21-Jan-08
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7
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Vishay
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