TP0610K-T1-E3

TP0610K Vishay Siliconix P-Channel 60 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) RDS(on) () VGS(th) (V) ID (mA) - 60 6 at VGS = - 10 V - 1 to - 3 - 185 TO-236 (SOT-23) G Marking Code: 6Kwll 6K = Part Number Code for TP0610K w = Week Code ll = Lot Traceability 1 3 S D 2 Top View Ordering Information: TP0610K-T1-E3 (Lead (Pb)-free) TP0610K-T1-GE3 (Lead (Pb)-free and Halogen-free) • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • High-Side Switching • Low On-Resistance: 6  • Low Threshold: - 2 V (typ.) • Fast Swtiching Speed: 20 ns (typ.) • Low Input Capacitance: 20 pF (typ.) • 2000 V ESD Protection • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • Drivers: Relays, Solenoids, Lamps, Hammers, Display, Memories, Transistors, etc. • Battery Operated Systems • Power Supply Converter Circuits • Solid-State Relays BENEFITS • • • • • Ease in Driving Switches Low Offset (Error) Voltage Low-Voltage Operation High-Speed Circuits Easily Driven without Buffer ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol Limit Drain-Source Voltage VDS - 60 Gate-Source Voltage VGS ± 20 Continuous Drain Currenta TA = 25 °C TA = 100 °C Pulsed Drain Currentb Power Dissipationa Maximum Junction-to-Ambienta Operating Junction and Storage Temperature Range ID IDM TA = 25 °C TA = 100 °C PD Unit V - 185 - 115 mA - 800 350 140 mW RthJA 350 °C/W TJ, Tstg - 55 to 150 °C Notes: a. Surface mounted on FR4 board. b. Pulse width limited by maximum junction temperature. Document Number: 71411 S10-1476-Rev. H, 05-Jul-10 www.vishay.com 1 TP0610K Vishay Siliconix SPECIFICATIONS TA = 25 °C, unless otherwise noted Limits Parameter Symbol Test Conditions Min. VDS VGS = 0 V, ID = - 10 µA - 60 VGS(th) VDS = VGS, ID = - 250 µA -1 Typ.a Max. Unit Static Drain-Source Breakdown Voltage Gate-Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Currenta Drain-Source On-Resistancea IGSS IDSS ID(on) RDS(on) -3 VDS = 0 V, VGS = ± 20 V ± 10 VDS = 0 V, VGS = ± 10 V ± 200 VDS = 0 V, VGS = ± 10 V, TJ = 85 °C ± 500 VDS = 0 V, VGS = ± 5 V ± 100 VDS = - 60 V, VGS = 0 V - 25 VDS = - 60 V, VGS = 0 V, TJ = 85 °C - 50 VGS = - 10 V, VDS = - 10 V - 600 VGS = - 4.5 V, ID = - 25 mA 10 6 Diode Forward Voltage VDS = - 10 V, ID = - 100 mA VSD IS = - 200 mA, VGS = 0 V nA mA VGS = - 10 V, ID = - 500 mA gfs µA - 250 VGS = - 10 V, VDS = - 4.5 V VGS = - 10 V, ID = - 500 mA, TJ =125 °C Forward Transconductancea V  9 80 mS - 1.4 V Dynamic Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 1.7 VDS = - 30 V, VGS = - 15 V ID  - 500 mA 0.26 VDS = - 25 V, VGS = 0 V f = 1 MHz 10 nC 0.46 23 pF 5 Switchingb Turn-On Time td(on) Turn-Off Time td(off) VDD = - 25 V, RL = 150  ID  - 200 mA, VGEN = - 10 V, Rg = 10  20 35 ns Notes: a. Pulse test: PW  300 µs duty cycle  2 %. b. Switching time is essentially independent of operating temperature. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 71411 S10-1476-Rev. H, 05-Jul-10 TP0610K Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1.0 1200 VGS = 10 V TJ = - 55 °C 7V 0.8 I D - Drain Current (mA) ID - Drain Current (A) 8V 0.6 6V 0.4 5V 900 25 °C 125 °C 600 300 0.2 4V 0.0 0 0 1 2 3 4 5 0 2 VDS - Drain-to-Source Voltage (V) 4 6 8 10 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 40 20 VGS = 0 V VGS = 4.5 V 32 C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 16 12 VGS = 5 V 8 VGS = 10 V 4 Ciss 24 16 Coss 8 Crss 0 0 0 200 400 600 800 0 1000 5 ID - Drain Current (mA) 10 25 Capacitance 15 1.8 ID = 500 mA 1.5 12 VDS = 30 V RDS(on) - On-Resistance (Normalized) VGS - Gate-to-Source Voltage (V) 20 V DS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current VDS = 48 V 9 6 3 0 0.0 15 VGS = 10 V at 500 mA 1.2 VGS = 4.5 V at 25 mA 0.9 0.6 0.3 0.3 0.6 0.9 1.2 Qg - Total Gate Charge (nC) Gate Charge Document Number: 71411 S10-1476-Rev. H, 05-Jul-10 1.5 1.8 0.0 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature www.vishay.com 3 TP0610K Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 10 1000 RDS(on) - On-Resistance (Ω) I S - Source Current (A) VGS = 0 V 100 TJ = 125 °C 10 TJ = 25 °C 8 ID = 500 mA 6 4 ID = 200 mA 2 TJ = - 55 °C 0 1 0.00 0.3 0.6 0.9 1.2 V SD - Source-to-Drain Voltage (V) 0 1.5 4 6 8 10 VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-Source Voltage 0.5 3 0.4 2.5 ID = 250 µA 0.3 2 0.2 Power (W) VGS(th) Variance (V) 2 0.1 1.5 - 0.0 1 TA = 25 °C - 0.1 0.5 - 0.2 - 0.3 - 50 0 - 25 0 25 50 75 100 125 150 0.1 0.01 100 10 1 TJ - Junction Temperature (°C) Time (s) Threshold Voltage Variance Over Temperature Single Pulse Power, Junction-to-Ambient 600 Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 350 °C/W 0.02 3. TJM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (s) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71411. www.vishay.com 4 Document Number: 71411 S10-1476-Rev. H, 05-Jul-10 Package Information Vishay Siliconix SOT-23 (TO-236): 3-LEAD b 3 E1 1 E 2 e S e1 D 0.10 mm C 0.004" A2 A C q Gauge Plane Seating Plane Seating Plane C A1 Dim 0.25 mm L L1 MILLIMETERS Min INCHES Max Min Max 0.044 A 0.89 1.12 0.035 A1 0.01 0.10 0.0004 0.004 A2 0.88 1.02 0.0346 0.040 b 0.35 0.50 0.014 0.020 c 0.085 0.18 0.003 0.007 D 2.80 3.04 0.110 0.120 E 2.10 2.64 0.083 0.104 E1 1.20 1.40 0.047 e 0.95 BSC e1 L 1.90 BSC 0.40 L1 q 0.0748 Ref 0.60 0.016 0.64 Ref S 0.024 0.025 Ref 0.50 Ref 3° 0.055 0.0374 Ref 0.020 Ref 8° 3° 8° ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 Document Number: 71196 09-Jul-01 www.vishay.com 1 AN807 Vishay Siliconix Mounting LITTLE FOOTR SOT-23 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET footprint . In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. ambient air. This pattern uses all the available area underneath the body for this purpose. 0.114 2.9 0.081 2.05 0.150 3.8 0.059 1.5 0.0394 1.0 0.037 0.95 FIGURE 1. Footprint With Copper Spreading The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board. Figure 1 shows the footprint with copper spreading for the SOT-23 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the Document Number: 70739 26-Nov-03 Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device. www.vishay.com 1 Application Note 826 Vishay Siliconix 0.049 (1.245) 0.029 0.022 (0.559) (0.724) 0.037 (0.950) (2.692) 0.106 RECOMMENDED MINIMUM PADS FOR SOT-23 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72609 Revision: 21-Jan-08 www.vishay.com 25 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer  ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 08-Feb-17 1 Document Number: 91000