VCNL3036X01
www.vishay.com
Vishay Semiconductors
High Resolution Digital Proximity Sensor With I2C Interface
FEATURES
• Package type: surface-mount
• Dimensions (L x W x H in mm): 4.0 x 2.36 x 0.75
• AEC-Q101 qualified
• Integrated modules: proximity sensor (PS) and
signal conditioning IC
• Temperature compensation: -40 °C to +105 °C
• Low power consumption
compatible) interface
VDD
1
8
SDA
SCL
2
7
INT
GND
3
6
IRED1
IRED3
4
5
IRED2
I2C
(SMBus
• Output type: I2C bus
• Operation voltage: 2.5 V to 3.6 V
• Floor life: 168 h, MSL 3, according to J-STD-020
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
PROXIMITY FUNCTION
LINKS TO ADDITIONAL RESOURCES
3D 3D
3D Models
• Programmable IRED sink current
• Intelligent cancellation to reduce cross talk phenomenon
T
Design Tools
• Smart persistence scheme to reduce PS response time
Technical
Notes
• Selectable for 12-bit / 16-bit PS output data
DESCRIPTION
VCNL3036X01 integrates a proximity sensor (PS), a mux,
and a driver for up to 3 external IREDs into one small
package. It incorporates photodiodes, amplifiers, and
analog to digital converting circuits into a single chip by
CMOS process. PS programmable interrupt features of
individual high and low thresholds offers the best utilization
of resource and power saving on the microcontroller.
INTERRUPT
• Programmable interrupt function for PS with upper and
lower thresholds
• Adjustable persistence to prevent false triggers for PS
APPLICATIONS
• Force feedback applications
• Proximity / optical switch for consumer, computing,
automotive, and industrial devices
PRODUCT SUMMARY
PART
NUMBER
OPERATING
RANGE (1)
(mm)
OPERATING
VOLTAGE
RANGE
(V)
I2C BUS
VOLTAGE
RANGE
(V)
IRED PULSE
CURRENT (2)
(mA)
SPECTRAL
BANDWIDTH
RANGE
λ0.5 (nm)
OUTPUT
CODE
ADC RESOLUTION
PROXIMITY /
AMBIENT LIGHT
0 to 500
2.5 to 3.6
1.8 to 5.5
200
500 to 910
16 bit, I2C
16 bit / -
VCNL3036X01
Notes
(1) Part should be operated in dark condition (not in direct sunlight)
(2) Adjustable through I2C interface
ORDERING INFORMATION
ORDERING CODE
VCNL3036X01-GS08
VCNL3036X01-GS18
PACKAGING
Tape and reel
VOLUME (1)
MOQ: 3300 pcs
MOQ: 13 000 pcs
REMARKS
4.0 mm x 2.36 mm x 0.75 mm
Note
MOQ: minimum order quantity
(1)
Rev. 1.0, 12-Aug-2020
Document Number: 84937
1
For technical questions, contact: sensorstechsupport@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Supply voltage
TEST CONDITION
VDD
2.5
3.6
V
Operation temperature range
Tamb
-40
+105
°C
Storage temperature range
Tstg
-40
+110
°C
RECOMMENDED OPERATING CONDITIONS (Tamb = 25 °C, unless otherwise specified)
PARAMETER
SYMBOL
MIN.
MAX.
Supply voltage
TEST CONDITION
VDD
2.5
3.6
UNIT
V
Operation temperature range
Tamb
-40
+105
°C
I2C bus operating frequency
f(I2CCLK)
10
400
kHz
PIN DESCRIPTIONS
PIN ASSIGNMENT
SYMBOL
TYPE
FUNCTION
1
VDD
-
Power supply input
2
SCL
I
I2C digital bus clock input
3
GND
-
Ground
4
IRED3
I
Cathode (IRED3) connection
5
IRED2
I
Cathode (IRED2) connection
6
IRED1
I
Cathode (IRED1) connection
7
INT
O
Interrupt pin
8
SDA
I / O (open drain)
I2C data bus data input / output
BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
PARAMETER
TEST CONDITION
Supply voltage
Excluded LED driving
Supply current
Light condition = dark, VDD = 3.3 V
I2C supply voltage
PS enable
Logic high
I2C signal input
Logic low
Logic high
Logic low
Full PS counts
PS detection range
VDD = 3.3 V
VDD = 2.6 V
SYMBOL
MIN.
TYP.
MAX.
VDD
2.5
-
3.6
UNIT
V
IDD
-
300
-
μA
μA
IDD (SD)
-
0.2
-
VPULL UP
1.8
-
5.5
V
IPSSD
-
200
-
μA
VIH
1.55
-
-
VIL
-
-
0.4
VIH
1.4
-
-
VIL
-
-
0.4
-
-
4096 /
65 535
steps
12-bit / 16-bit resolution
Kodak gray card (1)(2)
V
V
0
-
500
mm
-40
-
+105
°C
LED anode voltage
-
-
5.5
V
IRED driving current
-
-
200
mA
Operating temperature range
Tamb
Notes
(1) Depending on external IRED
(2) Part should be operated in dark condition (not in direct sunlight)
Rev. 1.0, 12-Aug-2020
Document Number: 84937
2
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL3036X01
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Vishay Semiconductors
I2C BUS TIMING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
PARAMETER
SYMBOL
Clock frequency
STANDARD MODE
MIN.
MAX.
f(SMBCLK)
10
t(BUF)
4.7
Hold time after (repeated) start condition;
after this period, the first clock is generated
t(HDSTA)
Repeated start condition setup time
FAST MODE
UNIT
MIN.
MAX.
100
10
400
kHz
-
1.3
-
μs
4.0
-
0.6
-
μs
t(SUSTA)
4.7
-
0.6
-
μs
Stop condition setup time
t(SUSTO)
4.0
-
0.6
-
μs
Data hold time
t(HDDAT)
-
3450
-
900
ns
Data setup time
Bus free time between start and stop condition
t(SUDAT)
250
-
100
-
ns
I2C clock (SCK) low period
t(LOW)
4.7
-
1.3
-
μs
I2C clock (SCK) high period
t(HIGH)
4.0
-
0.6
-
μs
Clock / data fall time
t(F)
-
300
-
300
ns
Clock / data rise time
t(R)
-
1000
-
300
ns
t(LOW)
I2C BUS
CLOCK
(SCL)
t(R)
t(F)
VIH
VIL
t(HDSTA)
t(HIGH)
t(SUSTA)
t(SUSTO)
t(BUF)
t(HDDAT)
I2C BUS
DATA
(SDA)
t(SUDAT)
VIH
VIL
{
P
Stop condition
{
{
S
Start condition
{
S
Start
P
Stop
t(LOSEXT)
SCLACK
t(LOWMEXT)
SDAACK
t(LOWMEXT)
t(LOWMEXT)
2
I C BUS
CLOCK
(SCL)
I2C BUS
DATA
(SDA)
Fig. 1 - I2C Bus Timing Diagram
Rev. 1.0, 12-Aug-2020
Document Number: 84937
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VCNL3036X01
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PARAMETER TIMING INFORMATION
I2C BUS
CLOCK
(SCL)
I2C BUS
DATA
(SDA)
SA7
SA5
SA6
SA4
SA3
W
SA1
SA2
Start by
master
SA7
SA6
SA5
SA4
SA3
SA1
SA2
SA0
ACK by
VCNL3036X01
ACK by
VCNL3036X01
2
I C bus slave address byte
Command code
I2C BUS
CLOCK
(SCL)
I2C BUS
DATA
(SDA)
SA7
SA6
SA4
SA5
SA2
SA3
SA7
SA0
SA1
SA6
SA4
SA5
SA3
SA2
SA1
SA0
Stop by
ACK by
VCNL3036X01 master
ACK by
VCNL3036X01
Data byte low
Data byte high
Fig. 2 - I2C Bus Timing for Sending Word Command Format
I2C BUS
CLOCK
(SCL)
I2C BUS
DATA
(SDA)
SA7
SA6
SA5
SA4
SA3
W
SA1
SA2
Start by
master
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ACK by
VCNL3036X01
ACK by
VCNL3036X01
Command code
2
I C bus slave address byte
I2C BUS
CLOCK
(SCL)
I2C BUS
DATA
(SDA)
SA7
SA6
SA5
SA4
SA3
SA2
R
SA1
Start by
master
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ACK by
master
ACK by
VCNL3036X01
Data byte low
2
I C bus slave address byte
I2C BUS
CLOCK
(SCL)
I2C BUS
DATA
(SDA)
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
NACK by
master
Stop by
master
Data byte high
Fig. 3 - I2C Bus Timing for Receiving Word Command Format
Rev. 1.0, 12-Aug-2020
Document Number: 84937
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For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL3036X01
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Vishay Semiconductors
TYPICAL PERFORMANCE CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Axis Title
Axis Title
0.22
10000
0.9
0.7
2nd line
IDD - Supply Current (mA)
0.8
1000
0.6
0.5
0.4
100
0.3
0.2
VDD = 3.6 V
0.20
VDD = 3.0 V
0.18
1000
1st line
2nd line
10000
1st line
2nd line
2nd line
S(λ)rel - Relative Spectral Sensitivity
1.0
0.16
VDD = 2.5 V
0.14
100
0.12
PS: active force mode enable
0.1
0
400
500
600
700
800
0.10
10
1000 1100
900
10
-40
-20
0
20
40
60
80
100 120
λ - Wavelength (nm)
2nd line
Tamb - Ambient Temperature (°C)
2nd line
Fig. 4 - Relative Spectral Sensitivity vs. Wavelength
(proximity sensor)
Fig. 5 - Supply Current vs. Ambient Temperature
APPLICATION INFORMATION
Pin Connection with the Host
VCNL3036X01 integrates proximity sensor and an LED driver with three inputs for external IREDs all together with I2C interface.
It is very easy for the baseband (CPU) to access PS output data via I2C interface without extra software algorithms. The
hardware schematic is shown in the following diagram.
VCNL3036X01
VDD
1
8 SDA
DSP
GND 3
7 INT
Oscillator
2
PS-PD
SCL
Output buffer
I2C interface
PS
data buffer
6 IRED1
Driver
Temperature
compensation
IRED3 4
5 IRED2
Fig. 6 - Detailed Block Diagram
Rev. 1.0, 12-Aug-2020
Document Number: 84937
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VCNL3036X01
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Vishay Semiconductors
Digital Interface
VCNL3036X01 applies single slave address 0x41 (HEX) of 7-bit addressing following I2C protocol. All operations can be
controlled by the command register. The simple command structure helps users easily program the operation setting and latch
the light data from VCNL3036X01. As Fig. 10 shows, VCNL3036X01’s I2C command format is simple for read and write
operations between VCNL3036X01 and the host. The white sections indicate host activity and the gray sections indicate
VCNL3036X01’s acknowledgement of the host access activity. Write word and read word protocol is suitable for accessing
registers particularly for 12-bit / 16-bit PS data. Interrupt can be cleared by reading data out from register: INT_Flag. All
command codes should follow read word and write word protocols.
Send Byte → Write Command to VCNL3036X01
1
7
1
1
8
1
8
1
8
1
1
S
Slave address
Wr
A
Command code
A
Data byte low
A
Data byte high
A
P
Receive Byte → Read Data from VCNL3036X01
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
Slave address
Wr
A
Command code
A
S
Slave address
Rd
A
Data byte low
A
Data byte high
N
P
S = start condition
P = stop condition
A = acknowledge
N = no acknowledge
Shaded area = VCNL3036X01 acknowledge
Fig. 7 - Write Word and Read Word Protocol
Rev. 1.0, 12-Aug-2020
Document Number: 84937
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL3036X01
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Vishay Semiconductors
Function Description
For proximity sensor function, VCNL3036X01 supports different kinds of mechanical designs to achieve the best proximity
detection performance for any color of object with more flexibility. The basic PS function settings, such as duty ratio, integration
time, interrupt, and PS enable / disable, and persistence, are handled by the register: PS_CONF1. Duty ratio controls the PS
response time. Integration time represents the duration of the energy being received. The interrupt is asserted when the PS
detection levels over the high threshold level setting (register: PS_THDH) or lower than low threshold (register: PS_THDL). If the
interrupt function is enabled, the host reads the PS output data from VCNL3036X01 that saves host loading from periodically
reading PS data. More than that, INT flag (register: INT_Flag) indicates the behavior of INT triggered under different conditions.
PS persistence (PS_PERS) sets up the PS INT asserted conditions as long as the PS output value continually exceeds the
threshold level. The intelligent cancellation level can be set on register: PS_CANC to reduce the cross talk phenomenon.
VCNL3036X01 also supports an easy use of proximity detection logic output mode that outputs just high / low levels saving
loading from the host. Normal operation mode or proximity detection logic output mode can be selected on the register: PS_MS.
A smart persistence is provided to get faster PS response time and prevent false trigger for PS. Descriptions of each slave
address operation are shown in table 1.
TABLE 1 - COMMAND CODE AND REGISTER DESCRIPTION
COMMAND
CODE
DATE BYTE
LOW / HIGH
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
REGISTER
NAME
R/W
DEFAULT
VALUE
FUNCTION DESCRIPTION
L
Reserved
R
0x01
Reserved
H
Reserved
R
0x01
Reserved
L
Reserved
R
0x00
Reserved
H
Reserved
R
0x00
Reserved
L
Reserved
R
0x00
Reserved
H
Reserved
R
0x00
Reserved
L
PS_CONF1
R/W
0x01
PS duty ratio, integration time, persistence, and PS enable / disable
H
PS_CONF2
R/W
0x00
PS gain, PS output resolution selection, PS interrupt trigger method
L
PS_CONF3
R/W
0x00
PS smart persistence, active force mode, IRED select
H
PS_MS
R/W
0x00
LED current selection
L
PS_CANC_L
R/W
0x00
PS cancellation level setting
H
PS_CANC_M
R/W
0x00
PS cancellation level setting
L
PS_THDL_L
R/W
0x00
PS low interrupt threshold setting LSB byte
H
PS_THDL_M
R/W
0x00
PS low interrupt threshold setting MSB byte
L
PS_THDH_L
R/W
0x00
PS high interrupt threshold setting LSB byte
H
PS_THDH_M
R/W
0x00
PS high interrupt threshold setting MSB byte
L
PS1_Data_L
R
0x00
PS1 LSB output data
H
PS1_Data_M
R
0x00
PS1 MSB output data
L
PS2_Data_L
R
0x00
PS2 LSB output data
H
PS2_Data_M
R
0x00
PS2 MSB output data
L
PS3_Data_L
R
0x00
PS3 LSB output data
H
PS3_Data_M
R
0x00
PS3 MSB output data
L
Reserved
R
0x00
Reserved
H
Reserved
R
0x00
Reserved
L
Reserved
R
0x00
Reserved
H
Reserved
R
0x00
Reserved
L
Reserved
R
0x00
Reserved
H
INT_Flag
R
0x00
PS interrupt flags
L
ID_L
R
0x80
Device ID LSB
H
ID_M
R
0x00
Device address: 0x41
Note
• All of reserved register are used for internal test. Please keep as default setting
Rev. 1.0, 12-Aug-2020
Document Number: 84937
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For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VCNL3036X01
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Command Register Format
VCNL3036X01 provides an 8-bit command register for PS controlling independently. The description of each command format
is shown in following tables.
TABLE 2 - REGISTER: RESERVED
REGISTER NAME
COMMAND CODE: 0x00_L (0x00 DATA BYTE LOW)
Command
Bit
Reserved
7:0
Description
Default = 01H
TABLE 3 - REGISTER: RESERVED
COMMAND CODE: 0x00_H (0x00 DATA BYTE HIGH)
Command
Bit
Reserved
7:0
Description
Default = 01H
TABLE 4 - REGISTER RESERVED
COMMAND CODE: 0x01_L (0x01 DATA BYTE LOW) AND 0x01_H (0x01 DATA BYTE HIGH)
Register
Bit
Reserved
7:0
Description
Reserved
TABLE 5 - REGISTER: RESERVED
COMMAND CODE: 0x02_L (0x02 DATA BYTE LOW) AND 0x02_H (0x02 DATA BYTE HIGH)
Register
Bit
Reserved
7:0
Description
Reserved
TABLE 6 - REGISTER: PS_CONF1 DESCRIPTION
REGISTER: PS_CONF1
Command
COMMAND CODE: 0x03_L (0x03 DATA BYTE LOW)
Bit
Description
PS_Duty
7:6
(0 : 0) = 1/40, (0 : 1) = 1/80, (1 : 0) = 1/160, (1 : 1) = 1/320
PS IRED on / off duty ratio setting
PS_PERS
5:4
(0 : 0) = 1, (0 : 1) = 2, (1 : 0) = 3, (1 : 1) = 4
PS interrupt persistence setting
PS_ IT
3:1
(0 : 0 : 0) = 1T, (0 : 0 : 1) = 1.5T, (0 : 1 : 0) = 2T, (0 : 1 : 1) = 2.5T, (1 : 0 : 0) = 3T, (1 : 0 : 1) = 3.5T,
(1 : 1 : 0) = 4T, (1 : 1 : 1) = 8T, PS integration time setting
PS_SD
0
0 = PS power on, 1 = PS shut down, default = 1
TABLE 7 - REGISTER: PS_CONF2 DESCRIPTION
REGISTER: PS_CONF2
Command
COMMAND CODE: 0x03_H (0x03 DATA BYTE HIGH)
Bit
Description
MPX_INT_EN
7
0 = disabled, 1 = enabled
MPX_MODE
6
0 = disabled, 1 = enabled
PS_Gain
5:4
(0 : 0) and (0 : 1) = two step mode, (1: 0) single mode x 8, (1 : 1) single mode x 1
PS_HD
3
0 = PS output is 12 bits, 1 = PS output is 16 bits
PS_NS
2
(0 : 0) and (0 : 1) = two step mode, (1: 0) single mode x 8, (1 : 1) single mode x 1
PS_INT
1:0
Rev. 1.0, 12-Aug-2020
(0 : 0) = interrupt disable, (0 : 1) = trigger by closing, (1 : 0) = trigger by away,
(1 : 1) = trigger by closing and away
Document Number: 84937
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TABLE 8 - REGISTER: PS_CONF3 DESCRIPTION
REGISTER: PS_CONF3
Command
COMMAND CODE: 0x04_L (0x04 DATA BYTE LOW)
Bit
LED_I_LOW
7
IRED select
6:5
Description
0 = disabled = normal current, 1 = enabled = 1/10 of normal current,
with that the current is accordingly: 5 mA, 7.5 mA, 10 mA, 12 mA, 14 mA, 16 mA, 18 mA, 20 mA
(0 : 0) = IRED1, (0 : 1) = IRED2, (1 : 0) = IRED3, (1 : 1) = IRED3
PS_SMART_PERS
4
0 = disable; 1 = enable PS smart persistence
PS_AF
3
0 = active force mode disable (normal mode), 1 = active force mode enable
PS_TRIG
2
0 = no PS active force mode trigger, 1 = trigger one time cycle
VCNL3036X01 output one cycle data every time host writes in ‘1’ to sensor.
The state returns to ‘0’ automatically.
PS_MS
1
0 = proximity normal operation with interrupt function
1 = proximity detection logic output mode enable
PS_SC_EN
0
0 = turn off sunlight cancel; 1 = turn on sunlight cancel
PS sunlight cancel function enable setting
TABLE 9 - REGISTER: PS_MS DESCRIPTION
REGISTER: PS_MS
COMMAND CODE: 0x04_H (0x04 DATA BYTE HIGH)
Command
Bit
Reserved
7
PS_SC_CUR
6:5
Description
0
(0 : 0) = 1 x typical sunlight cancel current, (0 : 1) = 2 x typical sunlight cancel current,
(1 : 0) = 4 x typical sunlight cancel current, (1 : 1) = 8 x typical sunlight cancel current
PS_SP
4
0 = typical sunlight capability, 1 = 1.5 x typical sunlight capability
PS_SPO
3
0 = output is 00h in sunlight protect mode, 1 = output is FFh in sunlight protect mode,
LED_I
2:0
(0 : 0 : 0) = 50 mA; (0 : 0 : 1) = 75 mA; (0 : 1 : 0) = 100 mA; (0 : 1 : 1) = 120 mA
(1 : 0 : 0) = 140 mA; (1 : 0 : 1) = 160 mA; (1 : 1 : 0) = 180 mA; (1 : 1 : 1) = 200 mA
LED current selection setting
TABLE 10 - REGISTER PS_CANC_L AND PS_CANC_M DESCRIPTION
COMMAND CODE: 0x05_L (0x05 DATA BYTE LOW) AND 0x05_H (0x05 DATA BYTE HIGH)
Register
Bit
Description
PS_CANC_L
7:0
0x00 to 0xFF, PS cancellation level setting_LSB byte
PS_CANC_M
7:0
0x00 to 0xFF, PS cancellation level setting_MSB byte
TABLE 11 - REGISTER: PS_THDL_L AND PS_THDL_M DESCRIPTION
COMMAND CODE: 0x06_L (0x06 DATA BYTE LOW) AND 0x06_H (0x06 DATA BYTE HIGH)
Register
Bit
Description
PS_THDL_L
7:0
0x00 to 0xFF, PS interrupt low threshold setting_LSB byte
PS_THDL_M
7:0
0x00 to 0xFF, PS interrupt low threshold setting_MSB byte
TABLE 12 - REGISTER: PS_THDH_L AND PS_THDH_M DESCRIPTION
COMMAND CODE: 0x07_L (0x07 DATA BYTE LOW) AND 0x07_H (0x07 DATA BYTE HIGH)
Register
Bit
Description
PS_THDH_L
7:0
0x00 to 0xFF, PS interrupt high threshold setting_LSB byte
PS_THDH_M
7:0
0x00 to 0xFF, PS interrupt high threshold setting_MSB byte
Rev. 1.0, 12-Aug-2020
Document Number: 84937
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TABLE 13 - READ OUT REGISTER DESCRIPTION
Register
PS1_Data_L
Command Code
Bit
Description
0x08_L (0x08 data byte low)
7:0
0x00 to 0xFF, PS1 LSB output data
PS1_Data_M
0x08_H (0x08 data byte high)
7:0
0x00 to 0xFF, PS1 MSB output data
PS2_Data_L
0x09_L (0x09 data byte low)
7:0
0x00 to 0xFF, PS2 LSB output data
PS2_Data_M
0x09_H (0x09 data byte high)
7:0
0x00 to 0xFF, PS2 MSB output data
PS3_Data_L
0x0A_L (0x0A data byte low)
7:0
0x00 to 0xFF, PS3 LSB output data
PS3_Data_M
0x0A_H (0x0A data byte high)
7:0
0x00 to 0xFF, PS3 MSB output data
Reserved
0x0B_L (0x0B data byte low)
7:0
Reserved
Reserved
0x0B_H (0x0B data byte high)
7:0
Reserved
Reserved
0x0C_L (0x0C data byte low)
7:0
Reserved
Reserved
0x0C_H (0x0C data byte high)
7:0
Reserved
Reserved
0x0D_L (0x0D data byte low)
7:0
INT_Flag
0x0D_H (0x0D data byte high)
MPX_DATA_READY_FLAG
6
PS_SPFLAG, PS entering protection mode
5:2
1
0
ID_L
0x0E_H (0x0E data byte low)
ID_M
0x0E_H (0x0E data byte high)
Default = 0x00
7
Reserved
PS_IF_CLOSE, PS rises above PS_THDH INT trigger event
PS_IF_AWAY, PS drops below PS_THDL INT trigger event
7:0
0x80
7:6
(0 : 0)
5:4
(0 : 0) Slave address = 0x41 (7-bit)
3:0
Version code (0 : 0 : 0 : 0)
Adjustable Sampling Time
VCNL3036X01’s embedded IRED driver drives up to 3 external IREDs by a pulsed duty cycle. The IRED on / off duty ratio is
programmable by I2C command at register: PS_Duty which is related to the current consumption and PS response time.
The higher the duty ratio adopted, the faster response time achieved with higher power consumption. For example,
PS_Duty = 1/320, peak IRED current = 100 mA, averaged current consumption is 100 mA/320 = 0.3125 mA.
Initialization
VCNL3036X01 includes default values for each register. As long as power is on, it is ready to be controlled by host via I2C bus.
Threshold Window Setting
• Programmable PS Threshold
VCNL3036X01 provides both high and low thresholds for PS (register: PS_THDL, PS_THDH)
• PS Persistence
The PS persistence function (PS_PERS, 1, 2, 3, 4) helps to avoid false trigger of the PS INT. For example, if
PS_PERS = 3 times, the PS INT will not be asserted unless the PS value is greater than the PS threshold (PS_THDH) value
for three periods of time continuously
• PS Active Force Mode
An extreme power saving way to use PS is to apply PS active force (register: PS_CONF3 command: PS_FOR = 1) mode.
Anytime host would like to read out just one of PS data, write in ‘1’ at register: PS_CONF3 command: PS_FOR_Trig. Without
commands placed, there is no PS data output. VCNL3036X01 stays in standby mode constantly
Intelligent Cancellation
VCNL3036X01 provides an intelligent cancellation method to reduce cross talk phenomenon for the proximity sensor. The
output data will be subtracted by the input value on register: PS_CANC.
Rev. 1.0, 12-Aug-2020
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Interruption (INT)
VCNL3036X01 has PS interrupt feature operated by a single pin “INT”. The purpose of the interrupt feature is to actively inform
the host once INT has been asserted. With the interrupt function applied, the host does not need to be constantly pulling data
from the sensor, but to read data from the sensor while receiving interrupt request from the sensor. As long as the host
enables
PS interrupt (register: PS_INT) function, the level of INT pin (pin 7) is pulled low once INT asserted. All registers are
accessible even if INT is asserted.
To effectively adopt PS INT function, it is recommended to use PS detection mechanism at register: PS_INTT = 1 for the best
PS detection performance which can be adjusted by high / low THD level of PS. PS INT trigger way is defined by register:
PS_INT.
Interruption Flag
Register: INT_Flag represents all of interrupt trigger status for PS. Any flag value changes from “0” to “1” state, the level of INT
pin will be pulled low. As long as host reads INT_Flag data, the bit will change from “1” state to “0” state after reading out, the
INT level will be returned to high afterwards.
PROXIMITY DETECTION LOGIC OUTPUT MODE
VCNL3036X01 provides a proximity detection logic output mode that uses INT pin (pin 7) as a proximity detection logic high /
low output (register: PS_MS). When this mode is selected, the PS output (pin 7; INT/Pout) is pulled low when an object is closing
to be detected and returned to level high when the object moves away. Register: PS_THDH / PS_THDL defines how sensitive
PS detection is.
One thing to be stated is that whenever proximity detection logic mode applied, INT pin is only used as a logic high / low output.
Meanwhile, host has to simulate the GPIO pin as an INT pin function. If not, host needs to periodically reading the state
of INT at this GPIO pin.
PROXIMITY DETECTION HYSTERESIS
A PS detection hysteresis is important that keeps PS state in a certain range of detection distance. For example, PS INT asserts
when PS value over PS_THDH. Host switches off panel backlight and then clears INT. When PS value is less than PS_THDL,
host switches on panel backlight. Any PS value lower than PS_THDH or higher than PS_THDL, PS INT will not be asserted. Host
does keep the same state.
MULTIPLEX FEATURE WITH VCNL3036X01
VCNL3036X01 allows to connect up to 3 external IREDs. Each may be selected separate to allow for normal proximity.
If one select e.g. IRED2 then also PS2 delivers the corresponding proximity data. To allow for a fast quasi-parallel
measurements of all three channels the MPX_MODE may be activated (set to “1”).
Within “PS_FORCE_MODE” all three IREDs will be sequentially switched and available proximity result of this directly shown
within the three PS_DATA register.
Beside MPX_MODE enabled and PS_FORCE_MODE set this sequence starts direct after setting the PS_TRIG bit. Availability
of the data will be indicated with setting the MPX_DATA_READY flag or also the Interrupt if this is set-up also. Please see below
diagram.
PS_MS
INT_MPX_EN
PS_FORCE_MODE
PS_TRIG
PS_OPERATION_SEQUENCE
IRED1
IRED2
IRED3
MPX_DATA_READY FLAG
INTERRUPT
MPX DATA
Fig. 8 - VCNL3036X01 MPX Mode Sequence
Rev. 1.0, 12-Aug-2020
Document Number: 84937
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APPLICATION CIRCUIT BLOCK REFERENCE
1.8 V to 5.5 V
R2
2.5 V to 5.5 V
IRED3 (4)
C1
C2
22 μF
R3
R4
IRED2 (5)
Host
micro controller
100 nF
IRED1 (6)
VCNL3036X01
2.5 V to 3.6 V
C3
VDD (1)
INT (7)
GPIO / INT
100 nF
GND (3)
I2C bus clock SCL
I2C bus data SDA
SCL (2)
SDA (8)
Fig. 9 - Circuitry with Two Separate Power Supply Sources
Three additional capacitors in the circuit are proposed for the following purposes: (1) the 100 nF capacitor near the VDD pin is
used for power supply noise rejection, (2) the 22 μF plus parallel 100 nF capacitors - connected to the common anode of the
external IREDs - are used to prevent the IRED voltage from instantly dropping when an IRED is switched on, and (3) 2.2 kΩ to
4.7 kΩ are recommended values for the pull up resistor of I2C. The value of the pull-up resistor at the INT line could be 10 kΩ
applied on the INT pin.
1.8 V to 5.5 V
R2
2.5 V to 3.6 V
IRED3 (4)
C1
C2
22 μF
R3
R4
IRED2 (5)
100 nF
IRED1 (6)
VCNL3036X01
R1
10R
Host
micro controller
C4
C3
10 μF
VDD (1)
INT (7)
GPIO / INT
100 nF
GND (3)
SCL (2)
SDA (8)
I2C bus clock SCL
I2C bus data SDA
Fig. 10 - Circuitry with just One Common Power Supply Source
For high currents of the IREDs and / or power supply close to the lower limit of 2.5 V this R-C decoupling will prevent that the
VDD voltage drop below specified minimum.
Mechanical placement of the external IRED depends on the application.
Rev. 1.0, 12-Aug-2020
Document Number: 84937
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PACKAGE DIMENSIONS in millimeters
1.95
Pinning bottom view
0.195
0.29
IRED2
5
IRED1
6
INT
7
SDA
8
0.4
0.77
1.4
1.03
0.4
0.7
1.18
IRED3
4
0.415
GND
3
SCL
2
VDD
1
Exposed pad is
internally connected
to GND
0.195
0.65 (8 x)
Pinning top view
GND
3
SCL
2
VDD
1
IRED2
5
IRED1
6
INT
7
SDA
8
0.15
0.75
IRED3
4
1.05 (3 x)
(3.15)
Recommended solder foot print
0.65 (8 x)
(2.36)
1.36
(0.8)
2.66
2.36
(0.83) (0.78)
0.75 (8 x)
4
0.3 (6 x)
(4)
Drawing No.: 6.550-5331.02-4
Issue: 1; 27.07.2020
Not indicated tolerances ± 0.1 mm
Rev. 1.0, 12-Aug-2020
Technical drawings
according to DIN
specification.
Document Number: 84937
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TAPE AND REEL DIMENSIONS in millimeters
Reel-size:
GS 08: Ø 180 mm ± 2 mm = 3300 pcs.
GS 18: Ø 330 mm ± 2 mm = 13 000 pcs.
Non tolerated dimensions ± 0.1 mm
Reel-design is representative for different types.
Unreel direction
Re
el-
Ø
Ø
13
Em
(Em pty
pty lead
tra er 4
iler 00
20 mm
0m
m min.
mi
n.)
A
Label posted here
.4
1.3
A
0.3
18
Sensor orientation
Ø 1.55
4
4
2
12
Drawing No.: 9.800-5143.01-4
Issue: prel., 06.06.2017
Rev. 1.0, 12-Aug-2020
5.5
1.75
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SOLDER PROFILE
DRYPACK
Devices are packed in moisture barrier bags (MBB) to
prevent the products from moisture absorption during
transportation and storage. Each bag contains a desiccant.
Axis Title
10000
300
Max. 260 °C
255 °C
240 °C
217 °C
245 °C
FLOOR LIFE
1000
200
Max. 30 s
1st line
2nd line
2nd line
Temperature (°C)
250
150
Max. 120 s
100
Max. 100 s
Max. ramp down 6 °C/s
100
Floor life (time between soldering and removing from MBB)
must not exceed the time indicated on MBB label:
Floor life: 168 h
Conditions: Tamb < 30 °C, RH < 60 %
Moisture sensitivity level 3, according to J-STD-020.
Max. ramp up 3 °C/s
50
DRYING
10
0
0
50
100
150
200
250
300
Time (s)
19841
Fig. 11 - Lead (Pb)-free Reflow Solder Profile
according to J-STD-020
Rev. 1.0, 12-Aug-2020
In case of moisture absorption devices should be baked
before soldering. Conditions see J-STD-020 or label.
Devices taped on reel dry using recommended conditions
192 h at 40 °C (+ 5 °C), RH < 5 %.
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