VESD05A8B-HNH
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Vishay Semiconductors
8-Line ESD Protection Diode Array in LLP1713-9L
FEATURES
8
• Ultra compact LLP1713-9L package
2
7
• Low package profile < 0.6 mm
3
6
4
5
1
9
• 8-line ESD protection
• Low leakage current IR < 0.5 μA
• Low load capacitance CD = 20 pF
20522
20521
• ESD immunity acc. IEC 61000-4-2
± 17 kV contact discharge
± 17 kV air discharge
MARKING (example only)
• Working voltage range VRWM = 5 V
YXX
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
20719
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Dot = pin 1 marking
Y = type code (see table below)
XX = date code
DESIGN SUPPORT TOOLS
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Models
Available
ORDERING INFORMATION
ORDERING CODE
TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL)
MINIMUM ORDER QUANTITY
VESD05A8B-HNH-GS08
3000
15 000
DEVICE NAME
VESD05A8B-HNH
PACKAGE DATA
DEVICE NAME
PACKAGE
NAME
VESD05A8B-HNH LLP1713-9L
TYPE
CODE
WEIGHT
MOLDING COMPOUND
FLAMMABILITY RATING
E
3.7 mg
UL 94 V-0
MOISTURE
SENSITIVITY LEVEL
SOLDERING CONDITIONS
MSL level 1
Peak temperature max. 260 °C
(according J-STD-020)
ABSOLUTE MAXIMUM RATINGS VESD05A8B-HNH
RATING
Peak pulse current
Peak pulse power
ESD immunity
Operating temperature
Storage temperature
Rev. 1.6, 09-Jan-2019
TEST CONDITIONS
SYMBOL
VALUE
UNIT
BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9);
acc. IEC 61000-4-5; tp = 8/20 μs; single shot
IPPM
4
A
BiSy-mode: each input (pin 1 to pin 8) to any other input pin.
Pin 9 not connected. Acc. IEC 61000-4-5; tp = 8/20 μs; single shot
IPPM
3
A
BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9);
acc. IEC 61000-4-5; tp = 8/20 μs; single shot
PPP
52
W
BiSy-mode: each input (pin 1 to pin 8) to any other input pin.
Pin 9 not connected. Acc. IEC 61000-4-5; tp = 8/20 μs; single shot
PPP
45
W
Contact discharge acc. IEC 61000-4-2; 10 pulses
BiAs-mode: eacht input (pin 1 to pin 8) to ground (pin 9)
VESD
± 17
kV
Air discharge acc. IEC 61000-4-2; 10 pulses
BiSy-mode: each input (pin 1 to pin 8) to any other input pin.
Pin 9 not connected
VESD
± 10
kV
TJ
-40 to +125
°C
TSTG
-55 to +150
°C
Junction temperature
Document Number: 81741
1
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8B-HNH
www.vishay.com
Vishay Semiconductors
BiAs-MODE (8-line bidirectional asymmetrical protection mode)
With the VESD05A8B-HNH up to 8 signal- or data-lines (L1 to L8) can be protected against voltage transients. With pin 9
connected to ground and pin 1 up to pin 8 connected to a signal- or data-line which has to be protected. As long as the voltage
level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the
protection diode between data line and ground offer a high isolation to the ground line. The protection device behaves like an
open switch.
As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode
becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The
clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance
(resistance and inductance) of the protection device.
Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of
the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level.
Due to the different clamping levels in forward and reverse direction the VESD05A8B-HNH clamping behaviour is bidirectional
and asymmetrical (BiAs).
L1
L2
L3
L4
1
8
9
2
7
3
6
4
5
L8
L7
L6
L5
20524
ELECTRICAL CHARACTERISTICS VESD05A8B-HNH (Between pin 1 to 8, and pin 9)
(Tamb = 25 °C, unless otherwise specified)
TEST CONDITIONS/REMARKS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Number of lines which can be protected
Nchannel
-
-
8
lines
Max. reverse working voltage
VRWM
-
-
5
V
Reverse voltage
at IR = 0.5 μA
VR
5
-
Reverse current
at VR = VRWM = 5 V
IR
-
PARAMETER
Protection paths
Reverse stand-off voltage
-
V
0.5
μA
at IR = 1 mA
VBR
6
8
V
Reverse clamping voltage
at IPP = 4 A acc. IEC 61000-4-5
VC
-
13
V
Forward clamping voltage
at IF = 4 A acc. IEC 61000-4-5
VF
-
4.5
V
at VR = 0 V; f = 1 MHz
CD
-
20
23
pF
at VR = 2.5 V; f = 1 MHz
CD
-
12
14
pF
Reverse breakdown voltage
Capacitance
Rev. 1.6, 09-Jan-2019
Document Number: 81741
2
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8B-HNH
www.vishay.com
Vishay Semiconductors
If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the VESD05A8B-HNH can also be used
in parallel in order to "multiply" the performance. If two diodes are switched in parallel you get
• double surge power = double peak pulse current (2 x IPPM)
• half of the line inductance = reduced clamping voltage
• half of the line resistance = reduced clamping voltage
• double line capacitance (2 x CD)
• double reverse leakage current (2 x IR)
L1
1
L4
8
9
L2
2
7
3
6
4
5
L3
20525
BiSy-MODE (7-line bidirectional symmetrical protection mode)
If a bipolar symmetrical protection device is needed the VESD05A8B-HNH can also be used as a seven-line protection device.
Therefore seven pins (example: pin 1, 2, 3, 4, 6, 7 and 8) has to be connected to the signal or data-line (L1 to L7) and pin 5 to
ground. Pin 9 must not be connected!
Positive and negative voltage transients will be clamped in the same way. The clamping current from one data line through the
VESD05A8B-HNH to the ground passes one diode in forward direction and the other one in reverse direction. The clamping
voltage (VC) is defined by the breakthrough voltage (VBR) level of one diode plus the forward voltage of the other diode plus the
voltage drop at the series impedances (resistances and inductances) of the protection device.
Due to the same clamping levels in positive and negative direction the VESD05A8B-HNH voltage clamping behaviour is also
bidirectional and symmetrical (BiSy).
L1
L2
L3
L4
1
8
9
2
7
3
6
4
5
L7
L6
L5
20526_1
ELECTRICAL CHARACTERISTICS (One input pin 1 to 8 to any other input pin. Pin 9 not connected.)
(Tamb = 25 °C, unless otherwise specified)
PARAMETER
TEST CONDITIONS/REMARKS
SYMBOL
MIN.
TYP.
Number of lines which can be protected
Nchannel
-
Max. reverse working voltage
VRWM
-
Reverse voltage
at IR = 0.5 μA
VR
5.5
-
-
V
Reverse current
at VR = VRWM = 5.5 V
IR
-
0.5
μA
Protection paths
Reverse working voltage
Reverse breakdown voltage
Reverse clamping voltage
Capacitance
Rev. 1.6, 09-Jan-2019
MAX.
UNIT
-
7
lines
-
5.5
V
at IR = 1 mA
VBR
6.5
8.7
V
at IPP = 3 A acc. IEC 61000-4-5
VC
-
15
V
at VR = 0 V; f = 1 MHz
CD
-
10
13
pF
at VR = 2.5 V; f = 1 MHz
CD
-
8
10
pF
Document Number: 81741
3
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8B-HNH
www.vishay.com
Vishay Semiconductors
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
100
8 µs to 100 %
100 %
Pin 9 to
Pin 1, 2, 3, 4, 5, 6, 7 or 8
10
80 %
IF (mA)
IPPM
60 %
20 µs to 50 %
40 %
20 %
1
0.1
0.01
0%
0
10
20
30
40
Time (µs)
20548
0.001
0.5
0.8
0.9
1
VF (V)
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
8
120 %
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
Rise time = 0.7 ns to 1 ns
7
100 %
6
80 %
5
VR (V)
Discharge Current IESD
0.7
20780
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
60 %
53 %
4
3
40 %
2
27 %
20 %
1
0
0.01
0%
-10 0 10 20 30 40 50 60 70 80 90 100
Time (ns)
20557
0.1
1
10
20781
Fig. 2 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
100
1000 10000
IR (µA)
Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR
25
14
f = 1 MHz
20
12
positive surge
10
BiAs-mode
8
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
15
VC (V)
CD (pF)
0.6
6
Measured
acc. IEC 61000-4-5
(8/20 µs - wave form)
4
10
VC
2
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
0
BiSy-mode
between two Pins (1 - 8)
Pin 9 not connetced
5
-2
0
0
1
20778
2
3
4
5
6
VR (V)
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Rev. 1.6, 09-Jan-2019
negative surge
-4
0
20779
1
2
3
4
5
IPP (A)
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
Document Number: 81741
4
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8B-HNH
www.vishay.com
Vishay Semiconductors
PACKAGE DIMENSIONS in millimeters (Inches): LLP1713-9L
1.05 (0.041)
0.3 (0.012)
exp. DAP
0.35 (0.014)
0.45 (0.018)
0.2 (0.008) x 45°
0.24 (0.009)
0.23 (0.009)
0.17 (0.007)
0.4 (0.016) bsc
1.2 (0.047) ref.
1.4 (0.055)
0.5 (0.020)
0.6 (0.024)
1.75 (0.069)
1.65 (0.065)
0.152 (0.006) ref.
0 (0.000)
0.05 (0.002)
1.3 (0.051)
Pin 1 marking
Foot print recommendation:
3 x 0.4 = 1.2 (0.047)
20386
Rev. 1.6, 09-Jan-2019
0.4 (0.016)
1 (0.039)
0.2 (0.008)
Solder
resist mask
0.42 (0.017)
Document no.:S8-V-3906.04-001 (4)
Created - Date: 28. August 2006
Rev. 1 - Date: 27. May 2008
0.4 (0.016)
0.15 (0.006)
0.4 (0.016)
Solder pad
Document Number: 81741
5
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VESD05A8B-HNH
www.vishay.com
Vishay Semiconductors
Pin 1 - location
LLP1713
Top view
Rev. 1.6, 09-Jan-2019
Pad layout - view from top
seen at bottom side
Document Number: 81741
6
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 01-Jan-2023
1
Document Number: 91000
