VS-60CTQ150HN3
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Vishay Semiconductors
High Performance Schottky Rectifier, 2 x 30 A
FEATURES
Base
common
cathode
2
• 175 °C TJ operation
• Low forward voltage drop
• High frequency operation
• High purity, high temperature epoxy
encapsulation for enhanced mechanical
strength and moisture resistance
TO-220AB
Anode
Anode
2
1 Common 3
cathode
• Guard-ring for enhanced ruggedness and
long term reliability
Available
• AEC-Q101 qualified, meets JESD 201 class 2 whisker test
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
PRODUCT SUMMARY
Package
TO-220AB
IF(AV)
2 x 30 A
VR
150 V
DESCRIPTION
VF at IF
0.72 V
IRM max.
20 mA at 125 °C
TJ max.
175 °C
Diode variation
Common cathode
EAS
0.4 mJ
The center tap Schottky rectifier series has been optimized
for low reverse leakage at high temperature. The proprietary
barrier technology allows for reliable operation up to 175 °C
junction temperature. Typical applications are in switching
power supplies, converters, freewheeling diodes, and
reverse battery protection.
MAJOR RATINGS AND CHARACTERISTICS
CHARACTERISTICS
SYMBOL
IF(AV)
Rectangular waveform
VRRM
VALUES
UNITS
60
A
150
V
IFSM
tp = 5 μs sine
710
A
VF
30 Apk, TJ = 125 °C (typical, per leg)
0.69
V
TJ
Range
-55 to +175
°C
VOLTAGE RATINGS
PARAMETER
SYMBOL
Maximum DC reverse voltage
VR
Maximum working peak reverse voltage
VRWM
VS-60CTQ150HN3
UNITS
150
V
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Maximum average forward
current, see fig. 5
SYMBOL
TEST CONDITIONS
IF(AV)
50 % duty cycle at TC = 137 °C, rectangular waveform
VALUES
UNITS
30
per leg
60
per device
A
5 µs sine or 3 µs rect. pulse
Following any rated load
condition and with rated
VRRM applied
710
Maximum peak one cycle non-repetitive
surge current per leg, see fig. 7
IFSM
Non-repetitive avalanche energy per leg
EAS
TJ = 25 °C, IAS = 0.9 A, L = 1 mH
0.4
mJ
Repetitive avalanche current per leg
IAR
Current decaying linearly to zero in 1 μs
Frequency limited by TJ maximum VA = 1.5 x VR typical
0.9
A
10 ms sine or 6 ms rect. pulse
270
Revision: 09-Jan-15
Document Number: 95839
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VS-60CTQ150HN3
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Vishay Semiconductors
ELECTRICAL SPECIFICATIONS
SYMBOL
PARAMETER
TEST CONDITIONS
30 A
Maximum forward voltage drop per leg
See fig. 1
VFM (1)
TJ = 25 °C
60 A
30 A
TJ = 125 °C
60 A
Maximum reverse leakage current per leg
See fig. 2
IRM
Typical junction capacitance per leg
CT
Typical series inductance per leg
LS
Maximum voltage rate of change
dV/dt
TJ = 25 °C
VR = Rated VR
TJ = 125 °C
TYP
MAX.
0.83
0.88
UNITS
0.98
1.09
0.67
0.72
0.82
0.87
7
75
μA
V
7.2
20
mA
VR = 5 VDC (test signal range 100 kHz to 1 MHz) 25 °C
-
650
pF
Measured lead to lead 5 mm from package body
-
7.5
nH
Rated VR
-
10 000
V/μs
Note
(1) Pulse width < 300 μs, duty cycle < 2 %
THERMAL - MECHANICAL SPECIFICATIONS
SYMBOL
PARAMETER
Maximum junction and storage
temperature range
TEST CONDITIONS
TJ, TStg
per leg
Maximum thermal resistance,
junction to case
per package
RthJC
Typical thermal resistance,
case to heatsink
RthCS
Marking device
UNITS
-55 to +175
°C
DC operation, see fig. 4
1.2
DC operation
0.6
Mounting surface, smooth and greased
0.25
°C/W
6
Approximate weight
Mounting torque
VALUES
g
0.21
oz.
minimum
6 (5)
kgf · cm
maximum
12 (10)
(lbf · in)
Case style TO-220AB
60CTQ150H
Revision: 09-Jan-15
Document Number: 95839
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VS-60CTQ150HN3
Vishay Semiconductors
100
1000
TJ = 175 °C
IR - Reverse Current (mA)
IF - InstantaneousForward Current (A)
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100
10
TJ = 175 °C
TJ = 125 °C
TJ = 25 °C
1
0.2
TJ = 150 °C
10
TJ = 125 °C
TJ = 100 °C
1
TJ = 75 °C
0.1
TJ = 50 °C
0.01
TJ = 25 °C
0.001
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
2.0
20
40
60
80
100
120
140
160
VFM - Forward Voltage Drop (V)
VR - Reverse Voltage (V)
Fig. 1 - Maximum Forward Voltage Drop Characteristics (Per Leg)
Fig. 2 - Typical Values of Reverse Current vs.
Reverse Voltage (Per Leg)
CT - Junction Capacitance (pF)
1000
TJ = 125 °C
100
0
40
80
160
120
VR - Reverse Voltage (V)
ZthJC - Thermal Impedance (°C/W)
Fig. 3 - Typical Junction Capacitance vs. Reverse Voltage (Per Leg)
10
1
PDM
0.1
0.01
0.001
0.00001
t1
D = 0.75
D = 0.50
D = 0.33
D = 0.25
D = 0.20
Single pulse
(thermal resistance)
0.0001
0.001
0.01
t2
Notes:
1. Duty factor D = t1/t2
2. Peak TJ = PDM x ZthJC + TC
0.1
1
10
t1 - Rectangular Pulse Duration (s)
Fig. 4 - Maximum Thermal Impedance ZthJC Characteristics (Per Leg)
Revision: 09-Jan-15
Document Number: 95839
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VS-60CTQ150HN3
Vishay Semiconductors
35
180
170
160
DC
150
140
130
Square wave (D = 0.50)
80 % rated VR applied
120
110
100
30
Average Power Loss (W)
Allowable Case Temperature (°C)
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RMS limit
25
DC
20
D = 0.75
D = 0.50
D = 0.33
D = 0.25
D = 0.20
15
10
5
See note (1)
0
90
0
5
10
15
20
25
30
35
40
0
45
5
10
15
20
25
30
35
40
45
IF(AV) - Average Forward Current (A)
Fig. 5 - Maximum Allowable Case Temperature vs. Average
Forward Current (Per Leg)
Fig. 6 - Forward Power Loss Characteristics (Per Leg)
IFSM - Non-Repetitive Surge Current (A)
IF(AV) - Average Forward Current (A)
1000
At any rated load condition
and with rated VRRM
applied following surge
100
10
100
1000
10 000
tp - Square Wave Pulse Duration (µs)
Fig. 7 - Maximum Non-Repetitive Surge Current (Per Leg)
L
D.U.T.
IRFP460
Rg = 25 Ω
Current
monitor
High-speed
switch
Freewheel
diode
+ Vd = 25 V
40HFL40S02
Fig. 8 - Unclamped Inductive Test Circuit
Note
Formula used: TC = TJ - (Pd + PdREV) x RthJC;
Pd = Forward power loss = IF(AV) x VFM at (IF(AV)/D) (see fig. 6);
PdREV = Inverse power loss = VR1 x IR (1 - D); IR at VR1 = 80 % rated VR
(1)
Revision: 09-Jan-15
Document Number: 95839
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-60CTQ150HN3
www.vishay.com
Vishay Semiconductors
ORDERING INFORMATION TABLE
Device code
VS-
60
C
T
Q
150
H
N3
1
2
3
4
5
6
7
8
1
-
Vishay Semiconductors product
2
-
Current rating (60 = 60 A)
3
-
Circuit configuration
C = common cathode
-
4
Package
T = TO-220
5
-
Schottky “Q” series
6
-
Voltage rating (150 = 150 V)
7
-
H = AEC-Q101 qualified
8
-
Environmental digit
N3 = halogen-free, RoHS-compliant, and totally lead (Pb)-free
ORDERING INFORMATION (Example)
PREFERRED P/N
QUANTITY PER T/R
MINIMUM ORDER QUANTITY
PACKAGING DESCRIPTION
VS-60CTQ150HN3
50
1000
Antistatic plastic tube
LINKS TO RELATED DOCUMENTS
Dimensions
www.vishay.com/doc?95222
Part marking information
www.vishay.com/doc?95028
Revision: 09-Jan-15
Document Number: 95839
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Outline Dimensions
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Vishay Semiconductors
TO-220AB
DIMENSIONS in millimeters and inches
A
(6)
E
E2
ØP
0.014 M B A M
(7)
A
B
Seating
plane
A
Thermal pad
(E)
A1
1
Q
(6)
D
(H1)
H1
(7)
C
D2 (6)
(6) D
2 3
D
L1 (2)
C
Detail B
D1
3xb
1
2
3
3 x b2
Detail B
C
E1 (6)
L
(b, b2)
Base metal
View A - A
c
Plating
c1 (4)
c
A
2x e
A2
e1
b1, b3
(4)
Section C - C and D - D
0.015 M B A M
Lead tip
Conforms to JEDEC® outline TO-220AB
SYMBOL
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
4.25
4.65
0.167
0.183
A1
1.14
1.40
0.045
0.055
NOTES
SYMBOL
MILLIMETERS
INCHES
NOTES
MIN.
MAX.
MIN.
MAX.
D2
11.68
12.88
0.460
0.507
6
E
10.11
10.51
0.398
0.414
3, 6
A2
2.56
2.92
0.101
0.115
E1
6.86
8.89
0.270
0.350
6
b
0.69
1.01
0.027
0.040
E2
-
0.76
-
0.030
7
b1
0.38
0.97
0.015
0.038
4
e
2.41
2.67
0.095
0.105
b2
1.20
1.73
0.047
0.068
e1
4.88
5.28
0.192
0.208
b3
1.14
1.73
0.045
0.068
4
H1
5.84
6.86
0.230
0.270
c
0.36
0.61
0.014
0.024
L
13.52
14.02
0.532
0.552
c1
0.36
0.56
0.014
0.022
4
L1
3.32
3.82
0.131
0.150
D
14.85
15.25
0.585
0.600
3
ØP
3.54
3.73
0.139
0.147
D1
8.38
9.02
0.330
0.355
Q
2.60
3.00
0.102
0.118
6, 7
2
Notes
(1) Dimensioning and tolerancing as per ASME Y14.5M-1994
(2) Lead dimension and finish uncontrolled in L1
(3) Dimension D, D1 and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured
at the outermost extremes of the plastic body
(4) Dimension b1, b3 and c1 apply to base metal only
(5) Controlling dimensions: inches
(6) Thermal pad contour optional within dimensions E, H1, D2 and E1
(7) Dimensions E2 x H1 define a zone where stamping and singulation irregularities are allowed
(8) Outline conforms to JEDEC® TO-220, except A2 (maximum) and D2 (minimum) where dimensions are derived from the actual package
outline
Revision: 06-Mar-2020
Document Number: 95222
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Disclaimer
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Document Number: 91000