VS-VSKT320PbF Series
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Vishay Semiconductors
Thyristor/Thyristor
(MAGN-A-PAK Power Modules), 320 A
FEATURES
• High voltage
• Electrically isolated base plate
• 3600 VRMS isolating voltage
• Industrial standard package
• Simplified mechanical designs, rapid assembly
• High surge capability
• Large creepage distances
• UL approved file E78996
• Designed and qualified for industrial level
MAGN-A-PAK
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
DESCRIPTION
PRIMARY CHARACTERISTICS
IT(AV)
320 A
Type
Modules - thyristor, standard
Package
MAGN-A-PAK
This VSK series of MAGN-A-PAK modules uses high voltage
power thyristor/thyristor in doubler circuit configuration.
The semiconductors are electrically isolated from the metal
base, allowing common heatsinks and compact assemblies
to be built. They can be interconnected to form single phase
or three phase bridges or as AC-switches when modules are
connected in anti-parallel mode. These modules are
intended for general purpose applications such as battery
chargers, welders, motor drives, UPS, etc.
MAJOR RATINGS AND CHARACTERISTICS
SYMBOL
CHARACTERISTICS
IT(AV)
VALUES
70 °C
320
50 Hz
9000
60 Hz
9420
50 Hz
405
60 Hz
370
710
IT(RMS)
ITSM
I2t
I2t
4050
VDRM/VRRM
TJ
Range
UNITS
A
kA2s
kA2s
1200 to 1600
V
-40 to +130
°C
IRRM/IDRM
AT 130 °C
MAXIMUM
mA
ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
TYPE NUMBER
VS-VSKT320-
VOLTAGE
CODE
VRRM/VDRM, MAXIMUM REPETITIVE
PEAK REVERSE AND OFF-STATE
BLOCKING VOLTAGE
V
VRSM, MAXIMUM
NON-REPETITIVE PEAK
REVERSE VOLTAGE
V
12
1200
1300
16
1600
1700
50
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ON-STATE CONDUCTION
PARAMETER
Maximum average on-state current
at case temperature
Maximum RMS on-state current
SYMBOL
IT(AV)
IT(RMS)
TEST CONDITIONS
180° conduction, half sine wave
As AC switch
ITSM
t = 10 ms
100 % VRRM
reapplied
t = 10 ms
I2t
Maximum I2t for fusing
I2t
A
70
°C
9000
No voltage
reapplied
t = 8.3 ms
t = 8.3 ms
Maximum I2t for fusing
UNITS
320
710
t = 10 ms
Maximum peak, one-cycle on-state
non-repetitive, surge current
VALUES
No voltage
reapplied
t = 8.3 ms
t = 10 ms
9420
7570
Sinusoidal
half wave,
initial TJ =
TJ maximum
100 % VRRM
reapplied
t = 8.3 ms
7920
405
370
287
4050
VT(TO)1
(16.7 % x x IT(AV) < I < x IT(AV)),
TJ = TJ maximum
0.80
High level value of threshold voltage
VT(TO)2
(I > x IT(AV)), TJ = TJ maximum
1.03
Low level value on-state slope resistance
rt1
(16.7 % x x IT(AV) < I < x IT(AV)),
TJ = TJ maximum
0.75
High level value on-state slope
resistance
rt2
(I > x IT(AV)), TJ = TJ maximum
0.53
ITM = 750 A, TJ = 25 °C, 180° conduction,
average power = VT(TO) x IT(AV) + rt x (IT(RMS))2
1.40
ITM = 750 A, TJ = TJ maximum, 180° conduction,
average power = VT(TO) x IT(AV) + rf x (IT(RMS))2
1.37
IH
Anode supply = 12 V, initial IT = 30 A, TJ = 25 °C
500
IL
Anode supply = 12 V, resistive load = 1 ,
gate pulse: 10 V, 100 μs, TJ = 25 °C
1000
Maximum holding current
Maximum latching current
VTM, VFM,
kA2s
262
t = 0.1 ms to 10 ms, no voltage reapplied
Low level value or threshold voltage
Maximum peak on-state or
forward voltage drop
A
kA2s
V
m
V
mA
SWITCHING
PARAMETER
SYMBOL
Typical delay time
td
Typical rise time
tr
Typical turn-off time range
tq
TEST CONDITIONS
TJ = 25 °C, gate current = 1 A dIg/dt = 1 A/μs
Vd = 0.67 % VDRM
ITM = 300 A; dI/dt = 15 A/μs; TJ = TJ maximum;
VR = 50 V; dV/dt = 20 V/μs; gate 0 V, 100
VALUES
UNITS
1.0
2.0
μs
200 to 350
BLOCKING
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
50
mA
50 Hz, circuit to base, all terminals shorted, 25 °C, 1 s
3600
V
TJ = TJ maximum, exponential to 67 % rated VDRM
1000
V/μs
Maximum peak reverse and
off-state leakage current
IRRM,
IDRM
TJ = TJ maximum
RMS insulation voltage
VINS
Critical rate of rise of off-state voltage
dV/dt
Revision: 26-Jul-2018
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TRIGGERING
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
PGM
tp 5 ms, TJ = TJ maximum
10.0
Maximum average gate power
PG(AV)
f = 50 Hz, TJ = TJ maximum
2.0
Maximum peak gate current
+ IGM
tp 5 ms, TJ = TJ maximum
3.0
Maximum peak negative gate voltage
- VGT
tp 5 ms, TJ = TJ maximum
5.0
TJ = - 40 °C
4.0
Maximum peak gate power
Maximum required DC gate voltage to trigger
Anode supply = 12 V,
resistive load; Ra = 1
TJ = 25 °C
VGT
TJ = TJ maximum
A
V
3.0
350
Anode supply = 12 V,
resistive load; Ra = 1
TJ = 25 °C
IGT
W
2.0
TJ = - 40 °C
Maximum required DC gate current to trigger
UNITS
mA
200
TJ = TJ maximum
100
Maximum gate voltage that will not trigger
VGD
TJ = TJ maximum, rated VDRM applied
0.25
V
Maximum gate current that will not trigger
IGD
TJ = TJ maximum, rated VDRM applied
10.0
mA
Maximum rate of rise of turned-on current
dI/dt
TJ = TJ maximum, ITM = 400 A,
rated VDRM applied
500
A/μs
VALUES
UNITS
-40 to +130
°C
THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER
SYMBOL
Junction operating and storage
temperature range
TEST CONDITIONS
TJ, TStg
Maximum thermal resistance,
junction to case per junction
RthJC
DC operation
0.125
Typical thermal resistance,
case to heatsink per module
RthCS
Mounting surface flat, smooth and greased
0.02
A mounting compound is recommended
and the torque should be rechecked after
a period of about 3 hours to allow for the
spread of the compound.
4 to 6
Mounting
torque
± 10 %
K/W
MAGN-A-PAK to heatsink
busbar to MAGN-A-PAK
Approximate weight
Nm
500
g
17.8
oz.
Case style
MAGN-A-PAK
R CONDUCTION PER JUNCTION
DEVICES
VSKT320-
SINUSOIDAL CONDUCTION AT TJ MAXIMUM
RECTANGULAR CONDUCTION AT TJ MAXIMUM
180°
120°
90°
60°
30°
180°
120°
90°
60°
30°
0.009
0.010
0.013
0.020
0.032
0.007
0.011
0.015
0.020
0.033
UNITS
K/W
Note
• Table shows the increment of thermal resistance RthJC when devices operate at different conduction angles than DC
Revision: 26-Jul-2018
Document Number: 94085
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Maximum Allowable Case
Temperature (°C)
RthJC(DC) = 0.125 K/W
120
110
Ø
Conduction angle
100
90
30°
80
60°
90°
120°
70
180°
Maximum Average On-State
Power Loss (W)
130
60
0
50
100
150
200
250
300
350
Average On-State Current (A)
94085_01
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0
200
300
400
500
8000
RthJC(DC) = 0.125 K/W
110
100
Ø
Conduction angle
90
80
30° 60°
70
90°
60
At any rated load condition and with
rated VRRM applied following surge.
Initial TJ = 130 °C
7500
120
Peak Half Sine Wave
On-State Current (A)
Maximum Allowable Case
Temperature (°C)
100
Average On-State Current (A)
Fig. 4 - On-State Power Loss Characteristics
130
DC
120°
7000
60 Hz 0.0083 s
50 Hz 0.0100 s
6500
6000
5500
5000
4500
4000
180°
Per junction
3500
50
0
100
200
300
400
1
500
Average On-State Current (A)
94085_02
10
100
Number of Equal Amplitude Half
Cycle Current Pulses (N)
94085_05
Fig. 5 - Maximum Non-Repetitive Surge Current
Fig. 2 - Current Ratings Characteristics
500
9000
180°
120°
90°
60°
30°
450
400
350
300
RMS limit
250
200
150
Ø
Conduction angle
Per Junction
TJ = 130 °C
100
50
100
200
300
7000
No voltage reapplied
Rated VRRM reapplied
6000
5000
4000
Per junction
0
0
Maximum non-repetitive surge current
versus pulse train duration. Control
of conduction may not be maintained.
Initial TJ = 130 °C
8000
Peak Half Sine Wave
On-State Current (A)
Maximum Average On-State
Power Loss (W)
RMS limit
Ø
Conduction angle
Per Junction
TJ = 130 °C
94085_04
Fig. 1 - Current Ratings Characteristics
94085_03
DC
180°
120°
90°
60°
30°
400
Average On-State Current (A)
Fig. 3 - On-State Power Loss Characteristics
3000
0.01
94085_06
0.1
1
Pulse Train Duration (s)
Fig. 6 - Maximum Non-Repetitive Surge Current
Revision: 26-Jul-2018
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VS-VSKT320PbF Series
Instantaneous On-State Current (A)
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10 000
TJ = 130 °C
1000
TJ = 25 °C
Per junction
100
0.5
1.5
2.5
3.5
4.5
Instantaneous On-State Voltage (V)
94085_07
Fig. 7 - On-State Voltage Drop Characteristics
ZthJC - Transient Thermal
Impedance (°C/W)
1
Steady state value
RthJC = 0.125 K/W
(DC operation)
0.1
0.01
0.001
0.001
0.01
0.1
1
10
100
Square Wave Pulse Duration (s)
94085_08
Fig. 8 - Thermal Impedance ZthJC Characteristics
ORDERING INFORMATION TABLE
Device code
VS-VS
KT
320
1
2
3
-
16
PbF
4
5
1
-
Vishay Semiconductors product
2
-
Circuit configuration (see dimensions - link at the end of datasheet)
3
-
Current rating
4
-
Voltage code x 100 = VRRM (see Voltage Ratings table)
5
-
• None = standard production
• PbF = lead (Pb)-free
Note
• To order the optional hardware go to www.vishay.com/doc?95172
Revision: 26-Jul-2018
Document Number: 94085
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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CIRCUIT CONFIGURATION
CIRCUIT DESCRIPTION
Two SCRs doubler circuit
CIRCUIT
CONFIGURATION CODE
KT
CIRCUIT DRAWING
~
~
+
+
-
K1 G1 G2 K2
LINKS TO RELATED DOCUMENTS
Dimensions
www.vishay.com/doc?95086
Revision: 26-Jul-2018
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