THC63LVD827-2BRA

THC63LVD827_Rev.1.00_E THC63LVD827 LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER General Description Features The THC63LVD827 transmitter is designed to support pixel data transmission between Host and Flat Panel Display and Dual Link transmission between Host and Flat Panel Display up to 1080p/1920x1440 resolutions. The THC63LVD827 converts 27bits (RGB 8 bits + Hsync, Vsync, DE) of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. For dual LVDS out, LVDS clock frequency of 87MHz, 51bits of RGB data are transmitted at an effective rate of 609Mbps per LVDS channel. For single LVDS out, LVDS clock frequency of 174MHz, 27bits of RGB data are transmitted at an effective rate of 1218Mbps per LVDS channel. 21bits (RGB 6 bits + Hsync, Vsync, DE) mode is also selectable for 6bit color transmission with lower power. • Low power 1.8V CMOS design • 7mm x 7mm/72pin/0.65mm pitch/TFBGA package • applicable to non-HDI PCB. Wide dot clock range, 10-174MHz, suited for TV Signal: up to 1080p(74.25MHz dual) PC Signal: up to 1920x1440(86MHz dual) • Supports 1.8V single power supply • 1.8V/2.5V/3.3V TTL/CMOS inputs are supported by setting IOVCC=1.8V/2.5V/3.3V • LVDS swing reducible by RS-pin to reduce both EMI and power consumption • PLL requires No external components • Flexible Input/Output mode 1. Single in / Dual LVDS out 2. Single in / Single LVDS out 3. Double edge Single in / Dual LVDS out • • • • 2 LVDS data mapping to simplify PCB layout Power down mode Input clock triggering edge selectable by R/F pin 6bit / 8bit modes selectable by 6B/8B pin Data Formatter 3 R/F RS 28 MAP PARALLEL TO SERIAL HSYNC VSYNC DE 28 24 1) DEMUX 2) MUX R1[7:0] G1[7:0] B1[7:0] TTL/CMOS Inputs TA1 +/- PARALLEL TO SERIAL Block Diagram TA2 +/- TB1 +/- LVDS Outputs 1st Link TC1 +/TD1 +/- TB2 +/- LVDS Outputs 2nd Link TC2 +/TD2 +/- MODE O/E DDRN /PDWN PRBS 6B/8B TRANSMITTER CLOCK IN TCLK1 +/PLL TCLK2 +/- 10 to 174MHz 10 to 174MHz (Single in /Dual out : 20 to 174MHz) Copyright©2012 THine Electronics, Inc. 1/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Pin Out (top view) Copyright©2012 THine Electronics, Inc. 2/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Pin Description Pin Name Pin # TA1+, TA1- A1,B1 TB1+, TB1- A2,B2 TC1+, TC1- A3,B3 TD1+, TD1- A5,B5 TCLK1+, TCLK1- A4,B4 TA2+, TA2- A6,B6 TB2+, TB2- A7,B7 TC2+, TC2- A8,B8 TD2+, TD2- C9,C8 TCLK2+, TCLK2- A9,B9 R17 ~ R10 G17 ~ G10 B17 ~ B10 Type Description The 1st Link. LVDS OUT The 1st pixel output data when Dual out. Output data when Single out. LVDS OUT LVDS OUT LVDS OUT LVDS Clock Out for 1st Link. The 2nd Link. The 2nd pixel output data when Dual out. LVDS Clock Out for 2nd Link. G1,G2,F1,F2 E1,E2,D1,D2 J4,H4,J3,H3 J2,H2,J1,H1 IN Pixel Data Inputs. J8,H8,J7,H7 J6,H6,J5,H5 DE G9 IN Data Enable Input. VSYNC H9 IN Vsync Input. HSYNC J9 IN Hsync Input. CLKIN F9 IN Clock Input. R/F G8 IN Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge LVDS swing mode select. RS RS F8 IN LVDS Swing (VOD, see Fig4 and Fig5) H 350mV L 200mV LVDS mapping table select. See Fig9 and Fig10. MAP E8 MAP H L IN Mapping Mode Mapping MODE1 Mapping MODE2 Pixel data mode. See Fig7 and Fig8. MODE E7 MODE H L IN Modes Single out (Single-in/Single-out) Dual out (Single-in/Dual-out) Output enable. O/E D9 IN H: Output enable, L: Output disable (all outputs are Hi-Z). H: Normal operation, /PDWN D8 IN L: Power down (all outputs are Hi-Z and all circuits are stand-by mode with minimum current (ITCCS)). PRBS a C1 Copyright©2012 THine Electronics, Inc. IN Must be tied to GND. 3/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Pin Description (Continued) Pin Name Pin # Type Reserved1 C3 IN Description Must be tied to GND. 6bit / 8bit mode select. 6B/8B F7 IN H: 6bit mode (21bit mode), L: 8bit mode (27bit mode). DDR function is active when MODE = L (Dual-out mode). DDRN E9 IN H: DDR (Double Edge input) function disable (Fig4). L: DDR (Double Edge input) function enable (Fig5). N/C C2 Must be Open. VCC G3,G5 Power Power Supply Pins for digital circuitry. IOVCC G7 Power Power Supply Pin for IO inputs circuitry. LVDSVCC C5,D3 Power Power Supply Pins for LVDS Outputs. PLLVCC C7 Power Power Supply Pin for PLL circuitry. GND F3,G4,G6,C4, E3,C6,D7 Ground Ground Pins. a: Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of 223-1. The generated PRBS is fed into input data latches, encoded and serialized into LVDS OUT. This function is normally to be used for analyzing the signal integrity of the transmission channel including PCB traces, connectors, and cables. Copyright©2012 THine Electronics, Inc. 4/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Absolute Maximum Ratings Supply Voltage (IOVCC) -0.3V ~ +4.0V Supply Voltage (VCC, PLLVCC, LVDSVCC) -0.3V ~ +2.1V CMOS/TTL Input Voltage -0.3V ~ (IOVCC+ 0.3V) LVDS Transmitter Output Voltage -0.3V ~ (LVDSVCC + 0.3V) Output Current -50mA ~ 50mA Junction Temperature +125 °C Storage Temperature Range -55 °C ~ +125 °C Reflow Peak Temperature / Time +260 °C / 10sec. Maximum Power Dissipation @+25 °C 1.3W Recommended Operating Conditions Parameter Min Typ Max Units Supply Voltage (IOVCC) 1.62 1.8 / 2.5 / 3.3 3.6 V Supply Voltage (PLLVCC / LVDSVCC / VCC) 1.62 1.8 1.98 V Operating Ambient Temperature (Ta) -40 85 °C Clock Single Edge Input Input 20 174 MHz MODE=L (DDRN=H) LVDS Output 10 87 MHz Dual-out Double Edge Input Input 10 174 MHz (DDRN=L) LVDS Output 10 174 MHz MODE=H Input 10 174 MHz Single-out LVDS Output 10 174 MHz Frequency Copyright©2012 THine Electronics, Inc. 5/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Electrical Characteristics CMOS/TTL (Pin type “IN”) DC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter VIH18 High Level Data Input Voltage VIL18 Low Level Data Input Voltage VIH25 High Level Data Input Voltage VIL25 Low Level Data Input Voltage VIH33 High Level Data Input Voltage VIL33 Low Level Data Input Voltage IINC Conditions Min. Typ. Max. Units 0.65 IOVCC IOVCC+0.3 V -0.3 0.35 IOVCC V 1.7 IOVCC+0.3 V -0.3 0.7 V 2.0 IOVCC+0.3 V -0.3 0.8 V -10 10 μA IOVCC=1.62V~1.98V IOVCC=2.3V~2.7V IOVCC=3.0V~3.6V Input Current VIN=GND~IOVCC LVDS Transmitter (Pin type “LVDS OUT”) DC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Normal swing VOD Differential Output Voltage RL=100Ω RS= H Reduced swing RS= L ΔVOD VOC Min. Typ. Max. 250 350 450 mV 140 200 300 mV 35 mV Change in VOD between complementary output states Common Mode Voltage ΔVOC Change in VOC between complementary output states IOS Output Short Circuit Current IOZ Output TRI-State current Copyright©2012 THine Electronics, Inc. RL=100Ω 1.125 VOUT=GND, RL=100Ω /PDWN=L, VOUT=GND~LVDSVCC 6/18 -20 1.25 1.375 Units V 35 mV 100 mA 20 μA THine Electronics, Inc. THC63LVD827_Rev.1.00_E Electrical Characteristics (Continued) Supply Current Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Typ.(a) Max.(b) Units CLKIN=37MHz 24 (18) 33 (26) mA CLKIN=65MHz 29 (23) 43 (37) mA CLKIN=72MHz 30 (24) 46 (40) mA CLKIN=89MHz 48 (36) 65 (53) mA Dual-out CLKIN=119MHz 53 (41) 75 (63) mA DDRN=H CLKIN=139MHz 56 (44) 82 (70) mA CLKIN=154MHz 58 (46) 88 (76) mA CLKIN=44.5MHz 47 (35) 64 (52) mA Dual-out CLKIN=59.5MHz 51 (39) 74 (62) mA DDRN=L CLKIN=69MHz 54 (42) 80 (68) mA CLKIN=77MHz 56 (44) 85 (73) mA 1 50 uA MODE=H Single-out MODE=L RL=100Ω ITCCW Transmitter Supply CL=5pF Current RS = H (RS = L) DDR Input Off MODE=L DDR Input On ITCCS Transmitter Power Down Supply /PDWN = L, All Inputs = Fixed L or H Current (a) All Typ. values are at Vcc=1.8V, Ta=25 °C . The 256 Grayscale Test Pattern inputs test for a typical display pattern. (b) All Max. values are at Vcc=1.98V, Ta=85 °C . Worst Case Test Pattern produces maximum switching frequency for all the LVDS outputs (Fig.1). TCLK1+ Txy+ x= A, B, C, D y=1,2 Fig1. Test Pattern (LVDS Output Full Toggle Pattern) Copyright©2012 THine Electronics, Inc. 7/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min. Typ. Max. Units tTCIP CLK IN Period(Fig4,5) tTCH CLK IN High Time(Fig4,5) 0.35tTCIP tTCL CLK IN Low Time(Fig4,5) 0.35tTCIP tTS TTL Data Setup to CLK IN(Fig4,5) 0.8 ns tTH TTL Data Hold from CKL IN(Fig4,5) 0.8 ns tTCD CLK IN to TCLK+/Delay (Fig4,5) tTCOP CLK OUT Period(Fig6) tLVT tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 tTPLL tDEINT tDEH tDEL 5.75 100 ns 0.5tTCIP 0.65tTCIP ns 0.5tTCIP 0.65tTCIP ns MODE=L,DDR=H 9tTCIP+3.1 9tTCIP+8.0 ns Others 5tTCIP+3.1 5tTCIP+8.0 ns 5.75 100 ns 0.6 1.5 ns 0.0 +0.15 ns LVDS Transition Time(Fig2) Output Data -0.15 Position0 (Fig6) Output Data Position1 (Fig6) Output Data Position2 (Fig6) tTCOP = Output Data Position3 (Fig6) 5.75ns~15ns Output Data Position4 (Fig6) Output Data Position5 (Fig6) Output Data Position6 (Fig6) t TCOP --------------- – 0.15 7 t TCOP --------------7 t TCOP --------------+ 0.15 7 ns t TCOP – 0.15 2 --------------7 t TCOP 2 --------------7 t TCOP 2 --------------+ 0.15 7 ns t TCOP 3 --------------– 0.15 7 t TCOP 3 --------------7 t TCOP 3 --------------+ 0.15 7 ns t TCOP 4 --------------– 0.15 7 t TCOP 4 --------------7 t TCOP + 0.15 4 --------------7 ns t TCOP 5 --------------– 0.15 7 t TCOP 5 --------------7 t TCOP 5 --------------+ 0.15 7 ns t TCOP – 0.15 6 --------------7 t TCOP 6 --------------7 t TCOP 6 --------------+ 0.15 7 ns 10.0 ms Phase Lock Time(Fig3) DE input period (Fig3-1) Dual out mode only (MODE=L) DE High time (Fig3-1) Dual-out mode only (MODE=L) DE Low time(Fig3-1) 4tTCIP tTCIP*(2n)(a) ns 2tTCIP tTCIP*(2m)(a) ns 2tTCIP Dual-out mode only (MODE=L) ns (a) Refer to Fig3-1 for details. Copyright©2012 THine Electronics, Inc. 8/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E AC Timing Diagrams Vdiff=(TA+)-(TA-) TA+ Vdiff 5pF 80% 80% 20% 20% 100Ω TAtLVT tLVT LVDS Output Load Fig2. LVDS Output Load and Transition Time CLKIN VIH /PDWN tTPLL Vdiff=0V TCLKx+/x=1,2 Fig3. PLL Lock Time tDEINT tTCIP CLKIN DE tDEH tDEL Note: In dual-out mode (MODE=L), the period between rising edges of DE (tDEINT), high time of DE (tDEH) should always satisfy following equations. tDEH = tTCIP * (2m) tDEINT = tTCIP * (2n) m, n =integer Fig3-1. Dual OUT mode DE input timing Copyright©2012 THine Electronics, Inc. 9/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E AC Timing Diagrams (Continued) tTCIP tTCH tTCL R/F=L IOVCC CLKIN IOVCC/2 IOVCC/2 IOVCC/2 R1n, G1n, B1n HSYNC VSYNC IOVCC/2 DE n=0-7 R/F=H tTS GND tTH IOVCC Current Data IOVCC/2 GND tTCD TCLKx+ x=1,2 VOD VOC TCLKxTxy+/x=1,2 y= A, B, C, D Current Data Fig4. CLKIN Period, High/Low Time, Setup/Hold Timing for Single Edge Input Mode MODE=H or MODE=L,DDR=H RS pin tTCIP tTCH tTCL VOD H 350mV L 200mV R/F=L IOVCC CLKIN IOVCC/2 IOVCC/2 R/F=H tTS R1n, G1n, B1n HSYNC VSYNC DE n=0-7 tTH tTS IOGND I tTH VCC IOVCC/2 1st Pixel Data 2nd Pixel Data IOVCC/2 GND tTCD TCLKx+ x=1,2 VOD VOC TCLKx- Txy+/x=1,2 y= A, B, C, D Current Data Fig5. CLKIN Period, High/Low Time, Setup/Hold Timing for Double Edge Input Mode (DDR) MODE=L,DDRN=L Copyright©2012 THine Electronics, Inc. 10/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E AC Timing Diagrams (Continued) tTOP2 tTOP3 tTOP4 tTOP5 tTOP6 tTOP0 tTOP1 Tyx+/- Tyx6 Tyx5 Tyx4 Tyx3 TCLKx+ Tyx2 Tyx1 Tyx0 Tyx6 Tyx5 Vdiff = 0V x = 1,2 y = A,B,C,D Tyx4 Tyx3 Tyx2 Tyx1 Vdiff = 0V tTCOP Note: Vdiff = (Tyx+) - (Tyx-), (TCLKx+) - (TCLKx-) Fig6. LVDS Output Data Position Copyright©2012 THine Electronics, Inc. 11/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Single-In / Dual-Out Mode (MODE = L) DE Rn,Gn,Bn HSYNC,VSYNC 1st Pixel Data 2nd Pixel Data 1st Pixel Data 2nd Pixel Data n=10-17 TCLK1+/-,TCLK2+/Previous Cycle Current Cycle TA1+/TB1+/- 1st Pixel Data are mapped. TC1+/TD1+/- TA2+/TB2+/- 2nd Pixel Data are mapped. TC2+/TD2+/- Fig7. Single-In / Dual-Out Mode (MODE=L) Copyright©2012 THine Electronics, Inc. 12/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Single-In / Single-Out Mode (MODE=H) Rn,Gn,Bn HSYNC,VSYNC,DE Pixel Data n=10-17 TCLK1+/Previous Cycle Current Cycle TA1+/TB1+/- Pixel Data are m apped. TC1+/TD1+/- TCLK2+/TA2+/- No output (HiZ) TB2+/TC2+/TD2+/- Fig8. Single-In / Single-Out Mode (MODE=H) Copyright©2012 THine Electronics, Inc. 13/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E LVDS Data Mapping for 8 bit mode (6B/8B=L) TCLKn+/Previous Cycle Current Cycle TAn+/- R13 R12 G12 R17 R16 R15 R14 R13 R12 TBn+/- G14 G13 B13 B12 G17 G16 G15 G14 G13 TCn+/- B15 B14 DE B17 B16 B15 B14 TDn+/- R11 R10 N/A G11 G10 R11 R10 VSYNC HSYNC B11 B10 n=1,2 (a) LVDS Data Mapping when MAP = H (Mapping Mode 1) TCLKn+/Previous Cycle Current Cycle TAn+/- R11 R10 G10 R15 R14 R13 R12 R11 R10 TBn+/- G12 G11 B11 B10 G15 G14 G13 G12 G11 TCn+/- B13 B12 DE B15 B14 B13 B12 TDn+/- R17 R16 N/A G17 G16 R17 R16 VSYNC HSYNC B17 B16 n=1,2 (b) LVDS Data Mapping when MAP = L (Mapping Mode 2) Fig9. LVDS Data Mapping for 8 bit mode (6B/8B=L) Copyright©2012 THine Electronics, Inc. 14/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E LVDS Data Mapping for 6 bit mode (6B/8B=H) TCLKn+/Previous Cycle Current Cycle TAn+/- R13 R12 G12 R17 R16 R15 R14 R13 R12 TBn+/- G14 G13 B13 B12 G17 G16 G15 G14 G13 TCn+/- B15 B14 DE B17 B16 B15 B14 VSYNC HSYNC HiZ TDn+/n=1,2 (a) LVDS Data Mapping when MAP = H (Mapping Mode 1) TCLKn+/Previous Cycle Current Cycle TAn+/- R11 R10 G10 R15 R14 R13 R12 R11 R10 TBn+/- G12 G11 B11 B10 G15 G14 G13 G12 G11 TCn+/- B13 B12 DE B15 B14 B13 B12 VSYNC HSYNC HiZ TDn+/n=1,2 (b) LVDS Data Mapping when MAP = L (Mapping Mode 2) Fig10. LVDS Data Mapping for 6 bit mode (6B/8B=H) Note: Input pins which are not used in 6 bit mode (R10-11,G10-11,B10-11 on Mapping Mode 1, R16-17,G16-17,G16-17 on Mapping Mode 2) can be H, L, or Open. Copyright©2012 THine Electronics, Inc. 15/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Note 1)Cable Connection and Disconnection Don't connect and disconnect the LVDS cable, when the power is supplied to the system. 2)GND Connection Connect the each GND of the PCB which THC63LVD827 and LVDS-Rx on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 3)Multi Drop Connection Multi drop connection is not recommended. 4)Asynchronous use Asynchronous use such as following systems are not recommended. Copyright©2012 THine Electronics, Inc. 16/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Package TFBGA Copyright©2012 THine Electronics, Inc. 17/18 THine Electronics, Inc. THC63LVD827_Rev.1.00_E Notices and Requests 1.)The product specifications described in this material are subject to change without prior notice. 2.)The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3.)This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4.)Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5.)This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6.)Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7.)Please note that this product is not designed to be radiation-proof. 8.)Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. E-mail: sales@thine.co.jp Copyright©2012 THine Electronics, Inc. 18/18 THine Electronics, Inc.