T14L1024A

tm TE CH Preliminary T14L1024A SRAM FEATURES • Fast Address Access Times : 10/12/15ns • Single 3.3V ±0.3V power supply • Low Power Consumption : 110/105/100mA • TTL I/O compatible • 2.0V data retention mode • Automatic power-down when deselected • Available packages : 32-pin 300 mil DIP/SOJ & 32-pin SOP/TSOP-I • Industry Standard Pin Assignment 128K X 8 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The T14L1024A is a one-megabit density, fast static random access memory organized as 131,072 words by 8 bits. It is designed for use in high performance memory applications such as main memory storage and high speed communication buffers. Fabricated using high performance CMOS technology, access times down to 10ns are achieved. Memory expansion by banking is easily accomplished using the chip enable pins CE1 and CE2. This device is packaged in a standard 32-pin 300 mil DIP/SOJ and 32-pin SOP/TSOP-I. BLOCK DIAGRAM Vcc Vss A0 . . . . A16 CE1 CE2 DATA I/O WE OE CORE ARRAY PIN CONFIGURATION NC A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 Vcc A11 CE2 WE A12 A13 A14 A15 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 DECODER DIP / SOJ / SOP 28 27 26 25 24 23 22 21 20 19 18 17 I/O0 . . . I/O7 PIN DESCRIPTION SYMBOL A0 - A16 I/O0 - I/O7 /CE1,CE2 /WE /OE Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground A15 A14 A13 A12 WE CE2 A11 VCC NC A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP-I 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 PART NUMBER EXAMPLES PACKAGE SPEED T14L1024A-10J SOJ 300mil 10ns T14L1024A-10P TSOP-I 8x13.4mm 10ns T14L1024A-10H TSOP-I 8x20mm 10ns 10ns T14L1024A-10N DIP 300mil T14L1024A-10D SOP 10ns TM Technology, Inc. reserves the right to change products or specifications without notice. P. 1 Publication Date: SEP. 2002 Revision:0.F tm TE CH Preliminary T14L1024A DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER Power Supply Voltage Input Voltage Output Voltage Operating Temperatrue Storage Temperature Power Dissipation Short Circuit Output Current SYM Vcc VIN VOUT TOPR TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 0 to +70 -55 to +150 1.0 50 UNIT V V V °C °C W mA TRUTH TABLE CE1 H CE2 X L H H H OE X WE X MODE Not Selected Not Selected Output Disable Read Write I/O0- I/O7 High-Z High-Z High-Z Data Out Data In Vcc X L L L X H L X X H H L I SB, I SB1 I SB, I SB1 Icc Icc Icc OPERATING CHARACTERISTICS (Vcc = 3.3V ±0.3V, Ta = 0 to 70°C) PARAMETER Power Supply Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current SYM. Vcc VIL VIH ILI ILO TEST CONDITIONS MIN. 3.0 -0.5 2.1 2.4 MAX. 3.6 0.8 Vcc+0.3 5 5 0.4 110 105 100 25 5 UNIT V V V uA uA V V mA mA mA mA mA VIN =Vss to Vcc VIN=Vss to Vcc , CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL I OL = 4.0 mA I OH =-2.0 mA CE1 = VIL VOL VOH Icc 10ns I SB I SB1 12ns IO = 0mA 15ns CE1 = VIH , CE2 = VIL, IO = 0mA Vcc = max; CE1 > Vcc-0.2V or CE2< Vss+0.2V; f=0mhz; IO = 0mA CE2 = VIH ;f=max Note: Typical characteristics are at Vcc = 3.3V, Ta = 25°C TM Technology, Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: SEP. 2002 Revision:0.F tm TE CH Preliminary T14L1024A RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN Typ-0.3 -0.3 2.1 0 TYP 3.3 MAX Typ+0.3 0.8 Vcc+0.3 70 UNIT V V V °C VIL VIH TA CAPACITANCE PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL C IN C I/O CONDITION VIN = 0V VOUT = 0V MAX. 6 8 UNIT pF pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0V to 3V 3.0 ns 1.5V C L =30pF, I OH / I OL = -2mA/4mA AC TEST LOADS AND WAVEFORM 3.3V RL=50 ohm OUTPUT Zo=50 ohm Vt=1.5V 30pF OUTPUT 5pF Including Jig and Scope R2 353 ohm R1 319 ohm (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) TM Technology, Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: SEP. 2002 Revision:0.F tm TE CH Preliminary T14L1024A AC CHARACTERISTICS ( Vcc =3.3V ±0.3V, Vss = 0V, Ta = 0 to 70°C) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYM. T14L1024A-10 T14L1024A-12 MIN. MAX. MIN. MAX. 10 12 3 0 3 10 10 6 5 5 3 0 3 12 12 7 6 6 T14L1024A-15 UNIT MIN. MAX. 15 ns 3 0 3 15 15 7 7 7 ns ns ns ns ns ns ns ns tRC tAA tACS tAOE tCLZ* tOLZ* tCHZ* tOHZ* tOH * These parameters are sampled but not 100% tested. (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write SYM. T14L1024A-10 T14L1024A-12 MIN. MAX. MIN. MAX. 10 12 8 8 0 8 0 6 0 0 5 5 10 10 0 10 0 8 0 0 6 6 T14L1024A-15 UNIT MIN. MAX. 15 ns 11 11 0 11 0 8 0 0 6 7 ns ns ns ns ns ns ns ns ns ns tWC tCW tAW tAS tWP tWR tDW tDH tWHZ* tOHZ* tOW * These parameters are sampled but not 100% tested. TM Technology, Inc. reserves the right to change products or specifications without notice. P. 4 Publication Date: SEP. 2002 Revision:0.F tm (Address A ddress TE CH Preliminary T14L1024A TIMING WAVEFORMS READ CYCLE 1 Controlled) tR C tA A tO H D out tO H READ CYCLE 2 (Chip Enable Controlled) tR C Address tA A OE t OE A t LZ O C E1 tO H CE2 t CS A t CLZ D out DON'T CARE UNDEFINED t HZ O tZ CH TM Technology, Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: SEP. 2002 Revision:0.F tm A d d re ss OE TE CH ( OE CLOCK) tW C Preliminary T14L1024A WRITE CYCLE 1 tC W tA W CE1 tW R CE2 tA S WE tO H Z tW P D out tD W tD H D IN WRITE CYCLE 2 ( OE = V IL Fixed) tW C A d d ress tC W tA W CE1 tW R CE2 tA S WE tW HZ tW P tO H (1 ,4 ) tO W (2 ) (3 ) D out tD W tD H D IN D O N 'T C A R E U N D E F IN E D TM Technology, Inc. reserves the right to change products or specifications without notice. P. 6 Publication Date: SEP. 2002 Revision:0.F tm TE CH Preliminary T14L1024A Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with C L = 5pF. guaranteed but not 100% tested. This parameter is 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TM Technology, Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: SEP. 2002 Revision:0.F tm TE CH Preliminary T14L1024A PACKAGE DIMENSIONS 32-LEAD SOJ (300 mil) SYMBOL A A1 A2 B B1 C D E E1 e L y DIMENSIONS IN INCHES 0.140(MAX) 0.026(MIN) 0.100±0.005 0.018(TYP) 0.028(TYP) 0.008(TYP) 0.823±0.005 0.335±0.010 0.300±0.005 0.050(TYP) 0.086±0.010 0.003(MAX) DIMENSIONS IN MM 3.556(MAX) 0.660(MIN) 2.540±0.127 0.457(TYP) 0.711(TYP) 0.203(TYP) 20.904±0.127 8.509±0.254 7.620±0.127 1.270(TYP) 2.184±0.254 0.076(MAX) TM Technology, Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: SEP. 2002 Revision:0.F tm 1 TE CH Preliminary T14L1024A PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x20mm) HD C 32 b E e 16 17 A2 "A " A A1 S e a t in g p la n e y D S e a t in g p la n e L D e t a il " A " L1 SYMBOL A A1 A2 b C HD D E e L L1 θ DIMENSIONS IN INCHES MIN NOM MAX 0.047 0.002 0.006 0.035 0.040 0.041 0.007 0.008 0.011 0.004 0.006 0.008 0.787 TYP 0.724 TYP 0.315 TYP 0.020 TYP 0.020 0.024 0.028 0.032 TYP 0° 3° 5° DIMENSIONS IN MM MIN NOM MAX 1.20 0.05 0.15 0.90 1.00 1.05 0.17 0.20 0.27 0.10 0.15 0.21 20.00 TYP 18.40 TYP 8.00 TYP 0.50 TYP 0.50 0.60 0.70 0.813 TYP 0° 3° 5° TM Technology, Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: SEP. 2002 Revision:0.F tm TE CH Preliminary T14L1024A PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm) HD C 1 32 b E e 16 17 A2 "A " A A1 S e a t in g p la n e y D S e a t in g p la n e L D e t a il " A " L1 SYMBOL A A1 A2 b C HD D E e L L1 θ DIMENSIONS IN INCHES MIN NOM MAX 0.047 0.002 0.006 0.035 0.040 0.041 0.007 0.008 0.011 0.004 0.006 0.008 0.528 TYP 0.465 TYP 0.315 TYP 0.020 TYP 0.020 0.024 0.028 0.032TYP 0° 3° 5° DIMENSIONS IN MM MIN NOM MAX 1.20 0.05 0.15 0.90 1.00 1.05 0.17 0.20 0.27 0.10 0.15 0.21 13.40 TYP 11.80 TYP 8.00 TYP 0.50 TYP 0.50 0.60 0.7 0.813 TYP 0° 3° 5° TM Technology, Inc. reserves the right to change products or specifications without notice. P. 10 Publication Date: SEP. 2002 Revision:0.F tm 32 TE CH Preliminary T14L1024A PACKAGE DIMENSIONS 32-LEAD DIP (300 mil) A 17 A1 1 16 B4 D B2 B B3 B1 C2 C1 C D1 0 Symbol A A1 B B1 B2 B3 B4 C C1 C2 D D1 θ Dimension in mm Min Nom Max 40.64 41.15 7.26 7.36 7.46 5.08 3.05 3.30 3.56 3.68 3.81 3.94 0.38 1.65 2.29 2.54 2.79 0.41 0.46 0.56 1.47 1.52 1.63 7.49 8.00 8.50 10.92 11.43 11.94 0° 15° Dimension in inch Min Nom Max 1.60 1.62 0.286 0.290 0.294 0.200 0.120 0.130 0.140 0.145 0.150 0.155 0.015 0.065 0.090 0.100 0.110 0.016 0.018 0.022 0.58 0.60 0.64 0.295 0.315 0.335 0.430 0.450 0.470 0° 15° TM Technology, Inc. reserves the right to change products or specifications without notice. P. 11 Publication Date: SEP. 2002 Revision:0.F tm 32 TE CH Preliminary T14L1024A PACKAGE DIMENSIONS 32-LEAD SOP e1 17 E HE Detail F 1 D A2 S y Seating Plane Dimension in inches min. typ. max 0.118 0.004 0.101 0.106 0.111 0.014 0.016 0.020 0.006 0.008 0.012 0.805 0.817 0.440 0.445 0.450 0.044 0.050 0.056 0.546 0.556 0.556 0.023 0.031 0.039 0.047 0.055 0.063 0.036 0.004 0° 10° Dimension in mm min. typ. max. 3.00 0.10 2.57 2.69 2.82 0.36 0.41 0.51 0.15 0.20 0.31 20.45 20.75 11.18 11.30 11.43 1.12 1.27 1.42 13.87 14.12 14.38 0.58 0.79 0.99 1.19 1.40 1.60 0.91 0.10 0° 10° e A1 See Detail F A LE b 16 L e1 C Symbol A A1 A2 b C D E e HE L LE S y • Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec. TM Technology, Inc. reserves the right to change products or specifications without notice. P. 12 Publication Date: SEP. 2002 Revision:0.F