T14L1024N-10P

tm TE CH T14L1024N SRAM FEATURES • Fast Address Access Times : 10/12/15ns • Single 3.3V ±0.3V power supply • Center power/ground pin configuration • Low Power Consumption : 110/105/100mA • TTL I/O compatible • 2.0V data retention mode • Automatic power-down when deselected • Available packages : - 32-pin 300 mil and 400 mil SOJ - 32-pin TSOP 8x13.4mm and 8x20mm - 36-Ball CSP (8x10mm) 128K X 8 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The T14L1024N is a one-megabit density, fast static random access memory organized as 131,072 words by 8 bits. It is designed for use in high performance memory applications such as main memory storage and high speed communication buffers. Fabricated using high performance CMOS technology, access times down to 10ns are achieved. BLOCK DIAGRAM Vcc Vss A0 . .. . A16 CE DATA I/O WE OE DECODER PART NUMBER EXAMPLES T14L1024N-10J T14L1024N-10W T14L1024N-10P T14L1024N-10H T14L1024N-10C PACKAGE SPEED SOJ 300mil 10ns SOJ 400 mil 10ns 10ns TSOP 8x13.4mm TSOP 8x20mm 10ns 36-Ball CSP 10ns CORE ARRAY I/O0 . . . I/O7 PIN DESCRIPTION SYMBOL A0 - A16 I/O0 - I/O7 CE WE OE Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground TM Technology Inc. reserves the right P. 1 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm A0 A1 A2 A3 CE I/O0 I/O1 Vcc Vss I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TE CH T14L1024N PIN CONFIGURATION 32 31 30 29 28 27 A16 A15 A14 A13 OE I/O7 I/O6 Vss Vcc I/O5 I/O4 A12 A11 A10 A9 A8 SOJ 26 25 24 23 22 21 20 19 18 17 A0 A1 A2 A3 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 1 2 3 4 5 6 A B C D E F G H A0 A1 NC A3 A6 A8 I /O 4 A2 WE A4 A7 I /O 0 I /O 5 NC A5 I /O 1 V ss V cc V cc V ss I /O 6 NC NC I /O 2 I /O 7 OE CE A 16 A 15 I /O 3 A9 A 10 A 11 A 12 A 13 A 14 36-Ball CSP TOP VIEW (Ball Down) TM Technology Inc. reserves the right P. 2 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER Power Supply Voltage Input Voltage Output Voltage Operating Temperatrue Storage Temperature Power Dissipation Short Circuit Output Current SYM Vcc VIN VOUT TOPR TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 0 to +70 -55 to +150 1.0 50 UNIT V V V °C °C W mA TRUTH TABLE CE H OE X WE X MODE Not Selected Not Selected Output Disable Read Write I/O0- I/O7 High-Z High-Z High-Z Data Out Data In Vcc X L L L X H L X X H H L I SB, I SB1 I SB, I SB1 Icc Icc Icc OPERATING CHARACTERISTICS (Vcc = 3.3V ±0.3V, Ta = 0 to 70°C) PARAMETER Power Supply Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current SYM. Vcc VIL VIH ILI ILO TEST CONDITIONS MIN. 3.0 -0.5 2.1 2.4 MAX. 3.6 0.8 Vcc+0.3 5 5 0.4 110 105 100 25 5 UNIT V V V uA uA V V mA mA mA mA mA VIN =Vss to Vcc VIN=Vss to Vcc , CE = VIH OE = VIH or WE = VIL I OL = 4.0 mA I OH =-2.0 mA CE = VIL VOL VOH Icc 10ns 12ns 15ns I SB I SB1 f=max IO = 0mA CE = VIH , IO = 0mA Vcc = max; CE ≥ Vcc-0.2V; f=0mhz; IO = 0mA Note: Typical characteristics are at Vcc = 3.3V, Ta = 25°C TM Technology Inc. reserves the right P. 3 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN Typ-0.3 -0.3 2.1 0 TYP 3.3 MAX Typ+0.3 0.8 Vcc+0.3 70 UNIT V V V °C VIL VIH TA CAPACITANCE PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL C IN C I/O CONDITION VIN = 0V VOUT = 0V MAX. 6 8 UNIT pF pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0V to 3V 3.0 ns 1.5V C L =30pF, I OH / I OL = -2mA/4mA AC TEST LOADS AND WAVEFORM 3.3V RL=50 ohm OUTPUT Zo=50 ohm Vt=1.5V 30pF OUTPUT 5pF Including Jig and Scope R2 353 ohm R1 319 ohm (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) TM Technology Inc. reserves the right P. 4 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N AC CHARACTERISTICS ( Vcc =3.3V ±0.3V, Vss = 0V, Ta = 0 to 70°C) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYM. T14L1024N-10 T14L1024N-12 MIN. MAX. MIN. MAX. 10 12 3 0 3 10 10 6 5 5 3 0 3 12 12 7 6 6 T14L1024N-15 UNIT MIN. MAX. 15 ns 3 0 3 15 15 7 7 7 ns ns ns ns ns ns ns ns tRC tAA tACS tAOE tCLZ* tOLZ* tCHZ* tOHZ* tOH * These parameters are sampled but not 100% tested. (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write SYM. T14L1024N-10 T14L1024N-12 MIN. MAX. MIN. MAX. 10 12 8 8 0 8 0 6 0 0 5 5 10 10 0 10 0 8 0 0 6 6 T14L1024N-15 UNIT MIN. MAX. 15 ns 11 11 0 11 0 8 0 0 6 7 ns ns ns ns ns ns ns ns ns ns tWC tCW tAW tAS tWP tWR tDW tDH tWHZ* tOHZ* tOW * These parameters are sampled but not 100% tested. TM Technology Inc. reserves the right P. 5 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm (Address TE CH T14L1024N TIMING WAVEFORMS READ CYCLE 1 Controlled) tR C A d d re s s tA A tO H tO H DOUT READ CYCLE 2 (Chip Enable Controlled) tRC Address tA A OE t AOE tOLZ tOH CE t ACS tCLZ tOHZ tCHZ DOUT D ON' T CARE UNDEFINED TM Technology Inc. reserves the right P. 6 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm Ad d r es s TE CH ( OE CLOCK) tW C T14L1024N WRITE CYCLE 1 t WR OE tC W CE t AW tW P WE t t AS OHZ (1,4) DOUT tD W tD H DIN WRITE CYCLE 2 ( OE = V IL Fixed) t WC Ad d r es s t CW t WR CE t t AW WP WE t AS t W HZ (1,4) t OW t OH (2) ( 3) DOUT t DW t DH DIN DON'T CARE UNDEFINED TM Technology Inc. reserves the right P. 7 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with C L = 5pF. guaranteed but not 100% tested. This parameter is 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TM Technology Inc. reserves the right P. 8 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N PACKAGE DIMENSIONS 32-LEAD SOJ (300 mil) SYMBOL A A1 A2 B B1 C D E E1 e L y DIMENSIONS IN INCHES 0.140(MAX) 0.026(MIN) 0.100±0.005 0.018(TYP) 0.028(TYP) 0.008(TYP) 0.823±0.005 0.335±0.010 0.300±0.005 0.050(TYP) 0.086±0.010 0.003(MAX) DIMENSIONS IN MM 3.556(MAX) 0.660(MIN) 2.540±0.127 0.457(TYP) 0.711(TYP) 0.203(TYP) 20.904±0.127 8.509±0.254 7.620±0.127 1.270(TYP) 2.184±0.254 0.076(MAX) TM Technology Inc. reserves the right P. 9 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N PACKAGE DIMENSIONS 32-LEAD SOJ (400 mil) SYMBOL A A1 A2 B B1 C D E E1 e L y DIMENSIONS IN INCHES 0.140(MAX) 0.026(MIN) 0.100±0.005 0.018(TYP) 0.028(TYP) 0.008(TYP) 0.823±0.005 0.440±0.010 0.400±0.005 0.050(TYP) 0.086±0.010 0.003(MAX) DIMENSIONS IN MM 3.556(MAX) 0.660(MIN) 2.540±0.127 0.457(TYP) 0.711(TYP) 0.203(TYP) 20.904±0.127 11.17±0.254 10.16±0.127 1.270(TYP) 2.184±0.254 0.076(MAX) TM Technology Inc. reserves the right P. 10 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm) SYMBOL A A1 A2 b C D E HD e L L1 y θ Dimension in inches 0.044(MAX) 0.004±0.002 0.041(MAX) 0.008±0.004 0.006±0.001 0.465±0.008 0.315±0.004 0.528±0.008 0.020(TYP.) 0.020±0.004 0.031±0.008 0.002(MAX) 0° ~ 5° Dimension in mm 1.10(MAX) 0.05±0.05 1.02(MAX) 0.20±0.10 0.15±0.02 11.8±0.2 8.0±0.1 13.4±0.2 0.5(TYP.) 0.5±0.1 0.8±0.2 0.05(MAX) 0° ~ 5° TM Technology Inc. reserves the right P. 11 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N PACKAGE DIMENSIONS 32-LEAD TSOP (8x20mm) SYMBOL A A1 A2 b C D Db E L L1 θ DIMENSIONS IN INCHES MIN NOM MAX -0.047 0.002 0.006 0.035 0.040 0.041 0.007 0.008 0.011 0.004 0.006 0.008 0.787 TYP 0.724 TYP 0.315 TYP 0.020 0.024 0.028 0.032 TYP 0°~12° DIMENSIONS IN MM MIN NOM MAX 1.20 0.05 0.15 0.90 1.00 1.05 0.17 0.20 0.27 0.10 0.15 0.21 20.00 TYP 18.40 TYP 8.00 TYP 0.598 0.610 0.622 0.813 TYP 0°~12° TM Technology Inc. reserves the right P. 12 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C tm TE CH T14L1024N PACKAGE DIMENSIONS 36-Ball CSP (8x10mm) 6 5 4 3 2 1 A e B C D D D1 E F G H E A2 SEATIN G PLA NE A1 A e E1 Symbol A A1 A2 D D1 E E1 e Dimension in mm Min 1.00 0.24 0.60 9.90 7.90 Nom 5.25 TYP 3.75 TYP 0.75 TYP Max 1.35 0.30 10.10 8.10 - TM Technology Inc. reserves the right P. 13 to change products or specifications without notice. Publication Date: APR. 2002 Revision: C