T14M256A

tm TE CH T 14M256A SRAM FEATURES • High speed access time: 7/8/10/12/15ns(max.) • Low power consumption : Active 300 mW (typ.) • Single + 5 power supply • Fully static operation – No clock or refreshing required • All inputs and outputs directly TTL compatible • Common I/O capability • Available packages : 28-pin 300 mil SOJ and TSOP-I (forward type ). • Output enable (OE ) available for very fast access • Mix-mode Outputs 32K X 8 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The T14M256A is a high speed, low power CMOS static RAM organized as 32,768 x 8 bits that operates on a single 5-volt power supply. This device is packaged in a standard 28-pin 300 mil SOJ or TSOP-I forward. BLOCK DIAGRAM Vcc → VSS → A0 . . . A 14 CS OE WE CONTROL DATA I/O I/O 1 . . . I/O 8 DECODER CORE ARRAY PIN CONFIGURATION A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 Vcc WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 SOJ 23 22 21 20 19 18 17 16 15 PIN DESCRIPTION SYMBOL A0 - A14 I/O1 - I/O8 CS WE OE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V cc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground Operating Temperatur e 0 ~ +70 °C PART NUMBER EXAMPLES PART NO. T 14M256 A-8J T 14M256 A-8 P T 14M256 A-8JE T 14M256 A-8 P E PACKAG E CODE S=SOJ 8ns P =TSOP-I S=SOJ P =TSOP-I 8ns -20 ~ +70 °C SPEED TSOP-I TM Technology Inc. reserves the right P. 1 to change products or specifications without notice. Publication Date: FEB. 2004 Revision:H tm TE CH T 14M256A DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage to Vss Potential Inputs to Vss Potential Power Dissipation Storage Temperature RATING -0.5 to + 6 -0.5 to Vcc +0.5 1.0 -60 to +150 UNIT V V W °C RECOMMENDED OPERATING CONDITIONS PARAMETER SYM MIN TYP MAX Supply Voltage Vcc Typ-5% 5 Typ+5% VIL Input Voltage, low -0.3 0.8 VIH Input Voltage, high 2 .2 Vcc+0.3 TA Ambient Temperature 0 70 N ote: VIL (min.) = -2.0V for pulse width ≤ 20ns, VIH (max.) = +7.0V for pulse width ≤ 20ns. UNIT V V V °C TRUTH TABLE CS H OE X WE X MODE Not Selected Output Disable R ead Write I/O1- I/O8 High-Z High-Z Data Out Data In Vcc ISB, I SB1 Icc Icc Icc L L L H L X H H L OPERATING CHARACTERISTICS (Vcc = 5V± 5%, Vss = 0V, Ta = 0 to 70° C) PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage SYM.  I L I I LO  TEST CONDITIONS Vin=Vss to Vcc VI/O=Vss to Vcc , CS =VIH or OE= VIH or WE = VIL I OL = + 8.0mA I OH = - 4.0mA -7 CS = VIL , I/O=0mA -8 Cycle = MIN. -10 Duty = 100% -12 -15 MIN. TYP. MAX. UNIT -10 +10 uA -10 +10 uA 2.4 0.4 125 120 110 100 90 15 2 V V mA mA mA mA mA mA mA VOL VOH Operating Power Supply Current Icc Standby Power Supply Current ISB I SB1 CS = VIH , Cycle=MIN, Duty=100% CS ≥ Vcc -0.2V N ote: Typical characteristics are at Vcc = 5V, Ta = 25°C TM Technology Inc. reserves the right P. 2 to change products or specifications without notice. Publication Date: FEB. 2004 Revision:H tm TE CH T 14M256A CAPACITANCE (Vcc = 5V, Ta = 25° C, f = 1 MHz) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VOUT= 0V MAX. 6 8 UNIT pF pF CIN CI / O N ote: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0V to 3V 3 ns 1.5V C L =30pF,I O H / I OL = -4mA/8mA AC TEST LOADS AND WAVEFORM DQ Z0 = 50 ohm Fig.1 R1 480 ohm 5V OUTPUT 30pF Including Jig and Scope Fig.2 3.0V 90% 0V 3ns Fig.5 10% 10% 3ns R2 255 ohm 5pF Including Jig and Scope R2 255 ohm 50 ohm Vt =1.73V 30 pF DQ Z0 = 50 ohm Fig.3 R1 480 ohm 50 ohm Vt =1.73V 5 pF 5V OUTPUT Fig.4 (For TCLZ, T OLZ , TCHZ , TOHZ , T WHZ, TOW ) 90% TM Technology Inc. reserves the right P. 3 to change products or specifications without notice. Publication Date: FEB. 2004 Revision:H tm TE CH T 14M256A AC CHARACTERISTICS (Vcc =5V ± 5%, Vss = 0V, Ta = 0 to 70° C) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYM. -7 -8 -10 -12 -15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. t tAA tACS tAOE tCLZ* tOLZ tCHZ* tOHZ tOH RC 7 2 0 2 7 7 3.5 3.5 3.5 - 8 3 0 2.5 8 8 5 4 4 - 10 3 0 3 10 10 6 5 5 - 12 3 0 3 12 12 7 6 6 - 15 3 0 0 0 3 15 15 7 7 7 - ns ns ns ns ns ns ns ns ns * These parameters are sampled but not 100% tested. (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write SYM. -7 -8 -10 -12 -15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. MIN. M AX. MIN. MAX. tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOHZ tOW 7 5 5 0 5 0 3 .5 0 0 3 3.5 - 8 6 6 0 6 0 5 0 0 4 4 - 10 8 8 0 8 0 6 0 0 5 5 - 12 10 10 0 10 0 8 0 0 6 6 - 15 11 11 0 11 0 8 0 0 6 7 - ns ns ns ns ns ns ns ns ns ns ns * These parameters are sampled but not 100% tested. TM Technology Inc. reserves the right P. 4 to change products or specifications without notice. Publication Date: FEB. 2004 Revision:H tm (Address TE CH T 14M256A TIMING WAVEFORMS READ CYCLE 1 Controlled) tRC A d d r e ss t AA tOH tOH DO UT READ CYCLE 2 (Chip Select Controlled) CS t A CS t CL Z t CH Z DO UT READ CYCLE 3 (Output Enable Controlled) t RC A d d r e ss tAA OE t A OE t OL Z t OH CS t A CS t CL Z t OH Z t CH Z D O UT DON 'T CAR E UN DEF IN ED TM Technology Inc. reserves the right P. 5 to change products or specifications without notice. Publication Date: FEB. 2004 Revision:H tm Addres s TE CH T 14M256A WRITE CYCLE 1 ( OE CLOCK) t WC t WR OE t CW CS t AW tW P WE t t AS O HZ (1, 4) D OU T t DW t DH DI N WRITE CYCLE 2 ( OE = VIL Fixed) t WC Ad dr es s t CW t WR CS t AW t WP WE t AS t WH Z ( 1, 4 ) tOW tOH ( 2) (3 ) DO U T tDW t DH DI N D ON 'T C AR E U N DE F INE D TM Technology Inc. reserves the right P. 6 to change products or specifications without notice. Publication Date: FEB. 2004 Revision:H tm TE CH T 14M256A Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to DIN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with CL = 5pF. This parameter is guaranteed but not 100% tested. 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If O E is high during a W E controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TM Technology Inc. reserves the right P. 7 to change products or specifications without notice. Publication Date: FEB. 2004 Revision:H tm TE CH T 14M256A PACKAGE DIMENSIONS 28-LEAD SOJ SRAM (300 mil) SYMBOL A B C D E F G H I J K L M N O P Q y DIMENSIONS IN INCHES 0.710±0.002 0.300±0.005 0.060±0.002 0.050±0.001 0.063±0.001 0.015±0.002 0.030±0.002 0.050±0.002 0.018±0.002 0.028±0.002 0.337±0.002 0.010±0.001 0.026±0.002 0.268±0.003 0.300±0.002 0.053±0. 001 0.140±0.004 0.004(MAX) DIMENSIONS IN MM 18.03±0.05 7.62±0.13 1.52±0.05 1.27±0.03 1.63±0.03 0.38±0.05 0.76±0.05 1.27±0.05 0.46±0.05 0.71±0.05 8.56±0.05 0.25±0.03 0.66±0.05 6.81±0.08 7.62±0.05 1.35±0.03 3.56±0.10 0.10(MAX) TM Technology Inc. reserves the right P. 8 to change products or specifications without notice. Publication Date: FEB. 2004 Revision:H tm 1 TE CH T 14M256A PACKAGE DIMENSIONS 28-LEAD TSOP-I SRAM (8X13.4mm) D C 28 b E e 14 15 A2 "A" A A1 Seating plane y Db Gauge plane Seating plane L 0.010 Detail "A" L1 SYMBOL A A1 A2 b c Db E e D L L1 y θ DIMENSIONS IN INCHES 0.047(max.) 0.004±0.002 0.039±0.002 0.008(typ.) 0.006(typ.) 0.465±0.004 0.315±0.004 0.022(typ.) 0.528±0.008 0.020±0.004 0.0315 ±0.004 0.004(max.) 0° ~5 ° DIMENSIONS IN MM 1.20(max.) 0.10 ±0.05 1.00 ±0.05 0.20(typ.) 0.15(typ.) 11.80± 0.10 8.00 ±0.10 0.55(typ.) 13.40± 0.20 0.50 ±0.10 0.80 ±0.10 0.10(max.) 0 ° ~5° Publication Date: FEB. 2004 Revision:H TM Technology Inc. reserves the right P. 9 to change products or specifications without notice.