T15M256B-70D

tm TE CH T15M256B SRAM FEATURES • High speed access time: 45/50/70/85/100ns • Low power supply current : - Operating :37mA(max) - Standby : 10uA • Power supply : 5V (± 10%) • Fully static operation – No clock or refreshing required • All inputs and outputs directly LVTTL compatible • Common I/O capability • Data retention voltage : 1.5V (min) • Available packages : 28-pin DIP(600mil),SOJ, SOP/lead-free, TSOP-I (8x13.4mm forward type and reverse type). • Operating temperature : 0 ~ +70 °C -40 ~ +85 °C 32K X 8 LOW POWER CMOS STATIC RAM GENERAL DESCRIPTION The T15M256B is a low power CMOS static RAM. organized as 32,768 x 8 bits that operates on a single 5-volt power supply. Low operating and standby current . Data retention is guaranteed at a power supply voltage as low as 1.5V. This device is packaged in a standard 28-pin DIP(600mil), SOJ, SOP, TSOP-I forward and reverse type. BLOCK DIAGRAM Vcc → Vss → A0 → A14 → . . . DECODER CORE ARRAY PART NUMBER EXAMPLES PART NO. T15M256B-70N T15M256B-70J T15M256B-70D T15M256B-85P T15M256B-85R T15M256B-70DG T15M256B-70NI T15M256B-70JI T15M256B-70DI T15M256B-85PI T15M256B-85RI PACKAGE CODE N=DIP J=SOJ D=SOP P= TSOP-I(Forward) R= TSOP-I(Reverse) D=SOP/lead-free N=DIP J=SOJ D=SOP P= TSOP-I(Forward) R= TSOP-I(Reverse) -40 ~ +85 °C 0 ~ +70 °C Operating Temperature CS → OE → CONTROL WE → ← I / O1 DATA I/O ← I / O8 . . TM Technology Inc. reserves the right to change products or specifications without notice. P. 1 Publication Date: OCT. 2003 Revision:C tm A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 1 I/O 2 I/O 3 V ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TE CH T15M256B PIN CONFIGURATION 28 27 26 25 24 V cc WE A 13 A8 A9 A 11 OE A 10 CS I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 Vcc WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 D IP & SO J 23 22 21 20 19 18 17 16 15 SOP 22 21 20 19 18 17 16 15 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP-I Forward 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP-I Reverse 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 PIN DESCRIPTION SYMBOL A0 - A14 I/O1 - I/O8 CS WE OE Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground TM Technology Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage to Vss Potential Inputs to Vss Potential Power Dissipation Storage Temperature RATING -0.5 to + 7V -0.5 to Vcc +0.5 0.7 -60 to +150 UNIT V V W °C RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN 4.5 -0.3 2.2 0/-40 TYP 5 MAX 5.5 0.8 Vcc+0.3 +70/+85 UNIT V V V °C VIL VIH TA TRUTH TABLE CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1- I/O8 High-Z High-Z Data Out Data In Power Standby Active Active Active OPERATING CHARACTERISTICS (Vcc = 5V / ± 10%, Vss = 0V, Ta = 0 ~ +70 °C /-40 to 85°C) PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage SYM. TEST CONDITIONS Vin=Vss to Vcc VI/O=Vss to Vcc , CS = VIH or OE = I LI I LO VOL VOH MIN. TYP. MAX. UNIT 1 uA 2.4 1 0.4 37 35 30 25 20 0.3 10 uA V V mA mA mA mA mA mA uA VIH or WE = VIL I OL = + 2.1mA I OH = - 1.0mA CS = VIL , I/O=0mA Cycle = MIN. Duty = 100% -45 -50 -70 -85 -100 Operating Power Supply Current Icc Standby Power Supply Current I SB I SB1 CS = VIH , Cycle=min, Duty=100% CS ≥ Vcc -0.2V TM Technology Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B CAPACITANCE (Vcc = 5V / ± 10%, Ta = 25°C, f = 1 MHz) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VOUT = 0V MAX. 6 8 UNIT pF pF C IN C I/O Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 3 ns 1.5V See Fig. 1,2 CONDITIONS AC TEST LOADS AND WAVEFORM 5V OUTPUT R 1 - 1928 ohm 5V OUTPUT R1- 1928 ohm 30pF Including Jig and Scope R2 1020 ohm 5pF Including Jig and Scope R2 1020 ohm (For T C L Z , T O LZ , T C H Z , T O H Z , T W H Z , T O W ) Fig 1 Fig 2 TM Technology Inc. reserves the right to change products or specifications without notice. P. 4 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B AC CHARACTERISTICS ( Vcc = 5V / ± 10%, Vss = 0V, Ta =0 ~ +70 °C/ -40 to 85°C) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z SYM. -45ns -50ns -70ns -85ns -100ns UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tRC tAA tACS tAOE tCLZ* tOLZ* 45 7 5 10 45 45 22 15 15 - 50 7 5 10 50 50 25 20 20 - 70 10 5 10 70 70 35 25 25 - 85 10 5 10 85 85 40 30 30 - 100 10 5 10 100 100 50 30 30 - ns ns ns ns ns ns ns ns ns Chip Deselection to Output in High tCHZ* Z Output Disable to Output in High Z tOHZ* Output Hold from Address Change tOH * These parameters is measured with 5pF test load. (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Active from End of Write SYM. -45ns -50ns -70ns -85ns -100ns UNIT ns ns ns ns ns ns ns ns ns ns MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tWC tCW tAW tAS tWP tWR tDW tDH tWHZ* tOW 45 35 35 0 25 0 22 0 5 15 - 50 40 40 0 30 0 25 0 5 20 - 70 60 60 0 50 0 30 0 5 25 - 85 70 70 0 60 0 35 0 5 30 - 100 80 80 0 70 0 40 0 5 30 - * These parameters is measured with 30pF test load. TM Technology Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B Symbol VDR IDR Test Condition CS ≥ Vcc -0.2V Vcc =5.0, CS ≥ Vcc -0.2V DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Recovery time Min 1.5 0 5 Typ max 10 unit V uA ms Data retention set-up time tCDR tR See data retention waveform DATA RETENTION WAVE FORM D ata Retention M ode V CC V cc_typ t V D R > 1 .5V Vcc_TYP t CD R R CS CS >VCC-0.2V V IH V IH TM Technology Inc. reserves the right to change products or specifications without notice. P. 6 Publication Date: OCT. 2003 Revision:C tm (Address TE CH T15M256B TIMING WAVEFORMS READ CYCLE 1 Controlled) tR C A d d re s s tA A tO H tO H DOUT READ CYCLE 2 (Chip Select CS tA C S tC L Z tC H Z Controlled) DOUT READ CYCLE 3 (Output Enable Controlled) tR C A d d re s s tA A OE tA O E tO L Z tO H CS tA C S tC L Z tO H Z tC H Z DOUT D ON' T CARE UNDEF INED TM Technology Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: OCT. 2003 Revision:C tm Ad d r es s TE CH ( OE CLOCK) tW C T15M256B WRITE CYCLE 1 t WR OE tC W CS t t AW WP WE t AS (1,4) tO H Z DOUT t DW t DH DIN WRITE CYCLE 2 ( OE = V IL Fixed) tW C A d d re s s tC W tW R CS tA W tW P WE tA S tW H Z (1 ,4 ) tO W tO H (2 ) (3 ) DOUT tD W tD H D IN D ON'T CARE UNDEF INED TM Technology Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with C L = 5pF. guaranteed but not 100% tested. This parameter is 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TM Technology Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B PACKAGE DIMENSIONS 28-LEAD DIP SRAM (600 mil) A A1 D B2 B B3 B1 C2 C1 C D1 Symbol A A1 B B1 B2 B3 C C1 C2 D D1 Dimension in inches min. typ. max 1.440 0.546 0.100 0.140 0.015 0.016 0.600 0.630 1.450 0.550 0.210 0.150 0.100 0.018 0.060 0.612 0.650 1.460 0.554 0.160 0.020 0.624 0.670 Dimension in mm min. typ. max. 36.58 13.87 2.54 3.56 0.38 0.41 15.24 16.0 36.83 13.97 5.33 3.81 2.54 0.46 1.52 15.54 16.51 P. 10 37.08 14.07 4.06 0.51 15.85 17.0 Publication Date: OCT. 2003 Revision:C TM Technology Inc. reserves the right to change products or specifications without notice. tm TE CH T15M256B PACKAGE DIMENSIONS 28-LEAD SOJ SRAM (300 mil) SYMBOL A B C D E F G H I J K L M N O P Q y DIMENSIONS IN INCHES 0.710±0.002 0.300±0.005 0.060±0.002 0.050±0.001 0.063±0.001 0.015±0.002 0.030±0.002 0.050±0.002 0.018±0.002 0.028±0.002 0.337±0.002 0.010±0.001 0.026±0.002 0.268±0.003 0.300±0.002 0.053±0.001 0.140±0.004 0.004(MAX) DIMENSIONS IN MM 18.03±0.05 7.62±0.13 1.52±0.05 1.27±0.03 1.63±0.03 0.38±0.05 0.76±0.05 1.27±0.05 0.46±0.05 0.71±0.05 8.56±0.05 0.25±0.03 0.66±0.05 6.81±0.08 7.62±0.05 1.35±0.03 3.56±0.10 0.10(MAX) TM Technology Inc. reserves the right to change products or specifications without notice. P. 11 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B PACKAGE DIMENSIONS 28-LEAD SOP e1 28 15 E HE Detail F 1 D A2 S y Seating Plane e A1 See Detail F A LE b 14 L e1 C Symbol A A1 A2 b C D E e HE L LE S y θ Dimension in inches Dimension in mm min. typ. max min. typ. max. 0.112 2.845 0.004 0.102 0.093 0.098 0.103 2.362 2.489 2.616 0.014 0.016 0.020 0.335 0.406 0.508 0.008 0.010 0.014 0.203 0.254 0.356 0.713 0.733 18.110 18.618 0.326 0.331 0.336 8.280 8.407 8.534 0.044 0.050 0.056 1.118 1.270 1.422 0.453 0.465 0.477 11.506 11.811 12.116 0.028 0.036 0.044 0.711 0.914 1.117 0.059 0.067 0.075 1.499 1.702 1.905 39 1.0 0.004 0.102 0° 10° 0° 10° Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec. TM Technology Inc. reserves the right to change products or specifications without notice. P. 12 Publication Date: OCT. 2003 Revision:C tm 1 TE CH T15M256B (8X13.4mm) PACKAGE DIMENSIONS 28-LEAD TSOP-I FORWARD AND REVERSE D C 28 b E e 14 15 A2 "A" A A1 Seating plane y Db Gauge plane Seating plane L 0.010 Detail "A" L1 SYMBOL A A1 A2 b c Db E e D L L1 y θ DIMENSIONS IN INCHES 0.047(max.) 0.004±0.002 0.039±0.002 0.008(typ.) 0.006(typ.) 0.465±0.004 0.315±0.004 0.022(typ.) 0.528±0.008 0.020±0.004 0.0315±0.004 0.004(max.) 0°~5° DIMENSIONS IN MM 1.20(max.) 0.10±0.05 1.00±0.05 0.20(typ.) 0.15(typ.) 11.80±0.10 8.00±0.10 0.55(typ.) 13.40±0.20 0.50±0.10 0.80±0.10 0.10(max.) 0°~5° TM Technology Inc. reserves the right to change products or specifications without notice. P. 13 Publication Date: OCT. 2003 Revision:C