T15N1024A-55DI

tm TE CH T15N1024A SRAM FEATURES • Low-power consumption - Active: 40mA at 55ns (Max.) - CMOS Stand-by: 10uA (Max.) • 55/70/100 ns access time • Equal access and cycle time • Single +2.4V to 3.6V Power Supply • TTL compatible , Tri-state output • Common I/O capability • Automatic power-down when deselected • Available in 32-pin SOP ,TSOP-I(8x20mm), TSOP-I(8x13.4mm) ,48-pin CSP packages • Operating temperature : Commercial : Industrial : 0 ~ +70 °C -40 ~ +85 °C 128K X 8 LOW POWER CMOS STATIC RAM GENERAL DESCRIPTION The T15N1024A is a very Low Power CMOS Static RAM organized as 131,072 words by 8 bits. That operates on a wide voltage range from 2.4V to 3.6V power supply, Fabricated using high performance CMOS technology, Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Data retention is guaranteed at a power supply voltage as low as 1.5V. BLOCK DIAGRAM PART NUMBER EXAMPLES PART NO. T15N1024A-55D T15N1024A-70H T15N1024A-100P T15N1024A-100C T15N1024A-55DI T15N1024A-70HI T15N1024A-100PI T15N1024A-100CI PACKAGE CODE D=SOP H=TSOP-I(8x20) P=TSOP-I(8x13.4) C=CSP D=SOP H=TSOP-I(8x20) P=TSOP-I(8x13.4) C=CSP Operating Temperature 0 ~ +70 °C Vcc Vss A0 . . . A16 WE OE CE1 CE2 DECODER CORE ARRAY -40 ~ +85 °C CONTROL CIRCUIT DATA I/O I/O1 .. I/O8 TM Technology Inc. reserves the right to change products or specifications without notice. P. 1 Publication Date: FEB. 2003 Revision:E tm NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS TE CH T15N1024A PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 SOP A 11 A9 A8 A 13 WE CE2 A 15 VDD NC A 16 A 14 A 12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T S O P -I (8 x13 .4 m m ) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A 10 CE1 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 VSS I/O 3 I/O 2 I/O 1 A0 A1 A2 A3 A 11 A9 A8 A 13 WE CE2 A 15 VDD NC A 16 A 14 A 12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T S O P -I (8 x20 m m ) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A 10 CE1 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 VSS I/O 3 I/O 2 I/O 1 A0 A1 A2 A3 1 A B C D E F G H A0 2 A1 3 CE2 4 A3 5 A6 6 A8 I/O5 A2 WE A4 A7 I/O1 I/O6 NC A5 I/O2 VSS 48-CSP TOP VIEW VDD VDD VSS I/O7 NC NC I/O3 I/O8 OE CE1 A16 A15 I/O4 A9 A10 A11 A12 A13 A14 PIN DESCRIPTIONS SYMBOL DESCRIPTIONS A0 ~ A16 Address inputs I/O0~I/O8 Data inputs/outputs CE1 ,CE2 Chip enable WE SYMBOL DESCRIPTIONS OE Output enable input Power supply Ground No connection VDD VSS NC Write enable input TM Technology Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: FEB. 2003 Revision:E tm TE CH T15N1024A ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on Any Pin Relative to Gnd Power Dissipation Storage Temperature commercial Operating Temperature industrial SYM VR PD TSTG Ta MIN. -0.5 -55 0 -40 MAX. +4.6 V 0.7 +150 +70 +85 UNIT V W °C °C *Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE CE2 WE OE CE 1 H X X X X L X X L H H L L H H H L H L X *Note: X = Don’t Care, L = Low, H = High DATA High-Z High-Z Data Out High-Z Data In MODE Standby Standby Active, Read Active, Output Disable Active, Write TM Technology Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: FEB. 2003 Revision:E tm TE CH T15N1024A OPERATING CHARACTERISTICS (Vcc = 2.4 to 3.6V, Gnd = 0V, Ta = 0 ~ +70 °C /-40°C to 85°C) PARAMETER Input Leakage Current Output Leakage Current SYM. ILI TEST CONDITIONS Vcc = Max, VIN = Gnd to Vcc CE1 = VIH or CE2= VIL -55 Min Max -70 Min Max -100 Min Max UNIT uA - 1 - 1 - 1 ILO or OE = VIH or WE = VIL VOUT= Gnd to Vcc CE1 = VIL,CE2= VIH, - 1 - 1 - 1 uA Operating Power Supply Current ICC WE =VIH, OE = VIH , VIN = VIH or VIL, IOUT=0mA - 2 - 2 - 2 mA ICC1 Average Operating Current ICC2 Cycle time=1us, 100% duty, IOUT=0mA, CE1 ≤ 0.2V, CE2 ≥ VCC-0.2V, VIN ≤ 0.2V Cycle time=min, 100% duty, IOUT=0mA, CE1 = VIL,CE2= VIH , VIN = VIH or VIL CE1 = VIH - 3 - 3 - 3 mA - 40 - 35 - 25 mA Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level) Output Low Voltage I SB CE2= VIL CE1 ≥ Vcc-0.2V, - 0.5 - 0.5 - 0.5 mA I SB1 VOL Output High Voltage VOH CE2 ≥ VCC-0.2V or CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ Vcc-0.2V I OL = 1.0mA I OH = -0.5 mA - 10 - 10 - 10 uA 2.1 0.4 - 2.1 0.4 - 2.1 0.4 - V V TM Technology Inc. reserves the right to change products or specifications without notice. P. 4 Publication Date: FEB. 2003 Revision:E tm TE CH T15N1024A RECOMMENDED OPERATING CONDITIONS (Ta = 0 ~ +70 °C /-40°C to 85°C**) PARAMETER Supply Voltage Input Voltage SYM Vcc Gnd MIN 2.4 0.0 1.6 -0.3 MAX 3.6 0.0 Vcc+0.2 0.4 UNIT V V V V VIH VIL CAPACITANCE (f = 1 MHz, Ta = 25°C,) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VIN = VOUT = 0V MAX. 6 8 UNIT pF pF C IN C I/O Note: This parameter is guaranteed by device characterization and is not production tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0.2V to 2.1V 3.0 ns 1.4V C L =30pF+1TTL Load(55ns/70ns) C L =100pF+1TTL Load(Load for 100ns) AC TEST LOADS AND WAVEFORM TTL DQ RL 50 ohm C L* Z0 = 50 ohm Vt =1.4V CL 30 pF Fig.A * Including Scope and Jig Capacitance Fig.B Output Load Equivalent TM Technology Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: FEB. 2003 Revision:E tm TE CH T15N1024A AC CHARACTERISTICS( Vcc =2.4 to 3.6V, Gnd = 0V, Ta = 0 ~ +70 °C /-40°C to 85°C) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z SYM. Min -55 Max Min -70 Max -100 Min Max UNIT ns ns ns ns ns ns ns ns ns tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ 55 10 10 5 - 55 55 30 20 20 70 10 10 5 - 70 70 35 25 25 100 10 10 5 - 100 100 50 30 30 (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Enable to Write End Address Valid to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End SYM. Min -55 Max Min -70 Max -100 Min Max UNIT 30 ns ns ns ns ns ns ns ns ns ns tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW 55 50 50 0 45 0 25 0 5 25 - 70 60 60 0 50 0 30 0 5 25 - 100 80 80 0 70 0 40 0 5 TM Technology Inc. reserves the right to change products or specifications without notice. P. 6 Publication Date: FEB. 2003 Revision:E tm Address TE CH T15N1024A TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) tRC tAA tOH Dout Previous Data Vaild Data Vaild DON'T CARE UNDEFINED READ CYCLE 2 (Chip Enable Controlled) CE1 CE2 tACE tLZ tHZ Dout DON'T CARE UNDEFINED Notes (READ CYCLE) : 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device and from device to device interconnection. 5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE1 =VIL . TM Technology Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: FEB. 2003 Revision:E tm A d d re s s CE1 TE CH ( WE Controlled) tW C T15N1024A WRITE CYCLE 1 tA tC W W tW R CE2 tA WE tO tW D out HZ W S tW P H ig h - Z tD W tD H D IN H ig h - Z D O N 'T C A R E U N D E F IN E D WRITE CYCLE 2 A d d re s s ( CE Controlled) tW C tA W tC W tW R CE1 tA S CE2 tW WE P D out H ig h - Z tD W tD H D IN H ig h - Z D O N 'T C A R E U N D E F IN E D NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low CE1 , a high CE2 and a low WE . A write begins at the lateat transition among CE1 goes low, CE2 going high and WE going low. A write end at the earliest transition among CE1 going high, CE2 going low and WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE1 going low or CE2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. TM Technology Inc. reserves the right P. 8 to change products or specifications without notice. Publication Date: FEB. 2003 Revision:E tm TE CH T15N1024A DATA RETENTION CHARACTERISTICS (Ta = 0 ~ +70 °C /-40°C to 85°C) PARAMETER VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time SYM. VDR ICCDR tCDR tR TEST CONDITION CE1 ≥ VDD -0.2V CE2 ≤ 0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V MIN. 1.5 0 tRC MAX. 5* UNIT V uA ns ns * VCC=1.8V DATA RETENTION WAVEFORM (Ta = 0 ~ +70 °C /-40°C to 85°C) D ata Retention M ode V CC Vcc_typ t V DR > 1 .5V t V cc_TY P R CDR CE1 V IH CE1>VCC-0.2V V IH CE2 V IH CE2 < 0.2V V IH TM Technology Inc. reserves the right P. 9 to change products or specifications without notice. Publication Date: FEB. 2003 Revision:E tm 32 TE CH T15N1024A PACKAGE DIMENSIONS 32-LEAD SOP e1 17 E HE Detail F 1 D A2 S y Seating Plane Dimension in inches min. typ. max 0.118 0.004 0.101 0.106 0.111 0.014 0.016 0.020 0.006 0.008 0.012 0.805 0.817 0.440 0.445 0.450 0.044 0.050 0.056 0.546 0.556 0.556 0.023 0.031 0.039 0.047 0.055 0.063 0.036 0.004 0° 10° Dimension in mm min. typ. max. 3.00 0.10 2.57 2.69 2.82 0.36 0.41 0.51 0.15 0.20 0.31 20.45 20.75 11.18 11.30 11.43 1.12 1.27 1.42 13.87 14.12 14.38 0.58 0.79 0.99 1.19 1.40 1.60 0.91 0.10 0° 10° e A1 See Detail F A LE b 16 L e1 C Symbol A A1 A2 b C D E e HE L LE S y θ Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec. TM Technology Inc. reserves the right P. 10 to change products or specifications without notice. Publication Date: FEB. 2003 Revision:E tm TE CH T15N1024A PACKAGE DIMENSIONS 32-LEAD TSOP (8x20mm) SYMBOL A A1 A2 b C D Db E L L1 θ DIMENSIONS IN INCHES MIN -0.002 0.035 0.007 0.004 NOM 0.040 0.008 0.006 0.787 TYP 0.724 TYP 0.315 TYP 0.024 0.032 TYP 0°~12° MAX 0.047 0.006 0.041 0.011 0.008 DIMENSIONS IN MM MIN 0.05 0.90 0.17 0.10 NOM 1.00 0.20 0.15 20.00 TYP 18.40 TYP 8.00 TYP 0.610 0.813 TYP 0°~12° MAX 1.20 0.15 1.05 0.27 0.21 0.020 0.028 0.598 0.622 TM Technology Inc. reserves the right P. 11 to change products or specifications without notice. Publication Date: FEB. 2003 Revision:E tm 1 TE CH T15N1024A PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm) HD C 32 b E e 16 17 A2 "A " A A1 S e a t in g p la n e y D S e a t in g p la n e L D e t a il " A " L1 SYMBOL A A1 A2 b C D E HD e L L1 y θ Dimension in inches 0.044(MAX) 0.004±0.002 0.041(MAX) 0.008±0.004 0.006±0.001 0.465±0.008 0.315±0.004 0.528±0.008 0.020(TYP.) 0.020±0.004 0.031±0.008 0.002(MAX) 0° ~ 5° Dimension in mm 1.10(MAX) 0.05±0.05 1.02(MAX) 0.20±0.10 0.15±0.02 11.8±0.2 8.0±0.1 13.4±0.2 0.5(TYP.) 0.5±0.1 0.8±0.2 0.05(MAX) 0° ~ 5° Publication Date: FEB. 2003 Revision:E TM Technology Inc. reserves the right P. 12 to change products or specifications without notice. tm TE CH T15N1024A Units : millimeters PACKAGE DIMENSIONS 48-pin CSP (8 row x 6 column) 48 BALL FINE PITCH BGA (0.75mm ball pitch) To p V ie w B ottom V ie w B B1 A 1 IN DE X MA RK 0 .5 0 0.50 # A1 C C1 C1/2 B /2 A E2 D E Y 0.3 0 E1 Symbol A B B1 C C1 D E E1 E2 Y min 5.95 7.95 0.25 0.20 - typ 0.75 6.00 3.75 8.00 5.25 0.30 1.10 0.95 0.25 - max 6.05 8.05 0.35 1.20 0.30 0.08 Notes : 1. Bump counts : 48 (8 row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75) typ. 3. All tolerance are ±0.050 unless otherwise specified. 4. ‘Y’ is coplanarity : 0.08(max) 5. Units : mm TM Technology Inc. reserves the right P. 13 to change products or specifications without notice. Publication Date: FEB. 2003 Revision:E