T15V4M08A-70P

tm TE CH Preliminary T15V4M08A SRAM FEATURES • Low-power consumption - Active: 40mA at 55ns - Stand-by: 10uA (CMOS input/output) • 55/70/100 ns access time • Equal access and cycle time • Single +2.7V to 3.6V Power Supply • TTL compatible , Tri-state output • Common I/O capability • Automatic power-down when deselected • Available in 32-pin TSOP-I(8x13.4mm) and 48-pin CSP packages 512K X 8 LOW POWER CMOS STATIC RAM GENERAL DESCRIPTION The T15V4M08A is a very Low Power CMOS Static RAM organized as 524,288 words by 8 bits . This device is fabricated by high performance CMOS technology. It can be operated under wide power supply voltage range from +2.7V to +3.6V. The T15V4M08A inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Data retention is guaranteed at a power supply voltage as low as 1.5V. PART NUMBER EXAMPLES PART NO. T15V4M08A-55C T15V4M08A-70P PACKAGE CODE P= TSOP-I(8x13.4) C = CSP Vcc Vss A0 . . . A18 DECODER CORE ARRAY WE OE CE CONTROL CIRCUIT DATA I/O I/O1 . . . I/O8 BLOCK DIAGRAM Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 1 Publication Date: MAR. 2001 Revision:0.A tm A11 A9 A8 A13 WE A18 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 TE CH Preliminary T15V4M08A PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 TSOP-I (8x13.4mm) 1 A B C D E F G H A0 2 A1 3 NC 4 A3 5 A6 6 A8 I/O5 A2 WE A4 A7 I/O1 I/O6 NC A5 I/O2 VSS 48-CSP TOP VIEW VCC VCC VSS I/O7 A18 A17 I/O3 I/O8 OE CE A16 A15 I/O4 A9 A10 A11 A12 A13 A14 PIN DESCRIPTIONS SYMBOL DESCRIPTIONS A0 ~ A18 Address inputs I/O1~I/O8 Data inputs/outputs CE WE SYMBOL DESCRIPTIONS OE Output enable input Power supply Ground No connection VCC VSS NC Chip enable Write enable input Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: MAR. 2001 Revision:0.A tm TE CH Preliminary T15V4M08A ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on Any Pin Relative to VSS Power Dissipation Storage Temperature Temperature Under Bias SYM VR PD T STG IBIAS MIN. -0.2 -55 -40 MAX. +3.6 V 0.7 +150 +85 UNIT V W °C °C *Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TRUTH TABLE WE OE DATA MODE CE Standby H X X High-Z L H L Data Out Active, Read L H H High-Z Active, Output Disable L L X Data In Acitve, Write *Note: X = Don’t Care (Must be low or high state), L = Low, H = High Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: MAR. 2001 Revision:0.A tm TE CH Preliminary T15V4M08A OPERATING CHARACTERISTICS (Vcc = 2.7 to 3. 6V, Vss = 0V, Ta = -40° C to 85°C) PARAMETER Input Leakage Current Output Leakage Current SYM. TEST CONDITIONS -55 Min Max -70 Min Max -100 Min Max UNIT uA ILI Vcc = Max, VIN = Vss to Vcc CE = VIH or OE = V IH ILO or WE = V IL VOUT = Vss to Vcc CE = VIL, WE =VIH, OE = VIH , - 1 - 1 - 1 - 1 - 1 - 1 uA Operating Power Supply Current ICC ICC1 Average Operating Current ICC2 VIN = VIH or VIL, IOUT =0mA Cycle time=1us, 100% duty, IOUT =0mA, CE ≤0.2V,VIN ≤0.2V or VIN ≥Vcc-0.2V Cycle time=min, 100% duty, IOUT =0mA, CE = VIL, VIN = V IH or VIL CE = VIH VIN = V IH or VIL CE ≥Vcc-0.2V, - 2 - 2 - 2 mA - 3 - 3 - 3 mA - 40 - 35 - 25 mA Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level) Output Low Voltage Output High Voltage IS B - 0.3 - 0.3 - 0.3 mA IS B1 VOL VOH VIN ≤0.2V or VIN ≥Vcc-0.2V 2.2 10 0.4 - 2.2 10 0.4 - 2.2 10 0.4 - uA V V I OL = 2.1mA I OH = -1.0 mA Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 4 Publication Date: MAR. 2001 Revision:0.A tm TE CH Preliminary T15V4M08A RECOMMENDED OPERATING CONDITIONS (Ta = -40° C to 85°C) PARAMETER Supply Voltage Input Voltage SYM V cc Vss MIN 2.7 0.0 0.7Vcc -0.2 TYP 3.0 0.0 MAX 3.6 0.0 Vcc+0.3 0.6 UNIT V V V V VIH VIL CAPACITANCE (f = 1 MHz, Ta = 25°C,) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VIN = VOUT= 0V MAX. 8 10 UNIT pF pF CIN CI / O N ote: This parameter is guaranteed by device characterization and is not production tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0.6V to 0.7Vcc 3.0 ns 1.4V C L =30pF+1TTL Load(55ns/70ns) C L =100pF+1TTL Load(Load for 100ns) AC TEST LOADS AND WAVEFORM TTL DQ RL 50 ohm C L* Z 0 CL 30 pF = 50 ohm Vt =1.4V Fig.A * Including Scope and Jig Capacitance Fig.B Output Load Equivalent Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: MAR. 2001 Revision:0.A tm TE CH Preliminary T15V4M08A AC CHARACTERISTICS( Vcc =2.7 to 3.6V, Vss = 0V, Ta = -40° C to 85° C) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low -Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z SYM. tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ -55 Min Max Min -70 Max -100 Min Max UNIT ns ns ns ns ns ns ns ns ns 55 10 10 5 - 55 55 30 20 20 70 10 10 5 - 70 70 35 25 25 100 10 10 5 - 100 100 50 30 30 (2)WRITE CYCLE PARAMETER Write Cycle Time Chip Enable to Write End Address Valid to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End SYM. tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW -55 Min Max Min -70 Max -100 Min Max UNIT ns ns ns ns ns ns ns ns ns ns 55 50 50 0 45 0 25 0 5 20 - 70 60 60 0 50 0 30 0 5 25 - 100 80 80 0 70 0 40 0 5 30 - Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 6 Publication Date: MAR. 2001 Revision:0.A tm TE CH Preliminary T15V4M08A TIMING WAVEFORMS READ CYCLE 1 (Address Controlled, CE = OE = VIL , WE =VIH ) tRC Ad dres s tAA tOH D O UT P revious Data Valid Data V alid READ CYCLE 2 ( WE = VIH) tRC Address tOH tAA t CE ACE tHZ OE tOE tOLZ t LZ tOHZ D OUT High-Z DON'T CARE UNDEFINED Notes : (READ CYCLE) : 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the fir st transition address. 3. tHZ and t OHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device and from device to device interconnection. 5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE =VIL . Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: MAR. 2001 Revision:0.A tm A ddress CE TE CH tW C Preliminary T15V4M08A WRITE CYCLE 1 ( WE Controlled) tA W tC W t WR t AS t WP WE t WH Z tO W D OUT H igh- Z tD W tD H D IN H i gh -Z WRITE CYCLE 2 ( CE Controlled) tW C A d dr ess tA W tC W CE tA S tW R tW P WE DOUT H i gh -Z tD W tD H D IN H i gh -Z H i gh -Z D O N'T CA RE U ND E FIN E D NOTES ( WRITE CYCLE ) : 1. A write occurs during the overlap of a low CE , a low WE . A write begins at the lateat transition among CE goes low, WE going low. A write end at the earliest transition among CE going high, WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of CE going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: MAR. 2001 Revision:0.A tm TE CH Preliminary T15V4M08A DATA RETENTION CHARACTERISTICS P ARAMETER V C C for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time SYM. V DR ICCDR tCDR tR TEST CONDITION CE ≥ Vcc -0.2V VIN≥ Vcc -0.2V or VIN≤0.2V MIN. 1.5 0 tRC MAX. 10 UNIT V uA ns ns DATA RETENTION WAVEFORM (Ta = -40° C to 85° C) Data Retention Mode VCC Vcc_typ t V DR > 1.5V t Vcc_TYP R CDR CE V IH CE>VCC-0.2V V IH Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: MAR. 2001 Revision:0.A tm TE CH Preliminary T15V4M08A PACKAGE DIMENSIONS 32-LEAD TSOP-I (8x13.4mm) SYMBOL A A1 A2 b C D E HD e L L1 y è Dimension in inches 0.044(MAX) 0.004±0.002 0.041(MAX) 0.008±0.004 0.006±0.001 0.465±0.008 0.315±0.004 0.528±0.008 0.020(TYP.) 0.020±0.004 0.031±0.008 0.002(MAX) 0°~5° Dimension in mm 1.10(MAX) 0.05±0.05 1.02(MAX) 0.20±0.10 0.15±0.02 11.8±0.2 8.0±0.1 13.4±0.2 0.5(TYP.) 0.5±0.1 0.8±0.2 0.05(MAX) 0°~5° Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice. P. 10 Publication Date: MAR. 2001 Revision:0.A tm TE CH Preliminary T15V4M08A Units : millimeters PACKAGE DIMENSIONS 48-pin CSP (8 row x 6 column) 48 BALL FINE PITCH BGA (0.75mm ball pitch) Top V iew B ottom View B B1 A1 INDEX MARK 0. 50 0. 50 #A1 C C1 C1/2 B /2 A E2 Y D 0.30 E E1 Symbol A B B1 C C1 D E E1 E2 Y min 5.95 7.95 0.25 0.20 - typ 0.75 6.00 3.75 8.00 5.25 0.30 1.10 0.95 0.25 - max 6.05 8.05 0.35 1.20 0.30 0.08 P. 11 Publication Date: MAR. 2001 Revision:0.A Notes : 1. Bump counts : 48 (8 row x 6column) 2. Bump pitch : (x,y)=(0.75 x 0.75) typ. 3. All tolerance are ±0.050 unless otherwise specified. 4. ‘Y’ is coplanarity : 0.08(max) 5. Units : mm Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.