T224160B

tm TE CH T224160B DRAM FEATURES • Industry-standard x 16 pinouts and timing functions. • Single 5V (±10%) power supply. • All device pins are TTL- compatible. • 512-cycle refresh in 8ms. • Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. • Conventional FAST PAGE MODE access cycle. • BYTE WRITE and BYTE READ access cycles. 256K x 16 DYNAMIC RAM FAST PAGE MODE will write data into the upper byte (IO9~16). PIN ASSIGNMENT ( Top View ) Vcc I /01 I/02 I/03 I/04 Vcc I/05 I/06 I/07 I/08 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vss I/016 I/015 I/014 I/013 Vss I/012 I/011 I/010 I/09 NC CASL CASH OE A8 A7 A6 A5 A4 VSS SOJ OPTION TIMING 30ns 35ns 45ns 60ns PACKAGE SOJ TSOP(II) MARKING -30 -35 -45 -60 MARKING J S Vcc I/01 I/02 I/03 I/04 Vcc I/05 I/06 I/07 I/08 1 2 3 4 5 6 7 8 9 10 TSOP(II) 40 39 38 37 36 35 34 33 32 31 Vss I/016 I/015 I/014 I/013 Vss I/012 I/011 I/010 I/09 GENERAL DESCRIPTION The T224160B is a randomly accessed solid state memory containing 4,194,304 bits organized in a x16 configuration. The T224160B has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode operation The T224160B CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two C AS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL transiting low in a WRITE cycle will write data into the lower byte (IO1~IO8), and CASH transiting low Taiwan Memory Technology, Inc. reserves the right P. 1 to change products or specifications without notice. NC NC WE RAS NC A0 A1 A2 A3 Vcc 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 NC CASL CASH OE A8 A7 A6 A5 A4 VSS Publication Date: MAR. 2001 Revision:B tm TE CH T224160B FUNCTIONAL BLOCK DIAGRAM WE CASL CASH CAS CONTROL LOGIC DATA-IN BUFFER DQ01 16 . . DQ16 NO.2 CLOCK GENERATOR DATA-OUT BUFFER 9 COLUMN. ADDRESS BUFFER 9 COLUMN DECODER OE 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 9 9 ROW DECODER ROW. ADDRESS BUFFERS(9) REFRESH COUNTER REFRESH CONTROLLER 512 8 SENSE AMPLIFIERS VO GATING 512 x 16 8 9 512 512 x 512 x 16 MEMORY ARRAY RAS NO.1 CLOCK GENERATOR Vcc Vss PIN DESCRIPTIONS PIN NO. 16~19,22~26 14 28 29 13 27 2~5,6~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 SYM. A0-A8 RAS C ASH TYPE Input Input Input Input Input Input Supply Ground Address Input DESCRIPTION Row Address Strobe Column Address Strobe /Upper Byte Control Column Address Strobe /Lower Byte Control Write Enable Output Enable Power, 5V Ground No Connect CASL WE OE I/O1 - I/O16 Vcc Vss NC Input/ Output Data Input/ Output Taiwan Memory Technology, Inc. reserves the right P. 2 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm 1.2W TE CH T224160B *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on Any pin Relative to VSS… … -1V to 7V Operating Temperature, Ta (ambient)..0°C to +70°C Storage Temperature (plastic)….... -55°C to +150°C Power Dissipation ...............................…......... Short Circuit Output Current...................….... 50mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted) DESCRIPTION CONDITIONS Supply Voltage Supply Voltage Input High (Logic) voltage Input Low (Logic) voltage Input Leakage Current 0V ≤ VIN ≤ 7V 0V ≤ VOUT≤ 7V Output Leakage Current Output(s) disabled Output High Voltage IOH = -5 mA Output Low Voltage IOL = 4.2 mA N ote: 1.All Voltages referenced to Vss SYM. V cc Vss V IH V IL ILI ILO VOH VOL MIN 4.5 0 2.4 -1.0 -10 -10 2.4 MAX 5.5 0 Vcc+1 0.8 10 10 0.4 UNITS V V V V uA uA V V NOTES 1 1 1 Taiwan Memory Technology, Inc. reserves the right P. 3 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH T224160B DC CHARACTERISTICS (Ta = 0 to 70 °C, Vcc = 5V ±10%, Vss = 0V) Parameter Operating Current Standby Current Icc2 Standby Current Fast Page Mode Current RAS -only refresh Current CAS Before RAS Refresh Current 4 4 4 4 Symbol -30 -35 -45 -60 Unit Test Condition RAS , CAS cycling tRC =min TTL interface, Min Max Min Max Min Max Min Max Icc1 - 200 - 180 - 160 - 140 mA mA RAS , CAS =VIH, DOUT=High-Z CMOS interface, RAS , CAS > Vcc-0.2V RAS =VIL, CAS cycling, tPC = min CAS =VIH, RAS cycling, tRC = min RAS , CAS cycling, tRC = min Icc3 I cc4 Icc5 Icc6 - 2 200 200 200 - 2 180 180 180 - 2 160 160 160 - 2 mA 140 mA 140 mA 140 mA Note: Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition, Icc is specified as an average current. CAPACITANCE (Ta =25 °C, Vcc =5V, f = 1M HZ) Parameter Input Capacitance (address) Input Capacitance ( RAS , CAS , WE , OE ) Output Capacitance (data-in/out) Symbol C I1 C I2 CI/O Typ Max 5 7 10 Unit pF pF pF Taiwan Memory Technology, Inc. reserves the right P. 4 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH T224160B AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70° C) AC TEST CONDITIONS: Vcc=5V ± 10%, input pulse level = 0 to 3V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (50pF) AC CHARACTERISTICS PARAMETER Read or Write Cycle Time R ead-Modify-Write Cycle Time Fast-Page-Mode Read or Write Cycle Time Fast-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From C AS Precharge RAS Pulse Width RAS Pulse Width RAS Hold Time RAS Precharge Time C AS Pulse Width SYM tRC tRWC tPC tPCM tRAC tCAC tOAC tAA tACP tRAS -30 55 85 19 56 30 8 8 13 15 30 10K 100K -35 65 95 21 58 35 -45 85 115 25 65 45 -60 110 155 40 80 60 15 15 30 35 60 10K 60 15 100K UNIT MIN MAX MIN MAX MIN MAX MIN MAX Note s ns ns ns ns ns ns ns ns ns ns ns ns 4 5 13 8 9 11 9 11 15 19 18 22 35 10K 45 10K 35 9 100K tRASC 30 tRSH 8 tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL tRCS tRCH tRRH tCLZ tOFF1 45 11 100K 25 5 10K 30 3 10 3 0 5 8 0 4 26 13 0 0 0 3 3 15 24 30 35 6 10K 7 10K 35 3 10 3 0 5 8 0 4 30 15 0 0 0 3 3 15 28 45 5 10 5 0 5 8 0 6 40 19 0 0 0 3 3 15 37 CAS Hold Time C AS Precharge Time RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time RAS to Column Address Delay Time Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Read Command Setup Time Read Command Hold Time Reference to C AS Read Command Hold Time Reference to RAS C AS to Output in Low -Z ns 40 15 10K ns ns 60 10 20 5 0 5 15 0 15 50 30 0 0 0 3 3 15 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10,16 14 9,14 9 7 17 20 26 30 8 Output Buffer Turn-off Delay From CAS or R AS Taiwan Memory Technology, Inc. reserves the right P. 5 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH T224160B -30 SYM tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR 10 10 10 4 0 10 10 0 4 26 4 6 6 0 4 26 46 29 24 1.5 50 8 10 10 10 4 0 10 10 8 0 4 30 4 7 7 0 4 30 51 31 25 2.5 50 8 10 10 10 6 0 10 10 -35 8 0 6 46 6 9 9 0 6 40 61 35 27 2.5 50 8 10 10 10 15 0 10 10 -45 8 0 10 50 10 15 15 0 15 50 85 55 40 3 50 8 -60 15 AC CHARACTERISTICS (continued) AC CHARACTERISTICS PARAMETER Output Buffer Turn-off OE to Write Command Setup Time Write Command Hold Time Write Command Hold Time (Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS ) RAS to WE Delay Time Column Address to W E Delay Time CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (512 cycles) RAS to CAS Precharge Time C AS Setup Time (CBR REFRESH) Note s MIN MAX MIN MAX MIN MAX MIN MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns 16 11,14 14 14 14 14 12 12 11 11 11 2,3 6 6 15 CAS Hold Time (CBR REFRESH) tOEH OE Hold Time From WE During ReadModify-Write Cycle tORD OE Setup Prior to RAS During Hidden Refresh Cycle Write Command Hold Time (Test Mode in) tWTH Write Command Setup Time (Test Mode in) tWTS Taiwan Memory Technology, Inc. reserves the right P. 6 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH T224160B N otes: 1. An initial pause of 200us is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake -ups should be repeated any time the tREF refresh requirement is exceeded. 2. V IH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between V IH(2.4V) and VIL(0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and V IL in a monotonic manner. 4. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that t RCD exceeds the value shown. 5. Assume that tRCD ≥ tRCD(max) . 6. Enables on-chip refresh and address counters. 7. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, access time is controlled by tCAC. 8. Operation within the t AD limit ensures that R tRAC(max) can be met. tRAD(max) is specified as a reference point only; if tRAD is greater than the specified t AD(max) limit, R access time is controlled by tAA. 9. Either tRCH or tRRH must be satisfied for a READ cycle. 10. tOFF1 (max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL . 11. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY -WRITE cycles only. If t CS ≥ tWCS(min), the cycle is an W EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD ≥ tRWD(min), tAWD ≥ tAWD (min) and tCWD ≥ tCWD(min), the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE controlled) cycle. 12. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. WRITE command is defined as W E going low. 15. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 16. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. Taiwan Memory Technology, Inc. reserves the right P. 7 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH READ CYCLE tR C tRAS tRP T224160B RA S V IH V IL t C SH t R SH tC R P tR C D tCAS tRRH CA S V IH V IL tR A D tA S R tRAH RO W tA R t R AL tA S C tCAH ROW t RC H A DDR V IH V IL CO LUMN tR C S WE V IH V IL tA A t R AC t C AC tCLZ N OTE 1 tO F F 1 V I/O V OH OL V IH V IL OP EN tO A C V A L ID D A T A tO F F 2 O PE N OE EARLY WRITE CYCLE tR C tR A S RAS V IH V IL tR P tC R P V C AS V IH IL tR A D tR A H ROW t RC D tC S H tR S H tCAS tA R tA S R tA S C tRAL tCAH ROW A DDR V IH V IL CO LUMN tC W L tR W L t WC S tW C R tW P tW C H WE V IH V IL t DS tD H R tD H V A L ID D A T A V I/O V IOH IOL OE V IH V IL DON'T CARE UNDEFINED N ote: tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. Taiwan Memory Technology, Inc. reserves the right P. 8 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) t R WC tR A S tR P T224160B RA S V IH V IL tC R P V CA S IH V IL t RC D tC S H tR S H tC A S tA R tR AD tA S R tR A H RO W tA S C tR AL tC A H RO W t R WD t C WD t A WD t C WL t R WL t WP ADDR V IH V IL COLUMN tR C S WE V IH V IL tA A tR A C tC AC tC L Z tD S V A LID D t DH OPE N I/O V IOH V IOL V IH V IL OP EN tO A C OU T V A L ID D IN tO F F 2 tO E H OE FAST-PAGE-MODE READ CYCLE t RASC RAS V IH V IL tCSH tCRP V CAS V IH IL tRAD tRAH tRCD tCAS tPC tCP tRSH tCAS tCP tCAS tCPN tRP tAR tRAL tASC tCAH COLUM N tRCS tASC tCAH tASC tCAH ROW tRCH tRRH tASR V ADDR V IH IL ROW COLUMN COLUM N WE V IH V IL tAA tRAC tCAC tCLZ I/O VOH VOL OPEN tOAC OE V IH V IL tOFF1 VALID DAT A tOFF2 tCLZ tAA tACP tCAC tOFF1 VALID DATA tOAC tOFF2 tOAC tCLZ VALID DAT A tO FF2 tAA tACP tCAC tOFF1 OPEN DON'T CARE UNDEF INED N ote: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the t PC specification. Taiwan Memory Technology, Inc. reserves the right P. 9 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH FAST-PAGE-MODE EARLY-WRITE CYCLE t R AS C T224160B V RAS V IH IL tC R P tC S H tR C D t CA S tP C tC P tC A S tC P tR S H tC A S tC P N VIH CA S V IL tA R tR A D tA S R tR A H tA S C t CA H tA S C tC A H tA S C tR A L tC A H ADDR V IH V IL RO W C O LU M N tW C S t CWL t WCH tWP C O L U MN t WCS t CWL t WCH tWP C O L U MN tW C S tC W L tW C H tW P RO W V WE V IH IL tW C R tD H R t DS tD H tD S tD H tD S t RW L tD H I/O VIOH V IOL VIH V IL V A L ID D A T A V A L ID D A T A VA LID DA TA OE FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) t R A SC tR P RAS V IH V IL t CR P t RC D tC S H tC A S tC P tPC M t CA S tC P tR S H tC A S tC P N CAS V IH V IL tA R tR A D t AS R tR A H tA S C tC A H tA S C t CA H tA S C t R AL tC A H V ADDR V IH IL RO W C OLUMN tRW D tRC S tC W L tW P tA W D tC W D C OLUMN C OLUMN RO W tR W L tC WL tWP t AWD t CW D tC W L tA W D tC W D tW P WE V IH V IL t R AC t AA tD H tC A C tC L Z tD S tA A tA C P tC A C tC L Z VALI D DO UT VAL ID DI N V ALI D D OUT VALI D DI N tA A t DH t DS tA C P tC A C tC L Z VALI D D OUT V ALI D DI N tD S tD H I/O V IOH V IOL OP EN OP EN tO F F 2 tO A C tO A C tO F F 2 tO A C tO F F 2 tO E H V OE V IH IL D ON 'T CAR E UNDEF INED N ote: tPC can be measured from falling edge to falling edge of C AS , or from rising edge to rising edge of CAS . Both measurements must meet the tP C specification. Taiwan Memory Technology, Inc. reserves the right P. 10 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm V R A S IH V IL TE CH FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) tRASC T224160B tRP tCSH tPC tCRP C A S V IH V IL tAR tRAD tASR V A D D R VIH IL tR AH tASC tCAH tASC tC AH tASC tCAH ROW tRAL tRCD tC AS tCP tCAS tPC tCP tRSH tCAS tCP ROW COLUMN(A) tRCS COLUMN(B) tRCH COLUMN(N) tWCS tWCH WE V IH V IL t AA tRAC tCAC V I / O VIOH IOL tOFF1 VALID DATA (A) tACP t AA tCAC tCLZ VALID DATA (B) NOTE1 VALID DATA IN tO F1 F tDS tDH OPEN tOAC V OE VIH IL RAS ONLY REFRESH CYCLE (ADDR=A0-A8 ; OE , WE =DON‘T CARE) t RC tR A S RAS V IH V IL tR P tCRP tR P C V CA S V IH IL tASR ROW tR A H RO W V ADDR V IH IL V OH V OL I/O OP EN DON'T CARE UNDEFINED Note1:Do not drive data prior to tristate. Taiwan Memory Technology, Inc. reserves the right P. 11 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH CBR REFRESH CYCLE (A0-A8 ; OE =DON‘T CARE) T224160B tR P RA S V IH V IL tR A S tRP tR A S tR P C tC P N tC S R t C HR t RP C tC S R tC H R C A S H, CA S L V IH V IL O P EN I/O WE V IH V IL HIDDEN REFRESH CYCLE ( WE =HIGH ; OE =LOW) (R E A D ) tRA S tR P (R E F R E S H ) tRA S RAS V IH V IL V IH V IL tC RP tR C D t RS H tC H R CAS tA R t RAD tA S R tR A H tA S C tR A L tC A H A D D R V IH V IL ROW C OL U MN tA A tR A C tC A C tC L Z N OTE1 tO FF 1 I /O V OH V OL OPEN t OAC V A L ID D A T A tO F F 2 OPEN OE V IH V IL tO RD N ote: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. Taiwan Memory Technology, Inc. reserves the right P. 12 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH T224160B PACKAGE DIMENSIONS 40-LEAD SOJ DRAM (400 mil) SYMBOL A B C D E F G H I J K L y DIMENSIONS IN INCHES 1.025 ±0.010 0.400 ±0.005 0.045(MAX) 0.050 ±0.006 0.019 ±0.003 0.026 ±0.003 0.440 ±0.010 0.011 ±0.003 0.025(MIN) 0.364 ±0.020 0.047 ±0.006 0.150(MAX) 0.004(MAX) DIMENSIONS IN MM 26.035±0.254 10.160±0.127 1.143(MAX) 1.27± 0.152 0.483 ±0.08 0.661 ± 0.080 11.176±0.254 0.280 ± 0.080 0.635(MIN) 9.246 ± 0.508 1.194 ± 0.152 3.810(MAX) 0.102(MAX) Taiwan Memory Technology, Inc. reserves the right P. 13 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B tm TE CH T224160B PACKAGE DIMENSIONS 40-LEAD TSOP II DRAM (400 mil) " A" SYMBOL A A1 A2 b c D E E1 L1' L' y θ DIMENSIONS IN INCHES 0.047(max) 0.004±0.002 0.039±0.002 0.014(typ.) 0.005(typ.) 0.725±0.004 0.463±0.008 0.400±0.004 0.031 0.020±0.004 0.004(max) 0°~5° DIMENSIONS IN MM 1.20(max) 0.10±0.05 1.00±0.05 0.35(typ.) 0.127(typ.) 18.41±0.10 11.76±0.20 10.16±0.10 0.80 0.500±0.10 0.10(max) 0°~5° Taiwan Memory Technology, Inc. reserves the right P. 14 to change products or specifications without notice. Publication Date: MAR. 2001 Revision:B