tm
TE CH
T431616D/E
SDRAM
FEATURES
Fast access time: 5/6/7 ns • Fast clock rate: 200/166/143 MHz • Self refresh mode: standard and low power • Internal pipelined architecture • 512K word x 16-bit x 2-bank • Programmable Mode registers - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function • Individual byte controlled by LDQM and UDQM • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • CKE power down mode • JEDEC standard +3.3V±0.3V power supply • Interface: LVTTL • 50-pin 400 mil plastic TSOP II package • 60-ball, 6.4x10.1mm VFBGA package • Lead Free Package available for both TSOP II and VFBGA •Low Operating Current for T431616E
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T431616D/E SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The T431616D/E provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications
Key Specifications
T431616D/E tCK3 tRAS tAC3 tRC
Clock Cycle time(min.) Row Active time(max.) Access time from CLK(max.) Row Cycle time(min.)
-5/6/7
5/6/7ns 35/42/42 ns 4.5/5/5.5 ns 48/54/63 ns
ORDERING INFORMATION
Part Number T431616D-5S/C T431616D-5SG/CG T431616D-6S/C T431616D-6SG/CG T431616D-7S/C T431616D-7SG/CG T431616E-7S/C T431616E-7SG/CG G : indicates Lead Free Package Frequency 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz 143MHz 143MHz Package TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA
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Publication Date: FEB. 2007 Revision: A
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1
TE CH
T431616D/E
PIN ARRANGEMENT BGA (Top View)
2 3 4 5 6 7
TSOP-II (Top View)
V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5 0 P IN T S O P (II) (4 0 0 m il x 8 2 5 m il) (0 .8 m m P IN P IT C H ) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 V ss D Q 15 D Q 14 V SSQ D Q 13 D Q 12 V DDQ D Q 11 D Q 10 V SSQ DQ9 DQ8 V DDQ N .C UDQM C LK CKE N .C A9 A8 A7 A6 A5 A4 V ss
A
VSS
DQ15
DQ0
VDD
DQ0 DQ1 V SSQ
B
DQ14
VSSQ
VDDQ
DQ1
C
DQ13
VDDQ
VSSQ
DQ2
DQ2 DQ3
D
DQ12
DQ11
DQ4
DQ3
V DDQ DQ4
E
DQ10
VSSQ
VDDQ
DQ5
DQ5 V SSQ DQ6
F
DQ9
VDDQ
VSSQ
DQ6
G
DQ8
NC
NC
DQ7
DQ7 V DDQ
H
NC
NC
NC
NC
LD Q M WE
J
NC
UDQM
LDQM
W E#
CAS
K NC CLK RAS# CAS#
RAS CS
L
CKE
NC
NC
CS#
A 11 A 10
M
A11
A9
NC
NC
A0 A1 A2
N
A8
A7
A0
A10
P
A6
A5
A2
A1
A3 V DD
R
VSS
A4
A3
VDD
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tm
TE CH
T431616D/E
BLOCK DIAGRAM
I/O Control
LW E
Bank Select
D ata Input Register
LDQ M
Row Decoder
Row Buffeer Refresh Counter
Sense AMP
512K x 16
Output Buffer
D Qi
Address Register
CLK
512K x 16
A DD
LCBR
LRAS
Colum n Decoder
Col. Buffer
Latency & Burst Length
LCKE LRAS LCBR LW E LCAS Tim ing Register Program m ing R egister LW CB R LDQ M
CLK
CK E
CS
RA S
CA S
WE
L(U)DQ M
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Symbol CLK CKE
TE CH
T431616D/E
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When both banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0-A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 256K available in the respective bank. During a Precharge command, A10 is sampled to determine if both banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set command. Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH." Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O buffer controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is sampled HIGH. Input data is masked when LDQM/UDQM is sampled HIGH during a write cycle. Output data is masked (two-clock latency) when LDQM/UDQM is sampled HIGH during a read cycle. UDQM masks DQ15-DQ8, and LDQM masks DQ7-DQ0. The I/Os are byte-maskable during Reads and Writes. No Connect: These pins should be left unconnected. DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V ) DQ Ground: Provide isolated ground to DQs for improved noise immunity. ( 0 V ) Power Supply: +3.3V ± 0.3V Ground
Pin Descriptions (Table 1. Pin Details of T431616D/E)
Type Input Input
A11 A0-A10
Input Input
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
LDQM, UDQM
Input
DQ0-DQ15 NC VDDQ VSSQ VDD VSS
Input/Output Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. Supply Supply Supply Supply
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Publication Date: FEB. 2007 Revision: A
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TE CH
T431616D/E
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command
BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit
State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Any Active(4) Any Idle Idle Idle
(SelfRefresh)
CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE# H H H H H H H H H H H H H L H H L L H X X X X X X X X X X X H L H L L H H X X X X X X X X X X X X X X X X X X X L V V X V V V V V X X X X X X X X X X X V L H L H L H V X X X X X X X X X X X V X X V V V V V X X X X X X X X X X X L L L L L L L L L L H L L H L X H L X H L X L L L H H H H L H H X L L X H X X H X X H X X H H H L L L L L H H X L L X H X X H X X H X X H L L L L H H L H L X H H X H X X H X X H X X
Clock Suspend Mode Entry Power Down Mode Entry
Active Any(5) Active Any
(PowerDown)
Clock Suspend Mode Exit Power Down Mode Exit
Data Write/Output Enable Data Mask/Output Disable
Active
Note:
Active H X H X X X X 1. V=Valid X=Don't Care L=Low level H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 6. LDQM and UDQM
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1
TE CH
T431616D/E
Commands
BankPrecharge command (RAS# = "L", CAS# = "H", WE# = "L", A11 = “V”, A10 = "L", A0-A9 = Don't care) The BankPrecharge command precharges the bank disignated by A11 signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. PrechargeAll command (RAS# = "L", CAS# = "H", WE# = "L", A11 = Don't care, A10 = "H", A0-A9 = Don't care) The PrechargeAll command precharges both banks simultaneously and can be issued even if both banks are not in the active state. Both banks are then switched to the idle state. Read command (RAS# = "H", CAS# = "L", WE# = "H", A11= “V”, A9 = "L", A0-A7 = Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS# latency after the issue of the Read command. Each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
T0 T1 T2 T3 T4 T5 T6 T7 T8
2
3
CLK COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Burst Read Operation(Burst Length = 4, CAS# Latency = 1, 2, 3)
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TE CH
T431616D/E
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure).
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with highimpedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus contention.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK DQM
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DQ's
DOUT A0 Must be Hi-Z before the Write Command
DINB 0
DINB1
DI NB 2
: "H" or "L"
Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 3)
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CLK DQM COM MAND
TE CH
T0 T1 T2 T3 T4 T5 T6
T431616D/E
T7 T8
1 Clk Interval
NOP
NOP
BANKA ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
NOP
CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's
DIN A0 Must be Hi-Z before the Write Command DIN A0
DIN A1
DIN A2
DIN A3
DIN A1
DIN A2
DIN A3
: "H" or "L"
Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 1, 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK DQM
COMM AND
NOP
NOP
READ A
NOP
NOP
WRITE B
NOP
NOP
NOP
CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's
DOUT A0
DIN B0 Must be Hi-Z before the Write Command DIN B0
DIN B 1
DIN B2
DIN B3
DIN B 1
DIN B2
DIN B3
: "H" or "L"
Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 1, 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0 CLK Bank, Col A Bank, Row T1 T2 T3 T4 T5 T6 T7 T8
ADDR ESS
Bank (s)
tRP
COM M AND READ A NOP NOP NOP Precharge NOP NOP Ac tivate NOP
CAS# latency=1 tCK1 , DQ's CAS# la tency=2 t CK2 , DQ's CAS# la tency=3 t CK3 , DQ's
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
DOUT A 0
DOUT A 1
DOUT A 2
DOUT A 3
Read to Precharge (CAS# Latency = 1, 2, 3)
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4 5
TE CH
T431616D/E
Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. Write command (RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COM MAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ0 - DQ3
DIN A0
DIN A1
DIN A2
DIN A3
don't care
The first data element and the write are registered on the same clock edge.
Extra data is masked.
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the auto precharge function may be interrupted by a subsequent Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure).
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COM MAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
1 Clk Interval DQ's DIN A0 DIN B0 DIN B 1 DIN B2 DIN B3
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
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TE CH
T431616D/E
The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed.
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
don't care
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data for the write is masked.
Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention.
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the LDQM/UDQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure).
T0 CLK T1 T2 T3 T4 T5 T6
DQM tRP COM M AND WRITE NOP Precharge NOP NOP Activate NOP
ADDRESS
BA NK COL n DI N n DI N n+1
BANK (S) tWR
ROW
DQ
: don't care Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
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6
CLK COMMAND
TE CH
T431616D/E
Write and AutoPrecharge command (refer to the following figure) (RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored.
T0 T1 T2 T3 T4 T5 T6 T7 T8
Bank A Activate
NOP
NOP
AutoPrecharge
Write A
NOP
NOP
NOP
NOP
NOP
tDAL
CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DIN A0 DIN A1
DIN A0
DIN A1
* * * *
tDAL
tDAL
DIN A0 DIN A1
tDAL= tWR + tRP
Begin AutoPrecharge Bank can be reactivated at completion of tDAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 1, 2, 3)
7 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data) The mode register stores the data for controlling the various operating modes of SDRAM. The Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as both banks are in the idle state.
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CLK CKE
TE CH
T431616D/E
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCK2 Clock min. CS#
RAS#
CAS#
WE#
A11
A10 Address Key A0-A9
DQM
tRP
DQ Hi-Z
PrechargeAll
Mode Register Set Command
Any Command
Mode Register Set Cycle (CAS# Latency = 1, 2, 3)
The mode register is divided into various fields depending on functionality. Burst Length Field (A2~A0) • This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 1, 2, 4, 8, or full page. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length 1 2 4 8 Reserved Reserved Reserved Full Page
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TE CH
•
T431616D/E
Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length of 4 and 8. A3 0 1 Addressing Mode Sequential Interleave
--- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. When the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are effective. Data n Column Address 0
n
1
n+1
2
n+2
3
n+3
4
n+4
5
n+5
6
n+6
7
n+7
-
255
n+255
256
n
257
n+1
-
2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated. --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 • A7 A7 A7 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A5 A5 A5 Column Address A4 A4 A4 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A1 A1 A0 A0# 4 words 8 words Burst Length
A1# A0 A1# A0# A0 A0#
A2# A1 A2# A1
A2# A1# A0 A2# A1# A0#
CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) ≤ CAS# Latency X tCK A6 0 0 0 0 1 A5 0 0 1 1 X A4 0 1 0 1 X CAS# Latency Reserved 1 clock 2 clocks 3 clocks Reserved
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•
T431616D/E
Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. A8 0 0 1 A7 0 1 X Test Mode normal mode Vendor Use Only Vendor Use Only
•
Single Write Mode (A9) This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-Burst-Write mode is selected. When the BS bit is "1", the Burst-Read-Single-Write mode is selected. A9 0 1 Single Write Mode Burst-Read-Burst-Write Burst-Read-Single-Write
Note: A10 and A11 should stay “L” during mode set cycle.
8
No-Operation command (RAS# = "H", CAS# = "H", WE# = "H") The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low). This prevents unwanted commands from being registered during idle or wait states.
9
Burst Stop command (RAS# = "H", CAS# = "H", WE# = "L") The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure.
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK
COMM AND
READ A
NOP
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
The burst ends after a delay equal to the CAS# latency.
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Termination of a Burst Read Operation (Burst Length • 4, CAS# Latency = 1, 2, 3)
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CLK COM M AND
TE CH
T0 T1 T2 T3 T4 T5 T6
T431616D/E
T7 T8
NOP
WRITE A
NOP
NOP
Burst Stop
NOP
NOP
NOP
NOP
CAS# latency=1, 2, 3 DQ's
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked.
Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)
10
Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command. AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms) (RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = “Don‘t care, A0-A9 = Don't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 2048 times within 32ms. The time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed. SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms) (RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care) The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command). SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms) (CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H") This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode.
11
12
13
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T431616D/E
Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing Waveforms) (CKE = "L") When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when both banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations.
15 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing Waveforms, CKE= "H") When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command. 16 Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H") During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output buffers. LDQM/UDQM is also used for device selection, byte selection and bus control in a memory system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
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Symbol
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T431616D/E
Absolute Maximum Rating
Item Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Rating -5/6/7 VIN, VOUT VDD, VDDQ TOPR TSTG PD IOUT - 1.0 ~ 4.6 -1.0 ~ 4.6 0 ~ 70 - 55 ~ 125 1 50 V V °C °C W mA 1 1 1 1 1 1 Unit Note
Recommended D.C. Operating Conditions (Ta = -0~70°C)
Symbol VDD VDDQ VIH VIL Parameter Power Supply Voltage Power Supply Voltage(for I/O Buffer) LVTTL Input High Voltage LVTTL Input Low Voltage Min. 3.0 3.0 2.0 - 0.3 Typ. 3.3 3.3 Max. 3.6 3.6 VDDQ+0.3 0.8 Unit V V V V Note 2 2 2 2
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)
Symbol CI CI/O Parameter Input Capacitance Input/Output Capacitance Min. 2 4 Max. 5 7 Unit pF pF
Note: These parameters are periodically sampled and are not 100% tested.
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T431616D/E
Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0~70°C)
Description/Test condition Operating Current 1 bank tRC ≥ tRC(min), Outputs Open, Input operation signal one transition per one cycle Precharge Standby Current in non-power down mode tCK = tCK(min), CS# ≥ VIH, CKE = VIH Input signals are changed once during 30ns. Precharge Standby Current in power down mode tCK = tCK(min), CKE ≤ VIL(max) Precharge Standby Current in power down mode tCK = ∞,CKE ≤ VIL(max) Active Standby Current in power down mode CKE ≤ VIL(max), tCK = tCK(min) Active Standby Current in non-power down mode CKE ≥ VIL(max), tCK = tCK(min) Operating Current (Burst mode) tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data Refresh Current tRC ≥ tRC(min) Self Refresh Current VIH ≥ VDD - 0.2, 0V ≤ VIL ≤ 0.2V Symbol IDD1
- 5/6/7(T431616D) Max. - 7(T431616E) Max. Unit Note
130/115/100
40
3
IDD2N IDD2P IDD2PS IDD3P IDD3N IDD4 IDD5 IDD6
25 2 2 2 40 165/150/140 115/100/90 2
15 0.8 0.8 1.5 20 40 40 0.6 mA
3
3
3
3, 4 3
Parameter IIL IOL VOH VOL
Description Input Leakage Current ( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V ) Output Leakage Current Output disable, 0V ≤ VOUT ≤ VDDQ) LVTTL Output "H" Level Voltage ( IOUT = -2mA ) LVTTL Output "L" Level Voltage ( IOUT = 2mA )
Min. - 10 - 10 2.4 -
Max. 10 10 0.4
Unit Note uA uA V V
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Symbol
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T431616D/E
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, Ta = -0~70°C) (Note: 5, 6, 7, 8)
A.C. Parameter - 5/6/7/7L Min. Max. Unit Note
tRC tRCD tRP tRRD tRAS tWR tCK1 tCK2 tCK3 tCH tCL tAC1 tAC2 tAC3 tCCD tOH tLZ tHZ tIS tIH tPDE tREF
Note:
Row cycle time (same bank) RAS# to CAS# delay (same bank) Precharge to refresh/row activate command (same bank) Row activate to row activate delay (different banks) Row activate to precharge time (same bank) Write recovery time CL* = 1 Clock cycle time Clock high time Clock low time Access time from CLK (positive edge) CAS# to CAS# Delay time Data output hold time Data output low impedance Data output high impedance Data/Address/Control Input set-up time Data/Address/Control Input hold time PowerDown Exit set-up time Refresh time CL* = 1 CL* = 2 CL* = 3 CL* = 2 CL* = 3
48/54/63/63 15/16/16/16 15/16/16/16 10/12/14/14 35/42/42/42 2 -/20/20/20 -/7/8/8 5/6/7/7 2/2/2.5/2.5 2/2/2.5/2.5 -/8/13/13 -/6/6.5/6.5 4.5/5/5.5/5.5 1 1.8/2/2/2 1 3/4/5/5 2 1 2 64 ms ns Cycle ns 100,000 Cycle ns
9 9 9 9
10 11 11 11
10 8 11 11
* CL is CAS# Latency.
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. 6. Power-up sequence is described in Note 12. A.C. Test Conditions
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TE CH
T431616D/E
LVTTL Interface
Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals
3 .3V 1.2k Ω
1.4V / 1.4V Reference to the Under Output Load (B) 2.4V / 0.4V 1ns 1.4V
1 .4V 50Ω
Z0= 5 0 Ω
Output 30pF 87 0 Ω
Output 30pF
LVTTL D.C. Test Load (A)
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. These parameters account for the number of clock cycle and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number) 10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter. 11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 12. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time. 2) After power-up, a pause of 200us minimum is required. Then, it is recommended that LDQM/UDQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) Both banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required before or after the Mode Register Set command in step 4 to stabilize the internal circuitry of the device.
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T431616D/E
Timing Waveforms
Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCH
CKE
tCL t IS t IS t IH
tCK2
Begin AutoPrecharge Bank A Begin AutoPrecharge Bank B
t IS
CS#
RAS#
CAS#
WE#
A11
tIH
A10
RAx RBx RAy RAz RBy
t IS
A0-A9
RBx CAx RBx CBx RAy CAy RAz RBy
DQM
tRCD
Hi-Z
tRC
Ax0 Ax1 Ax2 Ax3
tDAL
Bx0 Bx1 Bx2
t IS
Bx3 Ay0
t IH
Ay1 Ay2
t WR
Ay3
tRP
tRRD
DQ
Activate Write with Activate Write with Activate Command AutoPrecharge Command AutoPrecharge Command Bank A Command Bank B Command Bank A Bank A Bank B
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B
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CLK
TE CH
T431616D/E
Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T 11
T12
T13
tCH tCL
CKE
tCK2 t IS
Begin AutoPrecharge Bank B
t IS
CS# RAS#
tIH
t IH
CAS#
WE#
A11
t IH
A10
RAx RBx RAy
t IS
A0-A9
RAx CAx RBx CBx RAy
tRRD tRAS
DQM Hi-Z DQ
tRC tRCD tAC2 t LZ tAC2
Ax0
t HZ
Ax1 Bx0
tRP
Bx1
t OH
Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A
t HZ
Activate Command Bank A
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CLK
TE CH
T431616D/E
Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
tRP
tRC
tRC
DQ
Ax0 Ax1
Ax2
Ax3
PrechargeAll AutoRefresh Command Command
AutoRefresh Command
Activate Command Bank A
Read Command Bank A
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CLK
TE CH
T431616D/E
Figure 4. Power on Sequene and Auto Refresh (CBR)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE High level is reauired Minimum of 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
A11
A10
Address Key
A0-A9
DQM
tRP
DQ Hi-Z
tRC
PrechargeALL Command Inputs must be stable for 200 µs
1st AutoRefresh Command Mode Register Set Command
(*)
2nd Auto Refresh Command
(*)
Any Command
Note (*) : The Auto Refresh command can be issued before or after Mode Register Set command
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T0
TE CH
T431616D/E
Figure 5. Self Refresh Entry & Exit Cycle
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CLK
*Note 2 *Note 1 *Note 4 *Note 3
tRC(min) tSRX
*Note 7
CKE
tPDE
*Note 5 *Note 6
t IS
CS#
RAS#
*Note 8 *Note 8
CAS#
A11
A0-A9
WE#
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Enter
SelfRefresh Exit
AutoRefresh
Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays "low". Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh. To Exit SelfRefresh Mode 1. System clock restart and be stable before returning CKE high. 2. Enable CKE and CKE should be set high for minimum time of tSRX. 3. CS# starts from high. 4. Minimum tRC is required after CKE going high to complete SelfRefresh exit. 5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh.
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T431616D/E
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=1)
T0 CLK
T 1 T2
T3
T4
T5
T6
T 7
T8
T9
T10 T 11 T1
T13 T14 T15 T16 T17 T1
T19 T20 T21 T22
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
t HZ
DQ Hi-Z
Ax0 Ax1 Ax3 Ax2
Activate Command Bank A Read Command Bank A
Clock Suspend Clock Suspend 2 Cycles 1 Cycle
Clock Suspend 3 Cycles
Note: CKE to CLK disable/enable = 1 clock
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T431616D/E
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
t HZ
DQ Hi-Z
Ax0 Ax1 Ax2 Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
Note: CKE to CLK disable/enable = 1 clock
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T431616D/E
Figure 6.3. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 CLK
T 1 T 2 T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
t HZ
DQ Hi-Z
Ax0 Ax1 Ax2 Ax3
Activate Command Bank A
Read Command Bank A
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
Note: CKE to CLK disable/enable = 1 clock
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TE CH
T431616D/E
Figure 7.1. Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS# Latency = 1)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate Clock Suspend Clock Suspend Command 1 Cycle 2 Cycles Bank A Write Command Bank A
Clock Suspend 3 Cycles
Note: CKE to CLK disable/enable = 1 clock
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T0 CLK
TE CH
T431616D/E
Figure 7.2. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=2)
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
T2 2
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM
DQ Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate Command Bank A
Clock Suspend Clock Suspend 1 Cycle 2 Cycles Write Command Bank A
Clock Suspend 3 Cycles
Note: CKE to CLK disable/enable = 1 clock
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TE CH
T431616D/E
Figure 7.3. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0-A9
RAx
CAx
DQM DQ Hi-Z
DAx0
DAx1
DAx2
DAx3
Activate Command Bank A
Clock Suspend Clock Suspend 1 Cycle 2 Cycles Write Command Bank A
Clock Suspend 3 Cycles
Note: CKE to CLK disable/enable = 1 clock
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CLK
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T431616D/E
Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
t IS
tPDE
Valid
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
DQM
tHZ
Hi-Z DQ
ACTIVE STANDBY Activate Read Command Command Bank A Bank A Power Down Power Down Mode Entry Mode Exit Ax0 Ax1 Ax2 Ax3 PRECHARGE STANDBY
Clock Mask Start
Clock Mask End
Precharge Command Bank A Power Down Mode Entry
Power Down Mode Exit Any Command
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TE CH
T431616D/E
Figure 9.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAw
RAz
A0~A9
RAw CAw
CAx
CAy
RAz
CAz
DQM
DQ Hi-Z
Aw0
Aw1 Aw2
Aw3 Ax0
Ax1
Ay0
Ay1 Ay2
Ay3
Az0
Az1 Az2
Az3
Activate Command Bank A Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Read Command Command Bank A Bank A Activate Command Bank A
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TE CH
T431616D/E
Figure 9.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAw
RAz
A0~A9
RAw
CAw
CAx
CAy
RAz
CAz
DQM
DQ Hi-Z
Aw0
Aw1 Aw2
Aw3
Ax0
Ax1 Ay0
Ay1
Ay2
Ay3
Az0
Az1
Az2
Az3
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
TM Technology Inc. reserves the right P. 34 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 9.3. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAw
RAz
A0~A9
RAw
CAw
CAx
CAy
RAz
CAz
DQM
DQ Hi-Z
Aw0
Aw1
Aw2
Aw3
Ax0 Ax1
Ay0
Ay1
Ay2
Ay3
Az0
Activate Command Bank A
Read Command Bank A
Read Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
TM Technology Inc. reserves the right P. 35 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 10.1. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
RBz
A0~A9
RBw
CBw
CBx
CBy
RBz
CBz
DQM Hi-Z DQ
DBw0 DBw1DBw2
DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Activate Command Bank A Write Command Bank B
Write Command Bank A
Write Command Bank B
Precharge Command Bank B Activate Command Bank B
Write Command Bank B
TM Technology Inc. reserves the right P. 36 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 10.2. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
RBz
A0~A9
RBw
CBw
CBx
CBy
RBz
CBz
DQM
DQ
Hi-Z
DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
Activate Command Bank A
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
TM Technology Inc. reserves the right P. 37 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 10.3. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RBw
RBz
A0~A9
RBw
CBw
CBx
CBy
RBz
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2
Activate Command Bank A
Write Command Bank B
Write Command Bank B
Write Command Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
TM Technology Inc. reserves the right P. 38 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 11.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RBx
RAx
RBy
A0~A9
RBx
CBx
RAx
CAx
RBy
CBy
tRCD
DQM Hi-Z DQ
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 By2
tAC1
tRP
Activate Command Bank B Read Command Bank B
Activate Command Bank A
Precharge Command Bank B Activate Read Command Command Bank B Bank A
Read Command Bank B
Precharge Command Bank A
TM Technology Inc. reserves the right P. 39 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 11.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE CS# High
RAS#
CAS#
WE#
A11
A10
RBx
RAx
RBy
A0~A9
RBx
CBx
RAx
CAx
RBy
CBy
tRCD
DQM
tAC2
tRP
Hi-Z DQ
Bx0
Bx1
Bx2
Bx3 Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2 Ax3
Ax4
Ax5
Ax6
Ax7
By0
By1
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Command Bank B Read Command Bank A
Activate Command Bank B
Read Command Bank B
TM Technology Inc. reserves the right P. 40 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 11.3. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE High
CS#
RAS#
CAS#
WE#
A11 A10
RBx
RAx
RBy
A0~A9
RBx
CBx
RAx
CAx
RBy
CBy
tRCD
DQM
tAC3
tRP
Hi-Z DQ
Bx0
Bx1 Bx2
Bx3
Bx4
Bx5
Bx6 Bx7
Ax0
Ax1 Ax2
Ax3
Ax4
Ax5 Ax6
Ax7
By0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Read Command Bank A
Precharge Command Bank B
Activate Command Bank B
Read Command Bank B
Precharge Command Bank A
TM Technology Inc. reserves the right P. 41 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 12.1. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKEHigh
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RAy
A0~A9
RAx
CAx
RBx CBx
RAy
CAy
tRCD
DQM
tRP
tWR
Hi-Z DQ
DAx0
DAx1 DAx2 DAx3
DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3DBx4 DBx5 DBx6 DBx7
DAy0 DAy1 DAy2 DAy3
Activate Command Bank A Write Command Bank A
Activate Command Bank B Write Command Bank B
Precharge Command Bank A Activate Command Bank A
Precharge Command Bank B
Write Command Bank A
TM Technology Inc. reserves the right P. 42 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 12.2. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE High CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RAy
A0~A9
RAx
CAx
RBx
CBx
RAy
CAy
DQM
tRCD
tWR*
tRP
tWR*
Hi-Z DQ
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1DAy2
DAy3 DAy4
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B Precharge Command Bank A
Activate Command Bank A
Write Command Bank A Precharge Command Bank B
* tWR > tWR(min.)
TM Technology Inc. reserves the right P. 43 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 12.3. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RAy
A0~A9
RAx
CAx
RBx
CBx
RAy
CAy
tRCD
DQM
tWR*
tRP
tWR*
DQHi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0
DAy1 DAy2 DAy3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Precharge Command Bank A
Activate Command Bank A
Write Command Bank A
Precharge Command Bank B
* tWR > tWR(min.)
TM Technology Inc. reserves the right P. 44 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
CAy
CAz
DQM
DQ Hi-Z
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Activate Command Bank A Read Command Bank A
Read Write The Write Data Command is Masked with a Command Bank A Bank A Zero Clock Latency
The Read Data is Masked with a Two Clock Latency
Precharge Command Bank B
TM Technology Inc. reserves the right P. 45 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
CAy
CAz
DQM
DQ Hi-Z
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Activate Command Bank A
Read Command Bank A
Write The Write Data Command is Masked with a Bank A Zero Clock Latency
Read Command Bank A
The Read Data is Masked with a Two Clock Latency
TM Technology Inc. reserves the right P. 46 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
CAy
CAz
DQM
DQ Hi-Z
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
Activate Command Bank A
Read Command Bank A
Write Read The Write Data Command is Masked with a Command Bank A Bank A Zero Clock Latency
The Read Data is Masked with a Two Clock Latency
TM Technology Inc. reserves the right P. 47 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBw
A0~A9
RAx RAx
RBw
CBw
CBx
CBy
CAy
CBz
DQM Hi-Z
tRCD tAC1
DQ
Ax0
Ax1
Ax2
Ax3
Bw0
Bw1
Bx0
Bx1
By0
By1 Ay0
Ay1
Bz0
Bz1
Bz2
Bz3
Activate Command Bank A Read Command Bank A
Activate Command Bank B Read Command Bank B
Read Command Bank B
Read Command Bank B
Read Command Bank A
Read Command Bank B
Precharge Command Bank A
Precharge Command Bank B
TM Technology Inc. reserves the right P. 48 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAx
A0~A9
RAx
CAy
RAx
CBw
CBx
CBy
CAy
CBz
DQM
tRCD
tAC2
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3 Bw0
Bw1
Bx0
Bx1
By0
By1 Ay0
Ay1
Bz0
Bz1
Bz2 Bz3
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Bank B
Read Command Bank B
Read Command Bank B
Read Command Bank A
Read Command Bank B Precharge Command Bank A
Precharge Command Bank B
TM Technology Inc. reserves the right P. 49 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
A0~A9
RAx
CAx
RBx
CBx
CBy
CBz
CAy
DQM DQ Hi-Z
tRCD
tAC3
Ax0
Ax1 Ax2
Ax3 Bx0
Bx1
By0 By1
Bz0
Bz1 Ay0
Ay1
Ay2
Ay3
Activate Command Bank A
Read Command Bank A Activate Command Bank B
Read Command Bank B
Read Command Bank B
Read Command Bank B
Read Prechaerge Command Command Bank A Bank B
Precharge Command Bank A
TM Technology Inc. reserves the right P. 50 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11 A10
RAx
RBw
A0~A9
RAx
CAx
RBw
CBw
CBx
CBy
CAy
CBz
tRP
DQM
tRCD tRRD
tWR tRP
DQ Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1
DBz0 DBz1 DBz2 DBz3
Activate Command Bank A
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank A
Write Command Bank A
Write Command Bank B Precharge Command Bank A
Precharge Command Bank B
TM Technology Inc. reserves the right P. 51 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBw
A0~A9
RAx
CAx
RBw
CBw
CBx
CBy
CAy
CBz
DQM
tRCD tRRD
tRP
tWR
tRP
DQ Hi-Z
DAx0 DAx1 DAx2
DAx3DBw0 DBw1 DBx0
DBx1 DBy0
DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank A
Write Command Bank B Precharge Command Bank A
Precharge Command Bank B
TM Technology Inc. reserves the right P. 52 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBw
A0~A9
RAx
CAx RBw
CBw
CBx
CBy
CAy
CBz
DQM
tRCD tRRD > tRRD(min)
tWR
tRP
tWR(min)
DQ Hi-Z
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate Command Bank A
Activate Command Bank B Write Command Bank A
Write Command Bank B
Write Command Bank B
Write Command Bank B
Write Command Bank A
Write Command Bank B Precharge Command Bank A
Precharge Command Bank B
TM Technology Inc. reserves the right P. 53 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
RBz
A0~A9
RAx
CAx
RBx CBx
CAy
RBy
CBy
RBz
CBz
DQM DQ Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
By3
Bz0
Bz1
Bz2
Bz3
Activate Command Bank A Read Command Bank A
Activate Command Bank B Read with Auto Precharge Command Bank B
Activate Command Bank B Read with Auto Precharge Command Bank A
Read with Auto Precharge Command Bank B
Activate Command Bank B Read with Auto Precharge Command Bank B
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Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
RAz
A0~A9
RAx
CAx
RBx
CBx
RAy
RBy
CBy
RAz
CAz
DQM
DQ Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
By3 Az0
Az1
Az2
Activate Command Bank A
Read Command Bank A
Read with Activate Command Auto Precharge Command Bank B Bank B
Read with Activate Read with Activate Read with Auto Precharge Command Auto Precharge Command Auto Precharge Command Bank B Command Bank A Command Bank A Bank B Bank A
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Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
A0~A9
RAx
CAx RBx
CBx
CAy
RBy
CBy
DQM
DQ Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1 Bx2
Bx3
Ay0
Ay1
Ay2 Ay3
By0 By1
By2
By3
Activate Command Bank A
Activate Command Bank B Read Command Bank A
Read with Auto Precharge Command Bank B
Read with Auto Precharge Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
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Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE High CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
RAz
A0~A9
RAx CAx
RBx
CBx
CAy
RBy
CBy
RAz
CAz
DQM
DQ Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3
DAz0 DAz0 DAz0 DAz0
Activate Command Bank A Write Command Bank A
Write with Activate Command Auto Precharge Command Bank B Bank B
Write with Auto Precharge Command Bank A
Write with Activate Command Auto Precharge Command Bank B Bank B
Activate Command Bank A Write with Auto Precharge Command Bank A
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Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
RAz
A0~A9
RAx
CAx
RBx
CBx
CAy
RBy
CBy
RAz
CAz
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3
Activate Command Bank A
Write Command Bank A
Activate Write with Command Auto Precharge Bank B Command Bank B
Write with Auto Precharge Command Bank A
Activate Write with Write with Activate Command Auto Precharge Command Auto Precharge Bank B Command Command Bank A Bank B Bank A
TM Technology Inc. reserves the right P. 58 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE High
CS#
RAS#
CAS#
WE#
A11
`
A10
RAx
RBx
RBy
A0~A9
RAx
CAx
RBx
CBx
CAy
RBy
CBy
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3
Activate Command Bank A
Activate Command Bank B Write Command Bank A
Write with Auto Precharge Command Bank B
Write with Auto Precharge Command Bank A
Activate Command Bank B
Write with Auto Precharge Command Bank B
TM Technology Inc. reserves the right P. 59 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
A0~A9
RAx
CAx RBx
CBx
RBy
DQM
tRRD
tRP
DQ Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1 Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Bx+6 Bx+7
Activate Command Bank A
Activate Command Bank B The burst counter wraps from the highest order Read page address back to zero Command during this time interval Bank A
Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Precharge Command Bank B Burst Stop Activate Command Command Bank B
TM Technology Inc. reserves the right P. 60 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
A0~A9
RAx
CAx
RBx
CBx
RBy
tRP
DQM
DQ Hi-Z
Ax
Ax+1 Ax+2 Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3
Bx+4 Bx+5
Bx+6
Activate Command Bank A
Read Command Bank A
Activate Read Precharge Full Command Command Page burst operation does not Command Bank B Bank B terminate when the burst length is satisfied; Bank B The burst counter wraps the burst counter increments and continues from the highest order bursting beginning with the starting address. page address back to zero Burst Stop during this time interval Command
Activate Command Bank B
TM Technology Inc. reserves the right P. 61 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
A0~A9
RAx
CAx
RBx
CBx
RBy
DQM
tRP
DQ Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Full Page burst operation does not Precharge Command terminate when the burst length is Bank B satisfied; the burst counter increments and continues bursting beginning with the Burst Stop starting address. Command
Activate Command Bank B
TM Technology Inc. reserves the right P. 62 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1)
T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
A0~A9 DQM
RAx
CAx
RBx
CBx
RBy
DQ Hi-Z
DBx DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1
DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6 DBx+ 7
Activate Command Bank A
Activate Command Bank B The burst counter wraps from the highest order Write page address back to zero Command during this time interval Bank A
Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Data is ignored
Precharge Command Bank B Burst Stop Activate Command Command Bank B
TM Technology Inc. reserves the right P. 63 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE High CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
A0~A9
RAx
CAx
RBx
CBx
RBy
DQM
DQ
Hi-Z
DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx
DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6
Activate Command Bank A
Write Command Bank A
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Data is ignored
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
TM Technology Inc. reserves the right P. 64 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBy
A0~A9
RAx
CAx
RBx
CBx
RBy
DQM
Data is ignored
DQ Hi-Z
DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx
DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5
Activate Command Bank A
Write Command Bank A
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
TM Technology Inc. reserves the right P. 65 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
CKE CS# High
RAS#
CAS#
WE#
A11
A10
RAx
A0~A9
RAx
CAx
CAy
CAz
LDQM
UDQM
DQ0 - DQ7
Ax0
Ax1
Ax2
DAy1 DAy2
Az1
Az2
DQ8 - DQ15
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az2
Az3
Activate Command Bank A
Read Upper 3 Bytes Command are masked Bank A
Lower Byte is masked
Write Upper 3 Bytes Read Command are masked Command Bank A Bank A
Lower Byte is masked
Lower Byte is masked
TM Technology Inc. reserves the right P. 66 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 21. Random Row Read (Interleaving Banks)
(Burst Length=2, CAS# Latency=1)
T0 CLK
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK1
CKE High
Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A
CS#
RAS#
CAS#
WE#
A11
A10
RBu
RAu
RBv
RAv
RBw
RAw
RBx
RAx
RBy
RAy
RBz
RAz
A0~A9
RBu
CBu
RAu CAu
RBv CBv
RAv
CAv
RBw CBw
RAw CAw RBx
CBx RAx CAx
RBy CBy
RAy CAy RBz
CBz RAz
DQM
tRP
tRP
tRP
tRP
tRP
tRP
tRP
tRP
tRP
tRP
DQ
Bu0
Bu1 Au0
Au1
Bv0 Bv1
Av0
Av1
Bw0 Bw1
Aw0
Aw1 Bx0
Bx1
Ax0
Ax1 By0
By1
Ay0 Ay1
Bz0
Activate Command Bank B
Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate Command Command Command Command Command Command Command Command Command Command Command Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Read Read Read Read Read Read Read Read Read Read Read Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge
TM Technology Inc. reserves the right P. 67 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBw
A0~A9
RAx
RBx
CAx
CBx
CAy
CBy
CAz
CBz
RBw
tRP
DQM
tRRD
DQ
tRCD
Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2
Activate Command Bank A
Activate Command Bank B
Read Command Bank B Read Read Command Command Bank A Bank A
Read Command Bank B
Read Command Bank A
Read Command Bank B
Precharge Command Bank B (Precharge Temination) Activate Command Bank B
TM Technology Inc. reserves the right P. 68 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RBx
RBw
A0~A9
RAx
RBx CAx
CBx
CAy
CBy
CAz
CBz
RBw
tWR
DQM
tRP
tRRD
DQ
tRCD
DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Activate Command Bank A
Activate Command Bank B
Write Command Bank B Write Write Command Command Bank A Bank A
Write Command Bank B
Write Command Bank A
Write Command Bank B
Precharge Command Bank B (Precharge Temination) Activate Write Data Command Bank B is masked
TM Technology Inc. reserves the right P. 69 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
T0
TE CH
T431616D/E
Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)
T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAy
RAz
A0~A9
RAx
CAx
RAy
CAy
RAz CAz
tWR tRP
DQM
tRP
Precharge Termination of a Read Burst.
DQ
DAx0 DAx1 DAx2 DAx3 DAx4
Ay0
Ay1 Ay2
DAz0
DAz1 DAz2 DAz3
DAz4 DAz5
DAz6 DAz7
Read Activate Precharge Termination Precharge Command Command Command of a Write Burst. Bank A Bank A Bank A Write data is masked. Write Activate Command Command Bank A Bank A
Precharge Command Bank A
Write Command Bank A
Activate Command Bank A
TM Technology Inc. reserves the right P. 70 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
TE CH
T431616D/E
Figure 24.2. Precharge Termination of a Burst
(Burst Length=8 or Full Page, CAS# Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE High
CS#
RAS#
CAS#
WE#
A11
A10
RAx
RAy
RAz
A0~A9
RAx
CAx
RAy
CAy
RAz
CAz
tWR
DQM
tRP
tRP
tRP
DQ
DAx0 DAx1 DAx2 DAx3
Ay0
Ay1
Ay2
Az0
Az1
Az2
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Precharge Termination of a Write Burst. Write data is masked.
Precharge Read Command Command Bank A Bank A Precharge Termination of a Read Burst
TM Technology Inc. reserves the right P. 71 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
CLK
TE CH
T431616D/E
Figure 24.3. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
CKE CS# High
RAS#
CAS#
WE#
A11
A10
RAx
RAy
RAz
A0~A9
RAx
CAx
RAy
CAy
RAz
tWR
DQM
tRP
tRP
DQ
DAx0 DAx1
Ay0
Ay1
Ay2
Activate Command Bank A
Write Command Bank A Write Data is masked
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Precharge Termination Command of a Read Burst Bank A
Precharge Termination of a Write Burst
TM Technology Inc. reserves the right P. 72 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
tm
50
TE CH
T431616D/E
50 Pin TSOP II Package Outline Drawing Information
26
HE
E
0.254
θ° L L1
1 D
25
A1 A2 A
S
B
e
L
y
L1
Symbol Min 0.002 0.012 0.82 0.398 -
A A1 A2 B c D E e 0.459 0.463 0.467 HE 0.016 0.020 0.024 L 0.0315 L1 0.035 S 0.004 y 0° 5° θ Notes : 1. Dimension D&E do not include interiead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension : mm
Dimension in inch Normal 0.005 0.015 0.006 0.825 0.400 0.031
Max 0.047 0.008 0.039 0.018 0.83 0.402 -
Min 0.05 0.3 20.82 10.11 11.66 0.40 0°
Dimension in mm Normal Max 1.20 0.125 0.20 1 0.375 0.45 0.155 20.95 21.08 10.16 10.21 0.80 11.76 0.50 0.80 0.88 11.86 0.60 0.10 5°
TM Technology Inc. reserves the right P. 73 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
C
tm
TE CH
T431616D/E
60-Ball (6.4mm x 10.1mm)VFBGA Units in mm
TOP VIEW
A1 CORNER
A1 CORNER
BOTTOM VIEW
R P N ML K J H GF E D C B A
A B CD E F G H J KLMN P R
C
1 2 3 4 5 6 7 1 2 3
AB D
4 5 6 7
D1 B1 E3 E2 E E1 A1
C1
SEATING PLANE
Symbol A A1 B B1 C C1 D D1 E E1 E2 E3
Dimension in mm Min Nom Max 6.30 6.40 6.50 10.00 10.10 10.20 3.90(typ) 9.10(typ) 0.65(typ) 0.65(typ) 0.35 0.4 0.45 0.35 0.4 0.45 0.22 0.27 0.32 1.00* 0.21 0.42 0.45 0.48
Dimension in inch Min Nom Max 0.248 2.52 2.56 0.394 0.398 0.402 0.154(typ) 0.358(typ) 0.026(typ) 0.026(typ) 0.014 0.016 0.018 0.014 0.016 0.018 0.009 0.11 0.13 0.039 0.008 0.017 0.018 0.019
Note : * if lead free package “E1” max.=1.2mm(0.047 inch)
TM Technology Inc. reserves the right P. 74 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
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