T66H0002A-Y

tm TE CH T66H0002A T66H0002A FEATURES ! ! Number of LCD drive outputs : 160 Supply voltage for LCD drive : +15.0 to +45.0 V ! Supply voltage for the logic system : +2.5 to +5.5 V ! ! Low power consumption Low output impedance 160 output LCD Segment/Common Driver IC DESCRIPTION The T66H0002A is a 160-output segment/common driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The T66H002A is good both as a segment driver and a common driver, and it can create a low power consuming, high resolution LCD. Segment mode: 1. Shift clock frequency : 14 MHz (MAX.) (VDD=+5.0V±10%) : 8 MHz(MAX.) 2. Adopts a data bus system 3. 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin 4. Automatic transfer function of an enable signal 5. Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 160 bits of input data 6. Line latch circuits are reset when / DISPOFF low active (VDD=+2.5V~+4.5V) TM Technology Inc. reserves the right P. 1 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm - TE CH T66H0002A Common mode: Shift clock frequency : 4 MHz (MAX.) Built-in 160-bit bi-directional shift register (divisible into 80 bits x 2) Available in a single mode (160-bit shift register) or in a dual mode (80-bit shift register x 2) a. Y1 b. Y160 c. Y1 d. Y160 Y160 Single mode Y1 Single mode Y80, Y81, Y81 Y80 Y160 Dual mode Y1 Dual mode The above 4 shift directions are pin selectable Part Number Examples Part No. T66H0002A-Y T66H0002A-AY T66H0002A Pkg. Description TCP Pitch 0.18mm, refer to Appendix TCP Pitch 0.22mm, refer to Appendix COG Refer to Pads List TM Technology Inc. reserves the right P. 2 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm 190-PIN TCP 186-PIN TCP PIN CONNECTIONS TM Technology Inc. reserves the right P. 3 to change products or specifications without notice. Y160 Y159 Y158 Y160 Y159 Y158 160 159 158 160 159 158 TE CH CHIP SURFACE CHIP SURFACE Y3 Y2 Y1 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Y3 Y2 Y1 3 2 1 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 V0L V12L V43L VSS L/R VDD S/C EIO2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 XCK /DISPOFF LP EIO1 FR MD VSS V43R V12R V0R 3 2 1 V0L V12L V43L V5L VSS L/R VDD S/C EIO2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 XCK /DISPOFF LP EIO1 FR MD NC NC VSS V5R V43R V12R V0R T66H0002A Publication Date: JUL. 2002 Revision:A tm 1 to 160 161, 186 162, 185 163, 184 166 167 168, 180 169 to 175 176 177 178 179 181 165 182 164,183 TE CH T66H0002A PIN DESCRIPTION For 186-PIN TCP PIN NO. SYMBOL Y1-Y160 V0L, V0R V12L,V12R V43L,V43R VDD S/C EIO2, EIO1 DI0-DI6 DI7 XCK /DISPOFF LP FR L/R MD VSS I/O O I I/O I I I I I I I I - DESCRIPTION LCD drive output Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for logic system (+2.5V to +5.5V) Segment mode/common mode selection Input/output for chip select or data od shift register Display data input at segment mode Display data input at segment mode/Dual mode data input Clock input for taking display data at segment mode Control input for output of non-select level Latch pules input /shift clock input for shift register AC-converting signal input for LCD drive waveform Display data shift direction selection Mode selection input Ground(0V) For 190-PIN TCP PIN NO. SYMBOL 1 to 160 161, 190 162, 189 163, 188 164,187 167 168 169, 181 170 to 176 177 178 179 180 182 166 183 184,185 165,185 Y1-Y160 V0L, V0R V12L,V12R V43L,V43R V5L,V5R VDD S/C EIO2, EIO1 DI0-DI6 DI7 XCK /DISPOFF LP FR L/R MD NC VSS I/O O I I/O I I I I I I I I I - DESCRIPTION LCD drive output Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Power supply for logic system (+2.5V to +5.5V) Segment mode/common mode selection Input/output for chip select or data od shift register Display data input at segment mode Display data input at segment mode/Dual mode data input Clock input for taking display data at segment mode Control input for output of non-select level Latch pules input /shift clock input for shift register AC-converting signal input for LCD drive waveform Display data shift direction selection Mode selection input Not Connection Ground(0V) TM Technology Inc. reserves the right P. 4 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A INPUT/OUTPUT CIRCUITS TM Technology Inc. reserves the right P. 5 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A TM Technology Inc. reserves the right P. 6 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A BLOCK DIAGRAM TM Technology Inc. reserves the right P. 7 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK Active Control FUNCTION In case of segment mode, controls the selection or non-selection of the chip. Following and LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 160 bits of data have been read in. Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode in latch circuit; after that they are put on the internal data 8 bits at a time. In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by the control logic. For every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. In case of segment mode, latches the data on the data bus. The latch state of each LCD rive output pin is controlled by the control logic and the data latch control; 160 bits of data are read in 20 sets of 8 bits. In case of segment mode, all 160 bits which have been read into the data latch are simultaneously latched at the falling edge of the LP signal, and are output to the level shifter block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. The logic voltage signal is level-shifted to the LCD drive voltage level, and in output to the driver block. Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4 levels(V0,V12,V43, or Vss) based on the S/C, FR and /DISPOFF signals. Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are rest and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 160 bits of data are read in , and the chip in non-selected. In case of common mode, controls the direction of data shift. SP Conversion & Data Control Data Latch Control Data Latch Line Latch/ Shift Register Level Shifter 4-Level driver Control Logic TM Technology Inc. reserves the right P. 8 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm VDD Vss TE CH T66H0002A FUNCTIONAL DESCRIPTION Pin Functions (Segment mode) SYMBOL FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage • Normally use the bias voltages set by a resistor divider. • Ensure that voltages are set such that Vss < V43 < V12 < V0. • ViL and ViR ( i= 0 , 12 , 43) must connect to an external power supply , and supply regular voltage which is assigned by specification for each power pin. Input pins for display data • In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. Connect DI7-DI4 to Vss or VDD. • In 8-bit parallel input mode, input data into the 8 pins, DI7- DI0. • Refer to “ RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. Clock input pin for taking display data • Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data • Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data • When set to Vss level “L” , data is read sequentially from Y160 to Y1. • When set to VDD level “H” , data is read sequentially from Y1 to Y160. • Refer to “ RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. Control input pin for output of non-select level • The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. • When set to Vss level “L”, the LCD drive output pins (Y1-Y160) are set to level Vss. • When set to “L” , the contents of the line latch are reset , but the display data are read in the data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is canceled , the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. • Table of truth values is shown in “TRUTH TABLE” in Functional Operations. AC signal input pin for LCD drive waveform • The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. • Normally it inputs a frame inversion signal. • The LCD drive output pins’ output voltage levels can be set using the line latch output signal and the FR signal. • Table of truth values is shown in “TRUTH TABLE” in Functional Operations. V0L , V0R V12L , V12R V43L , V43R DI 7 , D I 0 XCK LP L/R /DISPOFF FR TM Technology Inc. reserves the right P. 9 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm MD TE CH T66H0002A SYMBOL FUNCTION Mode selection pin • When set to Vss level “L”, 4 bit parallel input mode is set. • When set to VDD level “H”, 8 bit parallel input mode is set. • Refer to “ RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. Segment mode/common mode selection pin • When set to VDD level “H”, segment mode is set. Input/output pins for chip selection • When L/R input is at Vss level “L” , EIO1 is set for output , and EIO2 is set for input. • When L/R input is at VDD level “H” , EIO1 is set for input , and EIO2 is set for output. • During output , set to “H” while LP·/XCK is “H” and after 160 bits of data have been read , set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”. • During input , the chip is selected while EI is set to “L” after the LP signal is input. The chip is non-selected after 160 bits of data have been read. LCD drive output pins • Corresponding directly to each bit of the data latch, one level (V0, V12, V43 or Vss) is selected and output. • Table of truth values is shown in “TRUTH TABLE” in Functional Operations. S/C EIO1 , EIO2 Y1-Y160 TM Technology Inc. reserves the right P. 10 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm VDD Vss TE CH T66H0002A (Common mode) SYMBOL FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage • Normally use the bias voltages set by a resistor divider. • Ensure that voltages are set such that Vss < V43 < V12 < V0. • ViL and ViR ( i = 0 , 12 , 43) must connect to an external power supply , and supply regular voltage which is assigned by specification for each power pin. Shift data input/output pin for bi-directional shift register • Output pin when L/R is at Vss level “L” , input pin when L/R is at VDD level “H”. • When L/R = H, EIO1 is used as input pin, it will be pulled down. • When L/R = L, EIO1 is used as output pin, it won’t be pulled down. • Refer to “ RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. Shift data input/output pin for bi-directional shift register • Input pin when L/R is at Vss level “L” , output pin when L/R is at VDD level “H”. • When L/R = L, EIO2 is used as input pin, it will be pulled down. • When L/R = H, EIO2 is used as output pin, it won’t be pulled down. • Refer to “ RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. Shift Clock pulse input pin for bi-directional shift register • Data is shifted at the falling edge of the clock pulse. Input pin for selecting the shift direction of bi-directional shift register • Data is shifted from Y160 to Y1 when set to Vss level “L” , and data is shifted from Y1 to Y160 when set to VDD level “H”. • Refer to “ RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. Control input pin for output of non-select level • The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. • When set to Vss level “L”, the LCD drive output pins (Y1-Y160) are set to level V5. • When set to “L”, the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled , the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP. At that time , if /DISPOFF removal time does not correspond to what is shown in AC characteristic, the shift data is not read correctly. • Table of truth value is shown in “TRUTH TABLE” in Functional Operations. AC signal input pin for LCD drive waveform • The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. • Normally it inputs a frame inversion signal. • The LCD drive output pins’ output voltage levels can be set using the line latch output signal and the FR signal. • Table of truth value is shown in “TRUTH TABLE” in Functional Operations. V0L , V0R V12L , V12R V43L , V43R EIO1 EIO2 LP L/R /DISPOFF FR TM Technology Inc. reserves the right P. 11 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm MD TE CH T66H0002A SYMBOL FUNCTION Mode selection pin • When set to Vss level “L” , single operation is selected ; when set to VDD level “H” , dual mode operation is selected. • Refer to “ RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. Dual mode data input pin • According to the data shift direction of the data shift register , data can be input starting from the 81st bit. • When the chip is used in dual mode , DI7 will be pulled down. • When the chip is used in single mode , DI7 won’t be pulled down. • Refer to “ RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. Segment mode/common mode selection pin • When set to Vss level “L, common mode is set. Not used • Connect DI6-DI0 to Vss or VDD, avoiding floating. Not used • XCK is pulled down in common mode, so connect to Vss or open. LCD drive output pins • Corresponding directly to each bit of the data latch, one level (V0, V12, V43 or Vss) is selected and output. • Table of truth values is shown in “TRUTH TABLE” in Functional Operations. DI 7 S/C DI6-DI0 XCK Y1-Y160 TM Technology Inc. reserves the right P. 12 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm FR L L H H X TE CH T66H0002A Functional Operations TRUTH TABLE (Segment Mode) Latch Data L H L H X /DISPOFF H H H H L LCD Drive Output Voltage Level (Y1-Y160) V43 Vss V12 V0 Vss (Common Mode) FR L L H H X Latch Data L H L H X /DISPOFF H H H H L LCD Drive Output Voltage Level (Y1-Y160) V43 V0 V12 Vss Vss NOTES: · Vss < V43 < V12 < V0, L: Vss (0 V), H: VDD (+2.5 to +5.5 V), X : Don’t care · “Don’t care” should be fixed to “H” or “L”, avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage which is assigned by specification for each power pin. TM Technology Inc. reserves the right P. 13 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS (Segment Mode) (a) 4-bit Parallel Input Mode MD L/R EIO1 EIO2 DATA NUMBER OF CLOCKS IINPU 40 Clock 39 Clock 38 Clock … 3 Clock 2 Clock 1 Clock T DI 0 L L Output Input DI 1 DI 2 DI3 DI 0 L H Input Output DI 1 DI 2 DI3 Y1 Y2 Y3 Y4 Y160 Y159 Y158 Y157 Y5 Y6 Y7 Y8 Y156 Y155 Y154 Y153 Y9 Y10 Y11 Y12 Y152 Y151 Y150 Y149 … … … … … … … … Y149 Y150 Y151 Y152 Y12 Y11 Y10 Y9 Y153 Y154 Y155 Y156 Y8 Y7 Y6 Y5 Y157 Y158 Y159 Y160 Y4 Y3 Y2 Y1 TM Technology Inc. reserves the right P. 14 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm MD TE CH T66H0002A (b) 8 bit Parallel input Mode L/R EIO1 EIO2 DATA NUMBER OF CLOCKS IINPU 20 Clock 19 Clock 18 Clock … 3 Clock 2 Clock 1 Clock T DI 0 DI 1 DI 2 H L Output Input DI 3 DI 4 DI 5 DI 6 DI7 DI 0 DI 1 DI 2 H H Input Output DI 3 DI 4 DI 5 DI 6 DI7 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y160 Y159 Y158 Y157 Y156 Y155 Y154 Y153 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y152 Y151 Y150 Y149 Y148 Y147 Y146 Y145 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y144 Y143 Y142 Y141 Y140 Y139 Y138 Y137 … … … … … … … … … … … … … … … … Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 (Common Mode) MD L (Single) H (Dual) L/R L H L H Data Transfer Direction Y160 # Y1 Y1 # Y160 Y160 # Y81 Y80 #Y1 Y1 #Y80 Y81#Y160 EIO1 Output Input Output Input EIO2 Input Output Input Output DI7 X X Input Input NOTES: • L: Vss (0 V ), H: VDD (+2.5 to +5.5 V), X: Don’t care • “Don’t care” should be fixed to “H” or “L”, avoiding floating. TM Technology Inc. reserves the right P. 15 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS (a) When L/R = “L” (b) When L/R = “H” TM Technology Inc. reserves the right P. 16 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A CONNECTION EXAMPLES FOR PLURAL COMMON DRIVERS (a) Single Mode (L/R = “L”) (b) Single Mode (L/R = “H”) TM Technology Inc. reserves the right P. 17 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A (c) Dual Mode (L/R = “L”) (d) Dual Mode (L/R = “H”) TM Technology Inc. reserves the right P. 18 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A PRECAUTIONS Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows. ! When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power. ! It is advisable to connect the serial resister (50 to 100 Ω) or fuse to the LCD drive power V0 of the system as a current limiter. Set up a suitable value of the resister in consideration of the display grade. And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level V5 on /DISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here. TM Technology Inc. reserves the right P. 19 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage(1) SYMBOL APPLICABLE PINS VDD VDD V0 V0L,V0R V12 V43 V12L, V12R V43L, V43R DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, /DISPOFF, TEST1, TEST2 RATING -0.3 to +7.0 -0.3 to +45.0 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 UNIT V V V V 1,2 NOTE Supply voltage(2) Input voltage Storage temperature VI Tstg -0.3 to VDD + 0.3 -45 to +125 V ºC NOTES: 1. TA = +25 ºC 2. The maximum applicable voltage on any pin with respect to Vss (0V). RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage(1) Supply voltage(2) Operating temperature AYMBOL APPLICABLE PINS MIN. VDD VDD +2.5 V0 V0L,V0R +10.0 TOPR -20 TYP. MAX. UNIT NOTE +5.5 V 1,2 +45.0 V +85 ºC NOTES: 1. The applicable voltage on any pin with respect to Vss (0V). 2. Ensure that voltage are set such that Vss < V43 < V12 < V0. TM Technology Inc. reserves the right P. 20 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A ELECTRICAL CHARACTERISTICS DC Characteristics (Segment Mode) PARAMETER Input “Low” voltage Input “High” voltage Output “Low” voltage Output “High” voltage Input leakage current (Vss = 0V, VDD = +2.5 to +5.5V, V0 = +10.0 to +45.0V, TOPR = -20 to +85 ºC) SYMBOL VIL VIH VOL VOH ILIL ILIH IOL = +0.4mA IOH = -0.4mA VI = Vss VI = VDD Vo=40V CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE DI7-DI0, XCK, LP, 0.2VDD V L/R, FR, MD, S/C, 0.8VDD V EIO1, EIO2, /DISPOFF +0.4 V EIO1, EIO2 VDD-0.4 V DI7-DI0, XCK, LP, -10.0 uA L/R, FR, MD, S/C, +10.0 uA EIO1, EIO2, /DISPOFF 0.7 Y1 – Y160 1.0 1.5 Vss VDD VDD V0L,V0R 1.0 1.5 2.0 30.0 4.0 4.0 500.0 uA mA mA uA 1 2 3 4 kOhm Output resistance RON |•VON| Vo=30V =0.5V Vo=20V Standby current Supply current(1) (Non-selection) Supply current(2) (Selection) Supply current(3) ISTB IDD1 IDD2 Io NOTES: 1. VDD = +5.0V, V0 = +45.0 V, VI = Vss. 2. VDD = +5.0V, V0 = +45.0 V,fXCK = 14 MHz, non-load, EI = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +5.0V, V0 = +45.0 V,fXCK = 14 MHz, non-load, EI = Vss. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +5.0V, V0 = +45.0 V,fXCK = 14 MHz, fLP = 41.6 kHz, fFR = 80 Hz, non-load. The input data is turned over by data taking clock (4-bit parallel input mode). TM Technology Inc. reserves the right P. 21 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A (Common Mode) PARAMETER Input “Low” voltage Input “High” voltage Output “Low” voltage Output “High” voltage Input leakage current (Vss = 0V, VDD = +2.5 to +5.5V, V0 = +10.0 to +45.0V, TOPR = -20 to +85 ºC) SYMBOL VIL VIH VOL VOH ILIL ILIH IOL = +0.4mA IOH = -0.4mA VI = Vss VI = VDD VI = VDD Vo=40V |•VON| Vo=30V =0.5V Vo=20V CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE DI7-DI0, XCK, LP, 0.2VDD V L/R, FR, MD, S/C, 0.8VDD V EIO1, EIO2, /DISPOFF +0.4 V EIO1, EIO2 VDD-0.4 V DI7-DI0, XCK, LP, -10.0 uA L/R, FR, MD, S/C, EIO1, EIO2, /DISPOFF DI6-DI0, LP, L/R, FR, +10.0 uA MD, S/C, /DISPOFF DI7, XCK, EIO1, EIO2 100.0 uA 0.7 Y1 – Y160 1.0 1.5 Vss VDD V0L,V0R 1.0 1.5 2.0 30.0 80 160 uA uA uA 1 2 2 k• Input pull-down current IPD Output resistance RON Standby current Supply current(1) Supply current(2) ISTB IDD Io NOTES: 1.VDD = +5.0V, V0 = +45.0 V, VI = Vss. 2.VDD = +5.0V, V0 = +45.0 V, fLP = 41.6 kHz, fFR = 80 Hz, 1/480 duty operation, no-load. TM Technology Inc. reserves the right P. 22 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A AC Characteristics (Segment Mode 1) (Vss = 0V, VDD = +4.5 to +5.5V, V0 = +10.0 to +45.0V, TOPR = -20 to +85 ºC) PARAMETER Shift clock period Shift clock “H” pulse width Shift clock “L” pulse width Data setup time Data hold time Latch pulse “H” pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time /DISPOFF removal time /DISPOFF “L” pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL twck twckh twckl tDS tDH twLPH tLD tSL tLS tLH ts tR tF tSD tWDL tD tPD1,tPD2 tPD3 CL= 15 pF CL= 15 pF CL= 15 pF CONDITIONS tR,tF • 10 ns MIN. 71 23 23 10 20 23 0 25 25 25 21 TYP. MAX. UNIT NOTE ns 1 ns ns ns ns ns ns ns ns ns ns 50 ns 2 50 ns 2 ns us 40 1.2 1.2 ns us us 100 1.2 NOTES : 1. Takes the cascade connection into consideration 2. (twck - twckH – twckL )/2 is maximum in the case of high speed operation. TM Technology Inc. reserves the right P. 23 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A AC Characteristics (Segment Mode 2) (Vss = 0V, VDD = +2.5 to +4.5V, V0 = +10.0 to +45.0V, TOPR = -20 to +85 ºC) PARAMETER Shift clock period Shift clock “H” pulse width Shift clock “L” pulse width Data setup time Data hold time Latch pulse “H” pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Enable setup time Input signal rise time Input signal fall time /DISPOFF removal time /DISPOFF “L” pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL twck twckh twckl tDS tDH twLPH tLD tSL tLS tLH ts tR tF tSD tWDL tD tPD1,tPD2 tPD3 CL= 15 pF CL= 15 pF CL= 15 pF CONDITIONS tR,tF • 11 ns MIN. 125 51 51 30 40 51 0 51 51 51 36 TYP. MAX. UNIT NOTE ns 1 ns ns ns ns ns ns ns ns ns ns 50 ns 2 50 ns 2 ns us 78 1.2 1.2 ns us us 100 1.2 NOTES: 1.Takes the cascade connection into consideration. 2.(twck - twckH – twckL )/2 is maximum in the case of high speed operation. TM Technology Inc. reserves the right P. 24 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A Timing Chart of Segment Mode TM Technology Inc. reserves the right P. 25 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A (Common Mode) (Vss = 0V, VDD = +2.5 to +5.5V, V0 = +10.0 to +45.0V, TOPR = -20 to +85 ºC) PARAMETER Shift clock period Shift clock “H” pulse width Data setup time Data hold time Input signal rise time Input signal fall time /DISPOFF removal time /DISPOFF “L” pulse width Output delay time (1) Output delay time (2) Output delay time (3) SYMBOL twck twckH tSU tH tR tF tSD tWDL tDL tPD1,tPD2 tPD3 100 1.2 CL= 15 pF CL= 15 pF CL= 15 pF 200 1.2 1.2 CONDITIONS tR,tF • 20 ns VDD = +5.0±0.5V VDD = +2.5 to+4.5V MIN. 250 15 30 30 50 50 50 TYP. MAX. UNIT ns ns ns ns ns ns ns ns us ns us us TM Technology Inc. reserves the right P. 26 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A Timing Chart of Common Mode TM Technology Inc. reserves the right P. 27 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A Timing Chart Of 4-Device Cascade Connection Of Segment Drivers TM Technology Inc. reserves the right P. 28 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm TE CH T66H0002A SYSTEM CONFIGURATION EXAMPLE TM Technology Inc. reserves the right P. 29 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm D PAD160 D TE CH T66H0002A Pads List D PAD1 D T66H0002A D D PAD161 D D D D PAD193 D “D” means dummy pads which are floating inside the chip. PAD SIZE : OUTPAD = 55x72(Pad 1 to Pad 160) INPAD = 70x72(Pad 161 to Pad 193) DUMMY = 70x80 OPEN WINDOW : OUTPAD = 29x46 INPAD = 44x46 DUMMY = 44x54 BUMP SIZE : OUTPAD = 43x60 INPAD = 54x56 DUMMY = 54x64 BUMP HEIGHT = 18 CHIP SIZE = 10100 X 1030 (WITHOUT SCRIBE LINE) SCRIBE LINE = 80 UNIT = um Pad No. Pin Name X Y 1 4785.95 398.4 Y1 2 4725.95 398.4 Y2 TM Technology Inc. reserves the right P. 30 to change products or specifications without notice. Pad No. Pin Name X Y 38 2565.95 398.4 Y38 39 2505.95 398.4 Y39 Publication Date: JUL. 2002 Revision:A tm 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 TE CH Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 4665.95 4605.95 4545.95 4485.95 4425.95 4365.95 4305.95 4245.95 4185.95 4125.95 4065.95 4005.95 3945.95 3885.95 3825.95 3765.95 3705.95 3645.95 3585.95 3525.95 3465.95 3405.95 3345.95 3285.95 3225.95 3165.95 3105.95 3045.95 2985.95 2925.95 2865.95 2805.95 2745.95 2685.95 2625.95 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 Y 398.4 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 T66H0002A 2445.95 2385.95 2325.95 2265.95 2205.95 2145.95 2085.95 2025.95 1965.95 1905.95 1845.95 1785.95 1725.95 1665.95 1605.95 1545.95 1485.95 1425.95 1365.95 1305.95 1245.95 1185.95 1125.95 1065.95 1005.95 945.95 885.95 825.95 765.95 705.95 645.95 585.95 525.95 465.95 405.95 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 Pad No. Pin Name X 75 345.95 Y75 Pad No. Pin Name X Y 112 Y112 -1906.2 398.4 5 Publication Date: JUL. 2002 Revision:A TM Technology Inc. reserves the right P. 31 to change products or specifications without notice. tm 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 TE CH Y76 Y77 Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100 Y101 285.95 225.95 165.95 105.95 46.95 -46.25 398.4 398.4 398.4 398.4 398.4 398.4 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 T66H0002A -1966.2 5 -2026.2 5 -2086.2 5 -2146.2 5 -2206.2 5 -2266.2 5 -2326.2 5 -2386.2 5 -2446.2 5 -2506.2 5 -2566.2 5 -2626.2 5 -2686.2 5 -2746.2 5 -2806.2 5 -2866.2 5 -2926.2 5 -2986.2 5 -3046.2 5 -3106.2 5 -3166.2 5 -3226.2 5 -3286.2 5 -3346.2 5 -3406.2 5 -3466.2 5 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 -106.25 398.4 -166.25 398.4 -226.25 398.4 -286.25 398.4 -346.25 398.4 -406.25 398.4 -466.25 398.4 -526.25 398.4 -586.25 398.4 -646.25 398.4 -706.25 398.4 -766.25 398.4 -826.25 398.4 -886.25 398.4 -946.25 398.4 -1006.2 5 -1066.2 5 -1126.2 5 -1186.2 5 -1246.2 5 398.4 398.4 398.4 398.4 398.4 TM Technology Inc. reserves the right P. 32 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm 102 103 104 105 106 107 108 109 110 111 TE CH Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 -1306.2 5 -1366.2 5 -1426.2 5 -1486.2 5 -1546.2 5 -1606.2 5 -1666.2 5 -1726.2 5 -1786.2 5 -1846.2 5 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 139 140 141 142 143 144 145 146 147 148 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 T66H0002A -3526.2 5 -3586.2 5 -3646.2 5 -3706.2 5 -3766.2 5 -3826.2 5 -3886.2 5 -3946.2 5 -4006.2 5 -4066.2 5 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 Pad No. Pin Name X 149 Y149 -4126.2 5 150 Y150 -4186.2 5 151 Y151 -4246.2 5 152 Y152 -4306.2 5 153 -4366.2 Y153 5 154 -4426.2 Y154 5 155 Y155 -4486.2 5 156 Y156 -4546.2 5 157 Y157 -4606.2 5 158 Y158 -4666.2 5 159 -4726.2 Y159 5 160 Y160 -4786.2 5 161 -4754.4 V0L 162 -4669.4 V0L 163 V12L -4541.0 5 Y 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 398.4 -434 -434 -434 Pad No. Pin Name X 182 DISPOFF 2897.6 183 184 185 186 187 188 189 190 191 192 193 LP EIO1 FR MD GND GND V5R V43R V12R V0R V0R RT 3169.4 3259.4 3531.2 3621.2 3809.8 3894.8 4270.8 4398.5 4541.05 4669.4 4754.4 Y -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 Dummy 4970 319.75 4891.35 429.85 TM Technology Inc. reserves the right P. 33 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A tm 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 TE CH V43L V5L GND GND LR16 VDD VDD SC EIO2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 XCK -4398.5 -4270.8 -3894.8 -3809.8 -3621.2 -3531.2 -3446.2 -3356.2 -3084.4 -2994.4 -2722.6 -2632.6 -2360.8 2084 2174 2445.8 2535.8 2807.6 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 -434 LT LB RB Middle T66H0002A -4891.3 5 -4970 -4970 -4874.5 4874.5 4970 -1954.6 5 -1713.7 5 1842.3 429.85 319.75 -340.4 -429.85 -429.85 -340.4 -429.85 -435 -429.85 Appendix TM Technology Inc. reserves the right P. 34 to change products or specifications without notice. Publication Date: JUL. 2002 Revision:A Detail A Scale 5/1 Detail B Scale 5/1 Detail C Scale 2/1 TMT T66 H0 002 A TMT TMT T66 H00 0 T66 H00 02A 2A