TTP224B-BSBN
TTP224B-BSB
4 keys Touch Pad Detector IC
Outline
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The TTP224B-BSBN/TTP224B-BSB TonTouchTM IC is capacitive sensing design specifically
for touch pad controls. The device built in regulator for touch sensor. Stable sensing method
can cover diversity conditions. Human interfaces control panel links through non-conductive
dielectric material. The main application is focused at replacing of the mechanical switch or
button. The ASSP can independently handle the 4 touch pads with 4 direct output pins
Characteristic
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Operating voltage 2.4V ~ 5.5V
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Built-in regulator for touch sensor
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Operating current, @VDD=3V no load
At low power mode typical 2.5uA, At fast mode typical 13uA
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@VDD=3V operating voltage :
The response time about 160mS at low power mode, 60mS at fast mode
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Sensitivity can adjust by the capacitance（1~50pF）outside for each touch pad
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Provides Fast mode and Low Power mode selection by pad option (LPMB pin)
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Provides direct mode or toggle mode、CMOS output or open drain output、
active high or active low by pad option (TOG/OD/AHLB pin)
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Have the maximum on time 16sec/infinite by pad option(MOT0 pin)
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Provides Single-key and Multi-key functions by pad option (SM pin)
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After power-on have about 0.5sec stable-time, during the time do not touch the key pad, and
the function is disabled
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Auto calibration for life
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The re-calibration period is about 1 sec within 8 sec after power-on. When key has been
touched within 8 sec or key has not been touched more than 8 sec after power-on, then the
re-calibration period change to 4 sec
Applications
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Wide consumer products
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Button key replacement
2016/9/1
Page 1 of 9
Version：1.1
TTP224B-BSBN
TTP224B-BSB
Block diagram
TP0
TP1
TP2
TP3
Sensor oscillator
circuit
LPMB
MOT0
Timing counter &
function option
control circuit
Sensor &
Reference
detecting circuit
Output
mode
&
driver
circuit
TPQ0
TPQ1
TPQ2
TPQ3
Touch detecting
circuit
System oscillator
circuit
TOG
AHLB
OD
SM
Key-on & timing
control
Regulator
circuit
Pin Description
Pin NO
Pin Name
Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TP0
TP1
TP2
TP3
AHLB
VDD
TOG
LPMB
MOT0
VSS
OD
SM
TPQ3
TPQ2
TPQ1
TPQ0
I/O
I/O
I/O
I/O
I-PL
P
I-PL
I-PL
I-PH
P
I-PH
I-PH
O
O
O
O
Pad Description
Touch pad input pin
Touch pad input pin
Touch pad input pin
Touch pad input pin
Output active high or low option, default: 0
Positive power supply
Output type option, default: 0
Low power/fast mode option, default: 0
Key maximum on time option, default: 1
Negative power supply, ground
Output open-drain option, default: 1
Single/multi key option, default: 1
Direct output for TP3 touch input pin
Direct output for TP2 touch input pin
Direct output for TP1 touch input pin
Direct output for TP0 touch input pin
Pin Type
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I
CMOS input only
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I-PH
CMOS input and pull-high resister
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O
CMOS push-pull output
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I-PL
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I／O
CMOS
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OD
CMOS input and pull-low resister
Open drain output, have no Diode
protective circuit
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P
Power／Ground
2016/9/1
I／O
Page 2 of 9
Version：1.1
TTP224B-BSBN
TTP224B-BSB
Electrical Characteristics
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Absolute maximum ratings
Parameter
Symbol
Conditions
Rating
Unit
Operating Temperature
TOP
─
-40～+85
℃
Storage Temperature
TSTG
─
-50～+125
℃
Supply Voltage
VDD
Ta=25°C
VSS-0.3～VSS+5.5
V
VIN
Ta=25°C
VSS-0.3～VDD+0.3
V
ESD
─
5
KV
Input Voltage
Human Body Mode
Note：VSS symbolizes for system ground
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DC / AC characteristics：（Test condition at room temperature = 25 ℃）
Parameter
Operating Voltage
Internal Regulator Output
Symbol
VDD
Test Condition
Internal regulator enable
VREG
Min
Typ
2.4
2.2
2.3
Max
Unit
5.5
V
2.4
V
IOPF
VDD=3V, At low power
mode(regulator enable)
VDD=3V, At fast mode
(regulator enable)
Input Ports
VIL
Input Low Voltage
0
0.2
VDD
Input Ports
VIH
Input High Voltage
0.8
1.0
VDD
Output Port Sink Current
IOL
VDD=3V, VOL=0.6V
8
mA
Output Port Source Current
IOH
VDD=3V, VOH=2.4V
-4
mA
Input Pin Pull-high Resistor
RPH
VDD=3V
30K
ohm
Input Pin Pull-low Resistor
RPL
VDD=3V
25K
ohm
TR
VDD=3V、
At fast mode
VDD=3V、
At low power mode
Operating Current
Output Response Time
2016/9/1
IOPL
Page 3 of 9
2.5
uA
13.0
uA
60
mS
160
Version：1.1
TTP224B-BSBN
TTP224B-BSB
Function Description
Ⅰ. Sensitivity adjustment
The total loading of electrode size and capacitance of connecting line on PCB can affect the
sensitivity. So the sensitivity adjustment must according to the practical application on PCB. The
TTP224B-BSBN/TTP224B-BSB offers some methods for adjusting the sensitivity outside
1. by the electrode size
Under other conditions are fixed. Using a larger electrode size can increase sensitivity.
Otherwise it can decrease sensitivity. But the electrode size must use in the effective scope
2. by the panel thickness
Under other conditions are fixed. Using a thinner panel can increase sensitivity. Otherwise it
can decrease sensitivity. But the panel thickness must be below the maximum value
3. by the value of Cs0~Cs3（please see the down figure）
Under other conditions are fixed. Add the capacitors Cs0~Cs3 can fine tune the sensitivity
for single key, that lets all key’s sensitivity identical. When do not use any capacitor to VSS,
the sensitivity is most sensitive. When adding the values of Cs0~Cs3 will reduce sensitivity
in the useful range（1≦Cs0~Cs3≦50pF）
ELECTRODE
VDD
K0
VDD
Cs0
TP0
K1
Cs1
TP1
TPQ0
TPQ1
TPQ2
TPQ3
TP2
K2
Cs2
TP3
Cs3
AHLB
TOG
LPMB
K3
SM
OD
MOT0
VSS
2016/9/1
Page 4 of 9
Version：1.1
TTP224B-BSBN
TTP224B-BSB
Ⅱ. Output mode（By TOG、OD、AHLB pin option）
The TTP224B-BSBN/TTP224B-BSB outputs（TPQ0~TPQ3）has direct mode active high or low
by AHLB pin option, has toggle mode by TOG pin option and has open drain(have diode
protective circuit) mode by OD pin option
Pin
TPQ0 ～ TPQ3 option features
TOG
OD
AHLB
0
1
0
Direct mode, CMOS output active high
0
1
1
Direct mode, CMOS output active low
0
0
0
Direct mode, Open drain output active high
0
0
1
Direct mode, Open drain output active low
1
1
0
Toggle mode, CMOS output, Power on state=0
1
1
1
Toggle mode, CMOS output, Power on state=1
1
0
0
Toggle mode, Power on state high-Z, Active high
1
0
1
Toggle mode, Power on state high-Z, Active low
Remark
Default
Ⅲ. Key operating mode（By SM pin option）
The TTP224B-BSBN/TTP224B-BSB has the Single-key and Multi-key functions by SM pin
option
SM
Option features
Remark
1
Multi-key mode
Default
0
Single key mode
Multi-key mode：The TP0-TP3 can be detected 2 keys or above 2 keys at the same time
Single-key mode：The TP0-TP3 can be detected 1 key only at the same time, when any key be
detected, the other 3 keys can not be detected
2016/9/1
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Version：1.1
TTP224B-BSBN
TTP224B-BSB
Ⅳ. Maximum key on duration time（By MOT0 pin option）
If some objects cover in the sense pad, and causing the change quantity enough to be detected.
To prevent this, the TTP224B-BSBN/TTP224B-BSB sets a timer to monitor the detection. The
timer is the maximum on duration time. When the detection is over the timer, the system will
return to the power-on initial state, and the output becomes inactive until the next detection
MOT0
Option features
1
Infinite（Disable maximum on time）
0
Maximum on time 16 sec
Remark
Default
Ⅴ. Fast and Low power mode select（By LPMB pin option）
The TTP224B-BSBN/TTP224B-BSB has Fast mode and Low Power mode to be selected. It
depends on the state of LPMB pin. When the LPMB pin is connected to VDD, the
TTP224B-BSBN/TTP224B-BSB runs in Fast mode. When the LPMB pin is opened or connected
to VSS, the TTP224B-BSBN/TTP224B-BSB runs in Low Power mode.
In the Fast mode response time is faster, but the current consumption will be increased. In the
Low Power mode it will be saving power, but will be slowing response time for first touch. When
it awaked in fast mode, the response time is the same the fast mode. In this mode when
detecting key touch, it will switch to Fast mode. Until the key touch is released and will keep a
time about 8sec. Then it returns to Low Power mode.
The states and timing of two modes please see below figure.
Low Power Mode timing diagram:
Fast Mode timing diagram:
2016/9/1
LPMB
Option features
1
Fast mode
0
Low Power mode
Page 6 of 9
Remark
Default
Version：1.1
TTP224B-BSBN
TTP224B-BSB
Application circuit
K0
Cs0
K1
Cs1
K2
TPQ0 16
2 TP1
TPQ1 15
3 TP2
TPQ2 14
4 TP3
TPQ3 13
6 VDD
OD 11
7 TOG
VSS 10
8 LPMB
Cs3
SM 12
5 AHLB
Cs2
K3
1 TP0
MOT0 9
104
C1
Option table:
Key operation mode:
Output Mode:
TOG
OD
AHLB
Pad TPQ0~TP3 option features
SM
Option features
OPEN
OPEN
OPEN
Direct mode, CMOS active high output
OPEN
Multi-key mode
OPEN
OPEN
VDD
Direct mode, CMOS active low output
VSS
Single key mode
OPEN
VSS
OPEN
Direct mode, Open drain active high output
OPEN
VSS
VDD
Direct mode, Open drain active low output
VDD
OPEN
OPEN
Toggle mode, CMOS output, Power on state =0
VDD
OPEN
VDD
Toggle mode, CMOS output, Power on state =1
VDD
VSS
OPEN
Toggle mode, Power on state high-Z, Active high
VDD
VSS
VDD
Toggle mode, Power on state high-Z, Active low
Maximum key on duration time:
MOT0
Option features
VSS
Maximum on time 16sec
OPEN
Infinite(Disable maximum on time)
Fast and Low power mode:
LPMB
Option features
VDD
Fast mode
OPEN
Low Power mode
P.S.：
1. On PCB, the length of lines from touch pad to IC pin shorter is better.
And the lines do not parallel and cross with other lines.
2. The power supply must be stable. If the supply voltage drift or shift quickly, maybe causing
sensitivity anomalies or false detections.
3. The material of panel covering on the PCB can not include the metal or the electric element.
The paints on the surfaces are the same.
4. The C1 capacitor must be used between VDD and VSS; and should be routed with very short
tracks to the device’s VDD and VSS pins (TTP224B-BSBN/TTP224B-BSB).
5. The capacitance Cs0~Cs3 can be used to adjust the sensitivity. The value of Cs0~Cs3 use
smaller, then the sensitivity will be better. The sensitivity adjustment must according to the
practical application on PCB. The range of Cs0~Cs3 value are 1~50pF.
6. The sensitivity adjustment capacitors（Cs0~Cs3）must use smaller temperature coefficient and
more stable capacitors. Such are X7R, NPO for example. So for touch application, recommend to
use NPO capacitor, for reducing that the temperature varies to affect sensitivity.
2016/9/1
Page 7 of 9
Version：1.1
TTP224B-BSBN
TTP224B-BSB
Package outline
Package Type: SSOP-16
2016/9/1
Page 8 of 9
Version：1.1
TTP224B-BSBN
TTP224B-BSB
Package configuration
TTP224B-BSBN/TTP224B-BSB
TP0
TP1
TP2
TP3
AHLB
VDD
TOG
LPMB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TPQ0
TPQ1
TPQ2
TPQ3
SM
OD
VSS
MOT0
Package Type SSOP-16
Ordering Information
TTP224B-BSBN / TTP224B-BSB
Package Type
Chip Type
Wafer Type
No support
No support
TTP224B-BSBN
TTP224B-BSB
REVISION HISTORY
1. 2015/07/24
- Initial version：V1.0
2. 2016/09/01 => V_1.1
- Add the TTP224B-BSB
2016/9/1
Page 9 of 9
Version：1.1
