XC6108C21CGR-G

XC6108 series is Not Recommended for New Designs. XC6108 Series ETR0205_010b Voltage Detector with Separated Sense Pin & Delay Capacitor Pin ■GENERAL DESCRIPTION The XC6108 series is highly precise, low power consumption voltage detector, manufactured using CMOS and laser trimming technologies. Since the sense pin is separated from power supply, it allows the IC to monitor added power supply. Using the IC with the sense pin separated from power supply enables output to maintain the state of detection even when voltage of the monitored power supply drops to 0V. Moreover, with the built-in delay circuit, connecting the delay capacitance pin to the capacitor enables the IC to provide an arbitrary release delay time. Both CMOS and N-channel open drain output configurations are available. ■APPLICATIONS ■FEATURES ●Microprocessor reset circuitry Highly Accurate : +2% (Detect Voltage≧1.5V) +30mV (Detect Voltage＜1.5V) ●Charge voltage monitors Low Power Consumption ●Memory battery back-up switch circuits : 0.6 μA TYP. (detect, VIN= 1.0V ) 0.8 μA TYP. (release, VIN= 1.0V ) ●Power failure detection circuits : 0.8V ~ 5.0V in 0.1V increments Detect Voltage Range Operating Voltage Range : 1.0V ~ 6.0V Temperature Stability : ±100ppm/ ℃ TYP. Output Configuration : CMOS or N-channel open drain Operating Temperature : -40 ℃ ~ +85 ℃ Separated Sense Pin : VSEN Pin Available Built-In Delay Circuit : Delay Time Adjustable Packages : USP-4, SOT-25 Environmentally Friendly : EU RoHS Compliant, Pb Free ■TYPICAL APPLICATION CIRCUIT ■TYPICAL PERFORMANCE CHARACTERISTICS ●Output Voltage vs. Sense Voltage XC6108C25A GR (No Pull-Up resistor needed for 7.0 CMOS output product) 6.0 Output Voltage: VOUT (V) Output Voltage: VOUT (V) Monitering Power supply Ta=25℃ V IN=6.0V 5.0 4.0 4.0V 3.0 2.0 1.0 1.0V 0.0 -1.0 0 1 2 3 4 5 6 Sense oltage: VVSEN (V) SenseVVoltage: SEN (V) 1/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■PIN CONFIGURATION 5 4 Cd VSEN VOUT VSS USP-4 (BOTTOM VIEW) 1 * In the XC6108xxxA/B series, the dissipation pad should not be short-circuited with other pins. * In the XC6108xxxC/D series, when the dissipation pad is short-circuited with other pins, connect it to the NC pin (No.2) pin before use. VIN 2 3 SOT-25 (TOP VIEW) ■PIN ASSIGNMENT PIN NUMBER PIN NAME FUNCTION USP- 4 SOT-25 1 1 VOUT Output (Detect ”L”) 2 5 Cd Delay Capacitance (*1) 2 - NC No Connection 3 4 VSEN Sense 4 3 VIN Input 5 2 VSS Ground (*2) NOTE: *1: With the VSS pin of the USP-4 package, a tab on the backside is used as the pin No.5. *2: In the case of selecting no built-in delay capacitance pin type, the delay capacitance (Cd) pin will be used as the N.C. ■PRODUCT CLASSIFICATION ●Ordering Information XC6108 ①②③④⑤⑥-⑦(*1) DESIGNATOR DESCRIPTION ① Output Configuration ②③ Detect Voltage ④ Output Delay & Hysteresis (Options) SYMBOL C CMOS output N N-ch open drain output 08 ~ 50 Built-in delay capacitance pin, hysteresis 5% (TYP.)(Standard*) B Built-in delay capacitance pin, hysteresis less than 1%(Standard*) No built-in delay capacitance pin, hysteresis 5% (TYP.) (Semi-custom) No built-in delay capacitance pin, hysteresis less than 1% (Semi-custom) USP-4 C GR Packages Taping Type (*2) e.g. 18→1.8V A D ⑤⑥-⑦ DESCRIPTION GR-G USP-4 MR SOT-25 MR-G SOT-25 *When delay function isn’t used, open the delay capacitance pin before use. (*1) (*2) The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant. The device orientation is fixed in its embossed tape pocket. For reverse orientation, please contact your local Torex sales office or representative. (Standard orientation: ⑤R-⑦, Reverse orientation: ⑤L-⑦) 2/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■BLOCK DIAGRAMS (1) XC6108CxxA *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6108CxxC (semi-custom). (2) XC6108CxxB *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6108CxxD (semi-custom). (3) XC6108NxxA *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6108NxxC (semi-custom). (4) XC6108NxxB *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6108NxxD (semi-custom). 3/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■ABSOLUTE MAXIMUM RATINGS ●XC6108xxxA/B Ta = 25OC PARAMETER SYMBOL Input Voltage Output Current Output Voltage XC6108C (*1) XC6108N (*2) RATINGS VIN VSS－0.3 ~ 7.0 V IOUT 10 mA VOUT VSS－0.3 ~ VIN＋0.3 VSS－0.3 ~ 7.0 V Sense Pin Voltage VSEN VSS－0.3 ~ 7.0 V Delay Capacitance Pin Voltage VCD VSS－0.3 ~ VIN＋0.3 V Delay Capacitance Pin Current ICD 5.0 mA USP-4 Power Dissipation Pd SOT-25 120 250 mW Operating Temperature Range Ta －40 ~＋85 ℃ Storage Temperature Range Tstg －55 ~＋125 ℃ ●XC6108xxxC/D Ta = 25OC PARAMETER SYMBOL Input Voltage Output Current Output Voltage XC6108C (*1) XC6108N (*2) Sense Pin Voltage Power Dissipation SOT-25 UNITS VIN VSS－0.3 ~ 7.0 V IOUT 10 mA VOUT VSEN USP-4 RATINGS Pd VSS－0.3 ~ VIN＋0.3 VSS－0.3 ~ 7.0 VSS－0.3 ~ 7.0 120 250 V V mW Operating Temperature Range Ta －40 ~＋85 ℃ Storage Temperature Range Tstg －55 ~＋125 ℃ NOTE: *1: CMOS output *2: N-ch open drain output 4/22 UNITS XC6108 XC6108 series is Not Recommended for New Designs. Series ■ELECTRICAL CHARACTERISTICS ●XC6108xxxA PARAMETER Ta=25℃ SYMBOL Operating Voltage CONDITIONS VIN VDF(T) = 0.8 ~ 5.0V (*1) MIN. TYP. MAX. UNITS CIRCUITS 1.0 - 6.0 V - Detect Voltage VDF VIN = 1.0 ~ 6.0V E-1 V ① Hysteresis Width VHYS VIN = 1.0 ~ 6.0V E-2 V ① Detect Voltage Line Regulation ΔVDF / (ΔVIN・VDF) VIN = 1.0 ~ 6.0V %/V ① Supply Current 1 (*2) ISS1 VSEN = VDF x 0.9 μA ② Supply Current 2 (*2) ISS2 VSEN = VDF x 1.1 μA ② mA ③ mA ④ μA ③ ppm/ ℃ ① M ⑤ IOUT1 VSEN =0V VDS = 0.5V (N-ch) IOUT2 VSEN = 6.0V VDS = 0.5V (P-ch) Output Current (*3) Leakage Current CMOS Output Nch Open Drain Output ILEAK - ±0.1 - VIN = 1.0V - 0.6 1.5 VIN = 6.0V - 0.7 1.6 VIN = 1.0V - 0.8 1.7 VIN = 6.0V - 0.9 1.8 VIN = 1.0V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VIN = 6.0V 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 - VIN = 1.0V - -0.30 -0.08 VIN = 6.0V - -2.00 -0.70 0.20 - 0.20 0.40 ±100 - VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open - -40 ℃ ≦ Ta ≦ 85℃ - Temperature Characteristics ΔVDF / (ΔTopr･VDF) Sense Resistance (*4) RSEN VSEN = 5.0V, VIN = 0V Rdelay VSEN = 6.0V, VIN = 5.0V, Cd = 0V 1.6 2.0 2.4 M ⑥ ICD VDS = 0.5V, VIN = 1.0V - 200 - μA ⑥ VSEN = 6.0V, VIN = 1.0V 0.4 0.5 0.6 VSEN = 6.0V, VIN = 6.0V 2.9 3.0 3.1 V ⑦ VIN = VSEN = 0V ~ 1.0V - 0.3 0.4 V ⑧ 30 230 μs ⑨ 30 200 μs ⑨ Delay Resistance (*5) Delay capacitance pin Sink Current Delay Capacitance Pin Threshold Voltage VTCD Unspecified Operating Voltage (*6) VUNS Detect Delay Time (*7) tDF0 Release Delay Time (*8) tDR0 VIN = 6.0V, VSEN = 6.0V→ 0.0V Cd: Open VIN = 6.0V, VSEN = 0.0V→ 6.0V Cd: Open E-4 NOTE: *1: VDF(T): Nominal detect voltage *2: Current flows the sense resistor is not included. *3: The Pch values are applied only to the XC6108C series (CMOS output). *4: Calculated from the voltage value and the current value of the VSEN. *5: Calculated from the voltage value of the VIN and the current value of the Cd. *6: The maximum voltage of the VOUT in the range of the VIN 0V to 1.0V when the VIN and the VSEN are short-circuited This value is applied only to the XC6108C series (CMOS output). *7: Time which ranges from the state of VSEN=VDF to the VOUT reaching 0.6V when the VSEN falls without connecting to the Cd pin. *8: Time which ranges from the state of VIN= VDF +VHYS to the VOUT reaching 5.4V when the VSEN rises without connecting to the Cd pin. 5/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■ELECTRICAL CHARACTERISTICS (Continued) ●XC6108xxxB Ta=25℃ PARAMETER SYMBOL CONDITIONS (*1) MIN. TYP. MAX. UNITS CIRCUITS 1.0 - 6.0 V - Operating Voltage VIN VDF(T) = 0.8 ~ 5.0V Detect Voltage VDF VIN = 1.0 ~ 6.0V E-1 V ① Hysteresis Width VHYS VIN = 1.0 ~ 6.0V E-3 V ① Detect Voltage Line Regulation ΔVDF / (ΔVIN･VDF) VIN = 1.0 ~ 6.0V %/V ① Supply Current 1 (*2) ISS1 VSEN = VDF x 0.9 μA ② Supply Current 2 (*2) ISS2 VSEN = VDF x 1.1 μA ② mA ③ mA ④ μA ③ ppm/ ℃ ① M ⑤ IOUT1 VSEN =0V VDS = 0.5V (N-ch) IOUT2 VSEN = 6.0V VDS = 0.5V (P-ch) Output Current (*3) Leakage Current CMOS Output Nch Open Drain Output ILEAK - ±0.1 - VIN = 1.0V - 0.6 1.5 VIN = 6.0V - 0.7 1.6 VIN = 1.0V - 0.8 1.7 VIN = 6.0V - 0.9 1.8 VIN = 1.0V 0.1 0.7 - VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VIN = 6.0V 0.8 1.2 1.6 1.8 1.9 1.6 2.0 2.3 2.4 2.5 - VIN = 1.0V - -0.30 -0.08 VIN = 6.0V - -2.00 -0.70 0.20 - 0.20 0.40 ±100 - VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open - - Temperature Characteristics ΔVDF / (ΔTopr･VDF) -40 ℃ ≦ Ta ≦ 85℃ Sense Resistance (*4) RSEN VSEN = 5.0V, VIN = 0V Rdelay VSEN = 6.0V, VIN = 5.0V, Cd = 0V 1.6 2.0 2.4 M ⑥ ICD VDS = 0.5V, VIN = 1.0V - 200 - μA ⑥ VSEN = 6.0V, VIN = 1.0V 0.4 0.5 0.6 VSEN = 6.0V, VIN = 6.0V 2.9 3.0 3.1 V ⑦ VIN = VSEN = 0V ~ 1.0V - 0.3 0.4 V ⑧ 30 230 μs ⑨ 30 200 μs ⑨ Delay Resistance (*5) Delay capacitance pin Sink Current Delay Capacitance Pin Threshold Voltage VTCD Unspecified Operating Voltage (*6) VUNS Detect Delay Time (*7) tDF0 Release Delay Time (*8) tDR0 VIN = 6.0V, VSEN = 6.0V→ 0.0V Cd: Open VIN = 6.0V, VSEN = 0.0V→ 6.0V Cd: Open E-4 NOTE: *1: VDF(T): Nominal detect voltage *2: Current flows the sense resistor is not included. *3: The Pch values are applied only to the XC6108C series (CMOS output). *4: Calculated from the voltage value and the current value of the VSEN. *5: Calculated from the voltage value of the VIN and the current value of the Cd. *6: The maximum voltage of the VOUT in the range of the VIN 0V to 1.0V when the VIN and the VSEN are short-circuited This value is applied only to the XC6108C series (CMOS output). *7: Time which ranges from the state of VSEN=VDF to the VOUT reaching 0.6V when the VSEN falls without connecting to the Cd pin. *8: Time which ranges from the state of VIN= VDF +VHYS to the VOUT reaching 5.4V when the VSEN rises without connecting to the Cd pin. 6/22 XC6108 XC6108 series is Not Recommended for New Designs. Series ■ELECTRICAL CHARACTERISTICS (Continued) ●XC6108xxxC Ta=25℃ PARAMETER SYMBOL CONDITIONS (*1) MIN. TYP. MAX. UNITS CIRCUITS 1.0 - 6.0 V - Operating Voltage VIN VDF(T) = 0.8 ~ 5.0V Detect Voltage VDF VIN = 1.0 ~ 6.0V E-1 V ① Hysteresis Width VHYS VIN = 1.0 ~ 6.0V E-2 V ① Detect Voltage Line Regulation ΔVDF / (ΔVIN･VDF) VIN = 1.0 ~ 6.0V %/V ① Supply Current 1 (*2) ISS1 VSEN = VDF x 0.9 μA ② Supply Current 2 (*2) ISS2 VSEN = VDF x 1.1 μA ② mA ③ mA ④ μA ③ ppm/ ℃ ① M ⑤ IOUT1 VSEN =0V VDS = 0.5V (N-ch) IOUT2 VSEN = 6.0V VDS = 0.5V (P-ch) Output Current (*3) Leakage Current CMOS Output Nch Open Drain Output ILEAK - 0.6 1.5 - 0.7 1.6 VIN = 1.0V - 0.8 1.7 VIN = 6.0V - 0.9 1.8 VIN = 1.0V 0.1 0.7 VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VIN = 6.0V 0.8 1.2 1.6 1.8 1.9 1.6 2.0 2.3 2.4 2.5 VIN = 1.0V - -0.30 VIN = 6.0V - VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open - - -40 ℃ ≦ Ta ≦ 85℃ Sense Resistance (*4) RSEN VSEN = 5.0V, VIN = 0V VUNS VIN = VSEN = 0V ~ 1.0V tDF0 tDR0 Release Delay Time - VIN = 1.0V ΔVDF/ (ΔTopr･VDF) (*7) ±0.1 VIN = 6.0V Temperature Characteristics Unspecified Operating Voltage (*5) Detect Delay Time (*6) - - -0.08 -2.00 -0.70 0.20 - 0.20 0.40 ±100 - E-4 - 0.3 0.4 V ⑦ VIN = 6.0V, VSEN = 6.0V→ 0.0V 30 230 μs ⑨ VIN = 6.0V, VSEN = 0.0V→ 6.0V 30 200 μs ⑨ NOTE: *1: VDF(T): Nominal detect voltage *2: Current flows the sense resistor is not included. *3: The Pch values are applied only to the XC6108C series (CMOS output). *4: Calculated from the voltage value and the current value of the VSEN. *5: The maximum voltage of the VOUT in the range of the VIN 0V to 1.0V when the VIN and the VSEN are short-circuited This value is applied only to the XC6108C series (CMOS output). *6: Time which ranges from the state of VSEN=VDF to the VOUT reaching 0.6V when the VSEN falls. *7: Time which ranges from the state of VIN= VDF +VHYS to the VOUT reaching 5.4V when the VSEN rises. 7/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■ELECTRICAL CHARACTERISTICS (Continued) ●XC6108xxxD Ta=25℃ PARAMETER SYMBOL Operating Voltage CONDITIONS VIN VDF(T) = 0.8 ~ 5.0V (*1) MIN. TYP. MAX. UNITS CIRCUITS 1.0 - 6.0 V - Detect Voltage VDF VIN = 1.0 ~ 6.0V E-1 V 1 Hysteresis Width VHYS1 VIN = 1.0 ~ 6.0V E-3 V 1 Detect Voltage Line Regulation ΔVDF / (ΔVIN･VDF) VIN = 1.0 ~ 6.0V %/V 1 Supply Current 1 (*2) ISS1 VSEN = VDF x 0.9 μA 2 Supply Current 2 (*2) ISS2 VSEN = VDF x 1.1 μA 2 mA 3 mA 4 μA 3 ppm/ ℃ 1 M 5 IOUT1 VSEN =0V VDS = 0.5V (N-ch) IOUT2 VSEN = 6.0V VDS = 0.5V (P-ch) Output Current (*3) Leakage Current CMOS Output Nch Open Drain Output ILEAK - ±0.1 - VIN = 1.0V - 0.6 1.5 VIN = 6.0V - 0.7 1.6 VIN = 1.0V - 0.8 1.7 VIN = 6.0V - 0.9 1.8 VIN = 1.0V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VIN = 6.0V 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 - VIN = 1.0V - -0.30 -0.08 VIN = 6.0V VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open - - Temperature Characteristics ΔVDF / (ΔTopr･VDF) -40 ℃ ≦ Ta ≦ 85℃ Sense Resistance (*4) RSEN VSEN = 5.0V, VIN = 0V VUNS VIN = VSEN = 0V ~ 1.0V tDF0 tDR0 Unspecified Operating Voltage (*5) Detect Delay Time (*6) Release Delay Time (*7) - -2.00 -0.70 0.20 - 0.20 0.40 ±100 - E-4 - 0.3 0.4 V 7 VIN = 6.0V, VSEN = 6.0V→ 0.0V 30 230 μs 9 VIN = 6.0V, VSEN = 0.0V→ 6.0V 30 200 μs 9 NOTE: *1: VDF(T): Nominal detect voltage *2: Current flows the sense resistor is not included. *3: The Pch values are applied only to the XC6108C series (CMOS output). *4: Calculated from the voltage value and the current value of the VSEN. *5: The maximum voltage of the VOUT in the range of the VIN 0V to 1.0V when the VIN and the VSEN are short-circuited This value is applied only to the XC6108C series (CMOS output). *6: Time which ranges from the state of VSEN=VDF to the VOUT reaching 0.6V when the VSEN falls. *7: Time which ranges from the state of VIN= VDF +VHYS to the VOUT reaching 5.4V when the VSEN rises. 8/22 XC6108 XC6108 series is Not Recommended for New Designs. Series ■VOLTAGE CHART SYMBOL NOMINAL DETECT VOLTAGE VDF(T) (V) 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 E-1 DETECT VOLTAGE (V) (*1) VDF MIN. 0.770 0.870 0.970 1.070 1.170 1.270 1.370 1.470 1.568 1.666 1.764 1.862 1.960 2.058 2.156 2.254 2.352 2.450 2.548 2.646 2.744 2.842 2.940 3.038 3.136 3.234 3.332 3.430 3.528 3.626 3.724 3.822 3.920 4.018 4.116 4.214 4.312 4.410 4.508 4.606 4.704 4.802 4.900 MAX. 0.830 0.930 1.030 1.130 1.230 1.330 1.430 1.530 1.632 1.734 1.836 1.938 2.040 2.142 2.244 2.346 2.448 2.550 2.652 2.754 2.856 2.958 3.060 3.162 3.264 3.366 3.468 3.570 3.672 3.774 3.876 3.978 4.080 4.182 4.284 4.386 4.488 4.590 4.692 4.794 4.896 4.998 5.100 E-2 HYSTERESIS RANGE (V) VHYS MIN. MAX. 0.015 0.066 0.017 0.074 0.019 0.082 0.021 0.090 0.023 0.098 0.025 0.106 0.027 0.114 0.029 0.122 0.031 0.131 0.033 0.085 0.035 0.147 0.037 0.155 0.039 0.163 0.041 0.171 0.043 0.180 0.045 0.188 0.047 0.196 0.049 0.204 0.051 0.212 0.053 0.220 0.055 0.228 0.057 0.237 0.059 0.245 0.061 0.253 0.063 0.261 0.065 0.269 0.067 0.277 0.069 0.286 0.071 0.294 0.073 0.302 0.074 0.310 0.076 0.318 0.078 0.326 0.080 0.335 0.082 0.343 0.084 0.351 0.086 0.359 0.088 0.367 0.090 0.375 0.092 0.384 0.094 0.392 0.096 0.400 0.098 0.408 E-3 HYSTERESIS RANGE (V) VHYS MIN. MAX. 0.008 0.009 0.010 0.011 0.012 0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.020 0.021 0.022 0.023 0.024 0.026 0.027 0.028 0.029 0 0.030 0.031 0.032 0.033 0.034 0.035 0.036 0.037 0.038 0.039 0.040 0.041 0.042 0.043 0.044 0.045 0.046 0.047 0.048 0.049 0.050 0.051 E-4 SENSE RESISTANCE (MΩ) RSEN MIN. TYP. 10 20 13 24 15 28 NOTE: *1: When VDF(T)≦1.4V, the detection accuracy is ±30mV. When VDF(T)≧1.5V, the detection accuracy is ±2%. 9/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■TEST CIRCUITS Circuit 1 R=100kΩ (No resistor needed for CMOS output products) XC6108 Series Circuit 2 XC6108 Series Circuit 3 XC6108 Series Circuit 4 XC6108 Series Circuit 5 XC6108 Series 10/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■TEST CIRCUITS (Continued) Circuit 6 XC6108 Series Circuit 7 (No resistor needed for CMOS output products) XC6108 Series Circuit 8 XC6108 Series Circuit 9 (No resistor needed for CMOS output products) Waveform Measurement Point XC6108 Series *No delay capacitance pin available in the XC6108xxxC/D series. 11/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■OPERATIONAL EXPLANATION A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on page 14. ① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged to the power supply input voltage, (VIN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to reach the detect voltage (VDF) (VSEN>VDF), the output voltage (VOUT) keeps the “High” level (=VIN). * If a pull-up resistor of the XC6108N series (N-ch open drain) is connected to added power supply different from the input voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected. ② When the sense pin voltage keeps dropping and becomes equal to the detect voltage (VSEN =VDF), an N-ch transistor (M1) for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An inverter (Inv.1) operates as a comparator of the reference voltage VIN, and the output voltage changes into the “Low” level (=VSS). The detect delay time [tDF] is defined as time which ranges from VSEN=VDF to the VOUT of “Low” level (especially, when the Cd pin is not connected: tDF0). ③ While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground voltage (=VSS) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to reach the release voltage (VSEN< VDF +VHYS). ④ When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor (M1) for the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay resistor (Rdelay). The inverter (Inv.1) will operate as a comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic Threshold: VTHL=VSS) while the sense pin voltage keeps higher than the detect voltage (VSEN > VDF). ⑤ While the delay capacitance pin voltage (VCD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC series circuit. Assuming the time to the release delay time (tDR), it can be given by the formula (1). tDR = －Rdelay×Cd×In (1－VTCD / VIN) …(1) * In = a natural logarithm The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and the delay capacitance pin voltage is VIN /2 (TYP.) tDR = Rdelay×Cd×0.69…(2) ＊：Rdelay is 2.0MΩ（TYP.） As an example, presuming that the delay capacitance is 0.68μF, tDR is : 2.0×106×0.68×10-6×0.69=938(ms) * Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the ground (=VSS) level because time described in ③ is short. ⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (VCD=VTCD), the inverter (Inv.1) will be inverted. As a result, the output voltage changes into the “High” (=VIN) level. tDR0 is defined as time which ranges from VSEN=VDF+VHYS to the VOUT of “High” level without connecting to the Cd. ⑦ While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the delay capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=VIN) level. 12/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■OPERATIONAL EXPLANATION (Continued) ●Function Chart VSEN Cd L H L H L H L H L H TRANSITION OF VOUT CONDITION *1 ① ② L ⇒ L ⇒ L H L H ⇒ ⇒ H *1: VOUT transits from condition ① to ② because of the combination of VSEN and Cd. ●Example ex. 1) VOUT ranges from ‘L’ to ‘H’ in case of VSEN = ‘H’ (VDR≧VSEN), Cd=’H’ (VTCD≧Cd) while VOUT is ‘L’. ex. 2) VOUT maintains ‘H’ when Cd ranges from ‘H’ to ‘L’, VSEN=’H’ and Cd=’L’ when VOUT becomes ‘H’ in ex.1. ●Release Delay Time Chart DELAY CAPACITANCE [Cd] (μF) 0.010 0.022 0.047 0.100 0.220 0.470 1.000 RELEASE DELAY TIME [tDR] (TYP.) (ms) 13.8 30.4 64.9 138 304 649 1380 RELEASE DELAY TIME [tDR] *2 (MIN. ~ MAX.) (ms) 11.0 ~ 16.6 24.3 ~ 36.4 51.9 ~ 77.8 110 ~ 166 243~ 364 519 ~ 778 1100 ~ 1660 * The release delay time values above are calculated by using the formula (2). *2: The release delay time (tDR) is influenced by the delay capacitance Cd. 13/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■OPERATIONAL EXPLANATION (Continued) Figure 1: Typical application circuit example *The XC6108N series (N-ch open drain output) requires a pull-up resistor for pulling up output. VIN M2 VSEN M4 ＲＳEN=R1+R2+R3 Rdelay Comparator Inverter VOUT R1 VIN VSEN R2 R3 M3 Vref M5 M1 VSS Cd Cd Figure 2: The timing chart of Figure 1 VSEN (MIN.:0V, MAX.:6.0V) VDF+VHYS VDF VCD(MIN.:VSS, MAX.:VIN) VTCD VOUT (MIN.:VSS, MAX:VIN) 14/22 XC6108 XC6108 series is Not Recommended for New Designs. Series ■NOTES ON USE 1. Use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage to the device. 2. The power supply input pin voltage drops by the resistance between power supply and the VIN pin, and by through current at operation of the IC. At this time, the operation may be wrong if the power supply input pin voltage falls below the minimum operating voltage range. In CMOS output, for output current, drops in the power supply input pin voltage similarly occur. Moreover, in CMOS output, when the VIN pin and the sense pin are short-circuited and used, oscillation of the circuit may occur if the drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis voltage. Note it especially when you use the IC with the VIN pin connected to a resistor. 3. When the setting voltage is less than 1.0V, be sure to separate the VIN pin and the sense pin, and to apply the voltage over 1.0V to the VIN pin. 4. Note that a rapid and high fluctuation of the power supply input pin voltage may cause a wrong operation. 5. Power supply noise may cause operational function errors, Care must be taken to put the capacitor between VIN-GND and test on the board carefully. 6. When there is a possibility of which the power supply input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operation with the delay capacitance pin (Cd) connected to a capacitor, use a schottky barrier diode connected between the VIN pin and the Cd pin as the Figure 3 shown below. 6. In N channel open drain output, VOUT voltage at detect and release is determined by resistance of a pull up resistor connected at the VOUT pin. Please choose proper resistance values with reffering to Figure 4; During detection : VOUT = Vpull / (1+Rpull / RON) Vpull: Pull up voltage RON(※1)：On resistance of N channel driver M3 can be calculated as VDS / IOUT1 from electrical characteristics, For example, when (※2) RON = 0.5 / 0.8×10-3 = 625Ω（MIN.）at VIN=2.0V, Vpull = 3.0V and VOUT ≦0.1V at detect, Rpull= (Vpull /VOUT-1)×RON= (3 / 0.1-1)×625≒18ｋΩ In this case, Rpull should be selected higher or equal to 18kΩ in order to keep the output voltage less than 0.1V during detection. (※1) RON is bigger when VIN is smaller, be noted. (※2) For calculation, Minimum VIN should be chosen among the input voltage range. During releasing：VOUT = Vpull / (1 + Rpull / Roff) Vpull：Pull up voltage Roff：On resistance of N channel driver M3 is 15MΩ（MIN.） when the driver is off (as to VOUT / ILEAK) For example：when Vpull = 6.0V and VOUT ≧ 5.99V, Rpull = (Vpull / VOUT-1)×Roff = (6/5.99-1)×15×106 ≒25kΩ In this case, Rpull should be selected smaller or equal to 25kΩ in order to obtain output voltage higher than 5.99V during releasing. Figure 3: Circuit example with the delay capacitance pin (Cd) connected to a schottky barrier diode Figure 4: Circuit example of XC6108N Series Vpull VIN M2 R=100kΩ VIN (No resistor needed for CMOS output products) VSEN VIN VOUT VSEN VSEN Rpull Rdelay Comparator Inverter ILEA K R1 VOUT VIN VSEN VOUT M3 R2 Cd Cd ＲＳEN=R1+R2+R3 Vref VSS R3 M5 M1 VSS Cd NOTE： Roff=VOUT/ILEAK Figure 3 Figure 4 15/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (1) Supply Current vs. Sense Voltage XC6108C25A GR VIN=3.0V Supply Current : ISS (μA) Supply Current: ISS (μA) 2.0 Ta=85℃ 1.5 25℃ 1.0 0.5 -40℃ 0.0 0 1 2 3 4 5 VSEN (V)) Sense Voltage V oltage:: V SEN (V 6 (2) Supply Current vs. Input Voltage XC6108C25AGR XC6108C25AGR 1.2 1.0 1.0 Supply Current : ISS (μA) Supply Current: ISS (μA) Supply Current : ISSISS (μA) Supply Current: (μA) VSEN =2.25V 1.2 Ta=85℃ 0.8 25℃ 0.6 0.4 -40℃ 0.2 VSEN =2.75V Ta=85℃ 0.8 0.6 25℃ 0.4 -40℃ 0.2 0.0 0.0 0 1 2 3 4 5 InputVoltage Voltage: VIN(V) (V) Input : VIN 0 6 1 2 3 4 5 6 Input Voltage Voltage:: VIN VIN(V) (V) (3) Detect Voltage vs. Ambient Temperature (4) Detect Voltage vs. Input Voltage XC6108C25AGR XC6108C25AGR VIN=4.0V 2.55 2.55 Detect Voltage : VDF (V) Detect Voltage: VDF (V) Detect Voltage : VDF (V) Detect Voltage: VDF (V) Ta=25℃ 2.50 2.45 2.50 -40℃ 2.45 -50 16/22 85℃ -25 0 25 50 75 AAmbient mbient Temperature: Temperature :Ta Ta( (℃) ℃) 100 1.0 2.0 3.0 4.0 5.0 Input Voltage: VIN (V) Input Voltage : VIN (V) 6.0 XC6108 XC6108 series is Not Recommended for New Designs. Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (5) Hysteresis Voltage vs. Ambient Temperature (6) CD Pin Sink Current vs. Input Voltage XC6108C25AGR XC6108C25AGR VSEN =0V, VDS=0.5V 3.0 Cd PIN Sink Current : ICD (mA) Cd PIN Sink Current: ICD (mA) Hysteresis Voltage : VHYS (V) Hysteresis Voltage: VHYS (V) VIN=4.0V 0.20 0.15 0.10 0.05 -50 -25 0 25 50 75 Ambient A mbientTemperature Temperature:: Ta Ta(℃) (℃) 2.5 Ta=-40℃ 2.0 25℃ 1.5 1.0 85℃ 0.5 0.0 100 (7) Output Voltage vs. Sense Voltage 0 1 6 (8) Output Voltage vs. Input Voltage XC6108C25A GR XC6108N25AGR V SEN=V IN Pull-up=V IN R=100kΩ Ta=25℃ 7.0 4.0 Output Voltage : VOUT (V) Output Voltage: VOUT (V) 6.0 Output Voltage : VOUT (V) Output Voltage: VOUT (V) 2 3 4 5 Input InputVoltage: Voltage : VIN VIN (V) (V) V IN=6.0V 5.0 4.0 4.0V 3.0 2.0 1.0 1.0V 0.0 -1.0 0 1 2 3 4 5 3.0 Ta=85℃ 2.0 25℃ 1.0 -40℃ 0.0 -1.0 0 6 0.5 1 1.5 2 2.5 Input Voltage : VIN (V) Supply Voltage: VIN SEN (V) Sense oltage: :VVSEN SenseVVoltage (V) 3 (V) (9) Output Current vs. Input Voltage XC6108C25AGR VD S(N ch)=0.5V 4.0 3.5 Ta=-40℃ 3.0 25℃ 2.5 2.0 1.5 85℃ 1.0 VD S(Pch)=0.5V 0.0 Output Current: IOUT(mA) (mA) Output Current : IOUT Output OutputCurrent Current:: IOUT IOUT(mA) (mA) XC6108C25AGR 0.5 0.0 -0.5 Ta=85℃ -1.0 25℃ -1.5 -40℃ -2.0 0 1 2 3 4 5 Input Voltage Voltage:: VIN VIN (V) (V) Input 6 0 1 2 3 4 5 Input Voltage: VIN (V) Input Voltage : VIN (V) 6 17/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (10) Delay Resistance vs. Ambient Temperature (11) Release Delay Time vs. Delay Capacitance XC6108C25AGR XC6108C25AGR Release Time : TDR (ms) ReleaseDelay Delay time: TDR (ms) Delay Resistance: Rdelay Delay Resistance : Rdelay (MΩ) (MΩ) V SEN=6.0V V CD=0.0V V IN=5.0V 4 3.5 3 2.5 2 1.5 1 -50 -25 0 25 50 75 Ta=25℃ 10000 VIN=1.0V 3.0V 6.0V 1000 100 10 1 TDR=Cd×2.0×10 6 ×0.69 0.1 0.0001 100 0.001 0.01 0.1 1 Delay Capacitor: :Cd Delay Capacitance Cd (μF) (μF) Ambient Temperature : Ta (℃) Ambient Temperature: Ta (℃ ) (12) Detect Delay Time vs. Delay Capacitance (13) Leakage Current vs. Ambient Temperature XC6108C25AGR XC6108N25AGR Ta=25℃ V IN=6.0V 4.0V 100 3.0V 2.0V 10 1.0V 1 0.0001 1 XC6108N25AGR Leak Current: ILEAK (μA) VIN=VSEN=6.0V 0.25 0.20 0.15 0.10 1 2 3 4 5 Output Voltage: VOUT (V) 18/22 0.25 0.20 0.15 0.10 -50 0.001 0.01 0.1 DelayCapacitance Capacitance: Cd(μF) ( F) Delay : Cd (14) Leakage Current vs. Supply Voltage 0 V IN=V SEN=6.0V V OUT=6.0V Leak Carrent: ILEAK ( μ A) Detect : TDF DetectDelay DelayTime Time: TDF(μs) ( s) 1000 6 -25 0 25 50 75 Ambient Temperature: Ta (℃ ) 100 XC6108 series is Not Recommended for New Designs. XC6108 Series ■PACKAGING INFORMATION ●USP-4 * Soldering fillet surface is not formed because the sides of the pins are plated. ●SOT-25 2.9±0.2 +0.1 0.4 -0.05 5 4 0～0.1 1 2 (0.95) 3 +0.1 0.15 -0.05 1.9±0.2 19/22 XC6108 series is Not Recommended for New Designs. XC6108 Series ■PACKAGING INFORMATION (Continued) ●USP-4 Reference Pattern Layout 20/22 ●USP-4 Reference Metal Mask Design XC6108 XC6108 series is Not Recommended for New Designs. Series ■MARKING RULE ●SOT-25 ① represents output configuration and integer number of detect voltage 5 CMOS Output (XC6108C Series) MARK VOLTAGE (V) A 0.x B 1.x C 2.x D 3.x E 4.x F 5.x 4 ① ② ③ ④ 1 2 3 SOT-25 (TOP VIEW) N-ch Open Drain Output (XC6108N Series) MARK VOLTAGE (V) K 0.x L 1.x M 2.x N 3.x P 4.x R 5.x ② represents decimal number of detect voltage (ex.) MARK 3 0 VOLTAGE (V) x.3 x.0 PRODUCT SERIES XC6108xx3xxx XC6108xx0xxx ③ represents options MARK A B C D OPTIONS Built-in delay capacitance pin with hysteresis 5% (TYP.) (Standard) Built-in delay capacitance pin with hysteresis less than 1% (Standard) No built-in delay capacitance pin with hysteresis 5% (TYP.) (Semi-custom) No built-in delay capacitance pin with hysteresis less than 1% (Semi-custom) PRODUCT SERIES XC6108xxxAxx XC6108xxxBxx XC6108xxxCxx XC6108xxxDxx ④ represents production lot number 0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated. (G, I, J, O, Q, W excluded) ●USP-4 ①② 2 ③④ 1 ① represents output configuration and integer number of detect voltage USP-4 (TOP VIEW) 4 3 CMOS Output (XC6108C Series) MARK VOLTAGE (V) A 0.x B 1.x C 2.x D 3.x E 4.x F 5.x ② represents decimal number of detect voltage (ex.) MARK VOLTAGE (V) 3 x.3 0 x.0 N-ch Open Drain Output (XC6108N Series) MARK VOLTAGE (V) K 0.x L 1.x M 2.x N 3.x P 4.x R 5.x PRODUCT SERIES XC6108xx3xxx XC6108xx0xxx ③ represents options MARK OPTIONS A Built-in delay capacitance pin with hysteresis 5% (TYP.) (Standard) Built-in delay capacitance pin with hysteresis less than 1% (Standard) No built-in delay capacitance pin with hysteresis 5% (TYP.) (Semi-custom) No built-in delay capacitance pin with hysteresis less than 1% (Semi-custom) B C D PRODUCT SERIES XC6108xxxAxx XC6108xxxBxx XC6108xxxCxx XC6108xxxDxx ④ represents production lot number 0 to 9, A to Z repeated. (G, I, J, O, Q, W excluded) *No character inversion used. 21/22 XC6108 Series XC6108 series is Not Recommended for New Designs. 1. The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet. 3. Please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. The products in this datasheet are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. Atomic energy; aerospace; transport; combustion and associated safety equipment thereof.) 5. Please use the products listed in this datasheet within the specified ranges. Should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. We assume no responsibility for damage or loss due to abnormal use. 7. All rights reserved. No part of this datasheet may be copied or reproduced without the prior permission of TOREX SEMICONDUCTOR LTD. 22/22