XC6118C21CGR-G

XC6118 Series ETR02013-006 Voltage Detector with Separated Sense Pin & Delay Capacitor Pin ■GENERAL DESCRIPTION The XC6118 series is a low power consumption voltage detector with high accuracy detection, manufactured using CMOS process and laser trimming technologies. Since the sense pin is separated from the power supply pin, it allows the IC to monitor the other power supply. The XC6118 can maintain the state of detection even when voltage of the monitored power supply drops to 0V. Moreover, a release delay time can be adjusted by the external capacitor connected to the Cd pin. The VOUT pin is available in both CMOS and N-channel open drain output configurations. ■APPLICATIONS ■FEATURES ●Microprocessor reset circuitry High Accuracy :±2% (Detect Voltage≧1.5V) ±30mV(Detect Voltage＜1.5V) ●Charge voltage monitors Low Power Consumption ●Memory battery back-up switch circuits : 0.4μA TYP. (Detect, VIN=1.0V) 0.8μA TYP. (Release, VIN=1.0V) ●Power failure detection circuits Detect Voltage Range : 0.8V ~ 5.0V (0.1V increments) Operating Voltage Range : 1.0V ~ 6.0V Temperature Characteristics : ±100ppm/℃ TYP. Output Configuration : CMOS, N-channel open drain Pin Function : Power supply separation Release delay time adjustable Operating Ambient Temperature : -40℃ ~ 85℃ ■TYPICAL APPLICATION CIRCUIT Packages : USP-4, SOT-25 Environmentally Friendly : EU RoHS Compliant, Pb Free ■TYPICAL PERFORMANCE CHARACTERISTICS ●Output Voltage vs. Sense Voltage VIN VSEN VOUT (No Pull-Up resistor needed for CMOS output product) Cd Cd VSS Output Voltage: VOUT (V) VIN Monitoring Power 別電源 supply XC6118C25AGR R=100kΩ Ta=25℃ 7.0 6.0 VIN=6.0V 5.0 4.0 4.0V 3.0 2.0 1.0 1.0V 0.0 -1.0 0 1 2 3 4 5 6 Sense Voltage: VSEN (V) 1/21 XC6118 Series ■PIN CONFIGURATION Cd/NC Cd VSEN 5 Cd/NC 2 VOUT 1 4 3 VSEN 5 VSS 4 VIN 1 2 3 VOUT VSS VIN USP-4 (BOTTOM VIEW) SOT-25 (TOP VIEW) * In the XC6118xxxA/B series, the dissipation pad should not be short-circuited with other pins. * In the XC6118xxxC/D series, when the dissipation pad is short-circuited with other pins, connect it to the NC pin (No.2) pin before use. ■PIN ASSIGNMENT PIN NUMBER USP-4 SOT-25 1 2 2 3 4 5 1 5 5 4 3 2 PIN NAME FUNCTION VOUT Cd NC VSEN VIN VSS Output (Detect ”L”) Delay Capacitance (*1) No Connection Sense Input Ground (*2) NOTE: *1: With the VSS pin of the USP-4 package, a tab on the backside is used as the pin No.5. *2: In the case of selecting no built-in delay capacitance pin type, the delay capacitance (Cd) pin will be used as the NC. ■PRODUCT CLASSIFICATION ●Ordering Information XC6118①②③④⑤⑥-⑦(*1) DESIGNATOR ITEM ① Output Configuration ②③ Detect Voltage ④ Options SYMBOL C CMOS output N N-ch open drain output 08 ~ 50 Packages (Order Unit) e.g. 18 → 1.8V A Built-in delay capacitance pin, hysteresis 5% (TYP.) (Standard*) B Built-in delay capacitance pin, hysteresis less than 1%(Standard*) C D ⑤⑥-⑦ DESCRIPTION No built-in delay capacitance pin, hysteresis 5% (TYP.) (Semi-custom) No built-in delay capacitance pin, hysteresis less than 1% (Semi-custom) GR-G USP-4 (3,000pcs/Reel) MR-G SOT-25 (3,000pcs/Reel) *When delay function isn’t used, open the delay capacitance pin before use. (*1) The “-G” suffix denotes Halogen and Antimony free as well as being fully EU RoHS compliant. 2/21 XC6118 Series ■BLOCK DIAGRAMS (1) XC6118CxxA VIN M2 M4 VSEN Ｒ ＳＥＮ =R1+R2+R3 Rdelay Comparator Inverter R1 VOUT R2 M3 Vref R3 M1 M5 VSS Cd *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118CxxC (semi-custom). (2) XC6118CxxB VIN M2 M4 VSEN Ｒ ＳＥＮ =R1+R2 Rdelay Comparator Inverter R1 R2 VOUT M3 Vref M1 VSS Cd *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118CxxD (semi-custom). (3) XC6118NxxA VIN VSEN M2 Ｒ ＳＥＮ =R1+R2+R3 Rdelay Comparator Inverter R1 VOUT R2 M3 Vref R3 M5 *The delay capacitance pin (Cd) is not M1 VSS Cd connected to the circuit in the block diagram of XC6118NxxC (semi-custom). (4) XC6118NxxB VIN VSEN M2 Ｒ ＳＥＮ =R1+R2 Comparator Rdelay Inverter R1 R2 VOUT M3 Vref M1 VSS Cd *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118NxxD (semi-custom). * Diodes inside the circuits are ESD protection diodes and parasitic diodes. 3/21 XC6118 Series ■ABSOLUTE MAXIMUM RATINGS ●XC6118xxxA/B PARAMETER Input Voltage Output Current XC6118C (*1) Output Voltage XC6118N (*2) Sense Pin Voltage Delay Capacitance Pin Voltage Delay Capacitance Pin Current USP-4 Power Dissipation SOT-25 Operating Ambient Temperature Storage Temperature Ta=25℃ SYMBOL RATINGS UNITS VIN IOUT V mA Ta Tstg VSS-0.3 ~ 7.0 10 VSS-0.3 ~ VIN+0.3 VSS-0.3 ~ 7.0 VSS-0.3 ~ 7.0 VSS-0.3 ~ VIN+0.3 5.0 120 250 -40 ~ 85 -55 ~ 125 SYMBOL RATINGS UNITS VIN IOUT VSS-0.3 ~ 7.0 10 VSS-0.3 ~ VIN+0.3 VSS-0.3 ~ 7.0 VSS-0.3 ~ 7.0 120 250 -40 ~ 85 -55 ~ 125 V mA VOUT VSEN VCD ICD Pd ●XC6118xxxC/D PARAMETER Input Voltage Output Current XC6118C (*1) Output Voltage XC6118N (*2) Sense Pin Voltage USP-4 Power Dissipation SOT-25 Operating Ambient Temperature Storage Temperature NOTE: *1: CMOS output *2: N-ch open drain output 4/21 V V V mA mW oC oC Ta=25℃ VOUT VSEN Pd Ta Tstg V V mW oC oC XC6118 Series ■ELECTRICAL CHARACTERISTICS ●XC6118xxxA Ta=25℃ PARAMETER SYMBOL CONDITIONS MIN. Operating Voltage VIN VDF(T)=0.8 ~ 5.0V (*1) 1.0 V - Detect Voltage VDF VIN=1.0 ~ 6.0V E-1 V ① Hysteresis Width VHYS VIN=1.0 ~ 6.0V E-2 V ① Detect Voltage Line Regulation ΔVDF/ (ΔVIN・VDF) VIN=1.0 ~ 6.0V ±0.1 %/V ① Supply Current 1 (*2) ISS1 VSEN=VDF×0.9 VIN=1.0V VIN=6.0V 0.4 0.4 1.0 1.0 μA ② Supply Current 2 (*2) ISS2 VSEN=VDF×1.1 VIN=1.0V VIN=6.0V 0.8 0.9 1.6 1.8 μA ② IOUT1 VSEN=0V, VDS=0.5V(Nch) VIN=1.0V VIN=2.0V VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V mA ③ IOUT2 VSEN=6.0V, VDS=0.5V(Pch) VIN=1.0V VIN=6.0V mA ④ μA ③ Output Current (*3) Leakage Current CMOS Output (P-ch) N-ch Open Drain Output ILEAK Temperature Characteristics ΔVDF/ (ΔTopr・ VDF) Sense Resistance (*4) Delay Resistance (*5) Delay capacitance pin Sink Current Delay Capacitance Pin Threshold Voltage Undefined Operation (*6) 0.1 0.8 1.2 1.6 1.8 1.9 TYP. UNITS 6.0 0.7 1.6 2.0 2.3 2.4 2.5 -0.30 -1.00 VIN=6.0V, VSEN=0V, VOUT=0V, Cd: Open MAX. -0.08 -0.70 CIRCUITS -0.20 VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open 0.20 0.40 -40 oC≦Topr≦85 oC ±100 ppm/oC ① RSEN VSEN=5.0V, VIN=0V E-4 MΩ ⑤ RDELAY VSEN=6.0V, VIN=5.0V Cd=0V MΩ ⑥ ICD Cd=0.5V, VIN=1.0V μA ⑥ VTCD VSEN=6.0V, VIN=1.0V VSEN=6.0V, VIN=6.0V 1.6 2.0 2.4 200 0.4 2.9 0.5 3.0 0.6 3.1 V ⑦ VUNS VIN=VSEN=0 ~ 1.0V 0.3 0.4 V ⑧ Detect Delay Time (*7) tDF0 VIN=6.0V, VSEN=6.0V→0V Cd: Open 30 230 μs ⑨ Release Delay Time (*8) tDR0 VIN=6.0V, VSEN=0V→6.0V Cd: Open 30 200 μs ⑨ NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: It is calculated from the voltage value of the VIN and the current value of the Cd. *6: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *7: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *8: Delay time from the time of VIN= VDF +VHYS to the time of VOUT = 5.4V when the VSEN rises. 5/21 XC6118 Series ■ELECTRICAL CHARACTERISTICS (Continued) Ta=25℃ ●XC6118xxxB PARAMETER SYMBOL CONDITIONS MIN. Operating Voltage VIN VDF(T)=0.8 ~ 5.0V (*1) 1.0 Detect Voltage VDF VIN=1.0 ~ 6.0V E-1 Hysteresis Width VHYS VIN=1.0 ~ 6.0V Detect Voltage Line Regulation ΔVDF/ (ΔVIN・VDF) Supply Current 1 (*2) Supply Current 2 (*2) Output Current Leakage Current MAX. UNITS 6.0 V - V ① E-3 V ① VIN=1.0~ 6.0V ±0.1 %/V ① ISS1 VSEN=VDF×0.9 VIN=1.0V VIN=6.0V 0.4 0.4 1.0 1.0 μA ② ISS2 VSEN=VDF×1.1 VIN=1.0V VIN=6.0V 0.8 0.9 1.6 1.8 μA ② IOUT1 VSEN=0V VDS=0.5V(Nch) VIN=1.0V VIN=2.0V VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V mA ③ IOUT2 VSEN=6.0V VDS=0.5V(Pch) VIN=1.0V VIN=6.0V mA ④ μA ③ ppm/oC ① MΩ ⑤ MΩ ⑥ μA ⑥ (*3) CMOS Output (P-ch) N-ch Open Drain Output Temperature Characteristics ILEAK ΔVDF/ (ΔTopr・ VDF) RSEN VSEN=5.0V, VIN=0V VSEN=6.0V, VIN=5.0V Cd=0V ICD Cd=0.5V, VIN=1.0V Delay Capacitance Pin Threshold Voltage VTCD VSEN=6.0V, VIN=1.0V VSEN=6.0V, VIN=6.0V Undefined Operation (*6) VUNS Detect Delay Time (*7) Release Delay Time (*8) Sink Current 0.20 -40 oC≦Topr≦85 oC RDELAY -0.08 -0.70 0.40 ±100 E-4 1.6 2.0 2.4 200 0.4 2.9 0.5 3.0 0.6 3.1 V ⑦ VIN=VSEN=0~1.0V 0.3 0.4 V ⑧ tDF0 VIN=6.0V, VSEN=6.0V→0V Cd: Open 30 230 μs ⑨ tDR0 VIN=6.0V, VSEN=0V→6.0V Cd: Open 30 200 μs ⑨ NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: It is calculated from the voltage value of the VIN and the current value of the Cd. *6: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *7: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *8: Delay time from the time of VIN= VDF +VHYS to the time of VOUT= 5.4V when the VSEN rises. 6/21 CIRCUITS -0.20 VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open Delay Resistance (*5) 0.7 1.6 2.0 2.3 2.4 2.5 -0.30 -1.00 VIN=6.0V, VSEN=0V, VOUT=0V, Cd: Open Sense Resistance (*4) Delay capacitance pin 0.1 0.8 1.2 1.6 1.8 1.9 TYP. XC6118 Series ■ELECTRICAL CHARACTERISTICS (Continued) ●XC6118xxxC Ta=25℃ PARAMETER SYMBOL CONDITIONS MIN. Operating Voltage VIN VDF(T)=0.8 ~ 5.0V (*1) 1.0 Detect Voltage VDF VIN=1.0 ~ 6.0V Hysteresis Width TYP. MAX. UNITS CIRCUITS 6.0 V - E-1 V ① VHYS VIN=1.0 ~ 6.0V E-2 V ① ΔVDF/ (ΔVIN・ VDF) VIN=1.0 ~ 6.0V ±0.1 %/V ① Supply Current 1 (*2) ISS1 VSEN=VDF×0.9 VIN=1.0V VIN=6.0V 0.4 0.4 1.0 1.0 μA ② Supply Current 2 (*2) ISS2 VSEN=VDF×1.1 VIN=1.0V VIN=6.0V 0.8 0.9 1.6 1.8 μA ② IOUT1 VSEN=0V, VDS=0.5V(Nch) VIN=1.0V VIN=2.0V VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V mA ③ IOUT2 VSEN=6.0V, VDS=0.5V(Pch) VIN=1.0V VIN=6.0V mA ④ μA ③ ppm/oC ① Detect Voltage Line Regulation Output Current (*3) Leakage Current CMOS Output (P-ch) Nch Open Drain Output ILEAK 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 -0.30 -1.00 VIN=6.0V, VSEN=0V, VOUT=0V -0.20 VIN=6.0V, VSEN=6.0V, VOUT=6.0V 0.20 -0.08 -0.70 0.40 Temperature Characteristics ΔVDF/ (ΔTopr・ VDF) -40 oC≦ Topr ≦85 oC ±100 Sense Resistance (*4) RSEN VSEN=5.0V VIN=0V E-4 MΩ ⑤ Undefined Operation (*5) VUNS VIN=VSEN=0~1.0V 0.3 0.4 V ⑦ Detect Delay Time (*6) tDF0 VIN=6.0V, VSEN=6.0→0V 30 230 μs ⑨ Release Delay Time (*7) tDR0 VIN=6.0V, VSEN=0→6.0V 30 200 μs ⑨ NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *6: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *7: Delay time from the time of VIN= VDF +VHYS to the time of VOUT= 5.4V when the VSEN rises. 7/21 XC6118 Series ■ELECTRICAL CHARACTERISTICS (Continued) Ta=25℃ ●XC6118xxxD PARAMETER Operating Voltage SYMBOL CONDITIONS MIN. (*1) TYP. UNITS CIRCUITS 6.0 V - VIN VDF(T)=0.8 ~ 5.0V Detect Voltage VDF VIN=1.0 ~ 6.0V E-1 V ① Hysteresis Width VHYS VIN=1.0 ~ 6.0V E-3 V ① ΔVDF/ (ΔVIN・ VDF) VIN=1.0～6.0V ±0.1 %/V ① Supply Current 1 (*2) ISS1 VSEN=VDF×0.9 VIN=1.0V VIN=6.0V 0.4 0.4 1.0 1.0 μA ② Supply Current 2 (*2) ISS2 VSEN=VDF×1.1 VIN=1.0V VIN=6.0V 0.8 0.9 1.6 1.8 μA ② IOUT1 VSEN=0V VDS=0.5V(Nch) VIN=1.0V VIN=2.0V VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V mA ③ IOUT2 VSEN=6.0V, VDS=0.5V(Pch) VIN=1.0V VIN=6.0V mA ④ μA ③ ppm/oC ① Detect Voltage Line Regulation Output Current (*3) Leakage Current CMOS Output (P-ch) Nch Open Drain Output ILEAK 1.0 MAX. 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 -0.30 -1.00 VIN=6.0V, VSEN=0V, VOUT=0V -0.20 VIN=6.0V, VSEN=6.0V, VOUT=6.0V 0.20 -0.08 -0.70 0.40 Temperature Characteristics ΔVDF/ (ΔTopr・ VDF) -40 oC≦Topr≦85 oC ±100 Sense Resistance (*4) RSEN VSEN=5.0V, VIN=0V E-4 MΩ ⑤ Undefined Operation (*5) VUNS VIN=VSEN=0~1.0V 0.3 0.4 V ⑦ Detect Delay Time (*6) tDF0 VIN=6.0V VSEN=6.0→0V 30 230 μs ⑨ Release Delay Time (*7) tDR0 VIN=6.0V VSEN=0→6.0V 30 200 μs ⑨ NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *6: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *7: Delay time from the time of VIN= VDF +VHYS to the time of VOUT = 5.4V when the VSEN rises. 8/21 XC6118 Series ■VOLTAGE CHART SYMBOL PARAMETER NOMINAL VOLTAGE VDF(T) (V) 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 E-1 DETECT VOLTAGE (V) MIN. 0.770 0.870 0.970 1.070 1.170 1.270 1.370 1.470 1.568 1.666 1.764 1.862 1.960 2.058 2.156 2.254 2.352 2.450 2.548 2.646 2.744 2.842 2.940 3.038 3.136 3.234 3.332 3.430 3.528 3.626 3.724 3.822 3.920 4.018 4.116 4.214 4.312 4.410 4.508 4.606 4.704 4.802 4.900 VDF (*1) MAX. 0.830 0.930 1.030 1.130 1.230 1.330 1.430 1.530 1.632 1.734 1.836 1.938 2.040 2.142 2.244 2.346 2.448 2.550 2.652 2.754 2.856 2.958 3.060 3.162 3.264 3.366 3.468 3.570 3.672 3.774 3.876 3.978 4.080 4.182 4.284 4.386 4.488 4.590 4.692 4.794 4.896 4.998 5.100 E-2 E-3 E-4 HYSTERESIS RANGE (V) HYSTERESIS RANGE (V) SENSE RESISTANCE (MΩ) MIN. 0.015 0.017 0.019 0.021 0.023 0.025 0.027 0.029 0.031 0.033 0.035 0.037 0.039 0.041 0.043 0.045 0.047 0.049 0.051 0.053 0.055 0.057 0.059 0.061 0.063 0.065 0.067 0.069 0.071 0.073 0.074 0.076 0.078 0.080 0.082 0.084 0.086 0.088 0.090 0.092 0.094 0.096 0.098 VHYS MAX. 0.066 0.074 0.082 0.090 0.098 0.106 0.114 0.122 0.131 0.085 0.147 0.155 0.163 0.171 0.180 0.188 0.196 0.204 0.212 0.220 0.228 0.237 0.245 0.253 0.261 0.269 0.277 0.286 0.294 0.302 0.310 0.318 0.326 0.335 0.343 0.351 0.359 0.367 0.375 0.384 0.392 0.400 0.408 MIN. 0 VHYS MAX. 0.008 0.009 0.010 0.011 0.012 0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.020 0.021 0.022 0.023 0.024 0.026 0.027 0.028 0.029 0.030 0.031 0.032 0.033 0.034 0.035 0.036 0.037 0.038 0.039 0.040 0.041 0.042 0.043 0.044 0.045 0.046 0.047 0.048 0.049 0.050 0.051 MIN. RSEN TYP. 10 20 13 24 15 28 NOTE: *1: When VDF(T)≦1.4V, the detection accuracy is ±30mV. When VDF(T)≧1.5V, the detection accuracy is ±2%. 9/21 XC6118 Series ■TEST CIRCUITS Circuit 2 Circuit 1 RPULL =100kΩ (No resistor needed for VIN VSEN CMOS output products) VOUT VIN A VSEN XC6118 Series VOUT XC6118 Series Cd Cd V VSS VSS Circuit 4 Circuit 3 VIN VIN VSEN VOUT VSEN VOUT XC6118 Series A XC6118 Series A Cd Cd VSS VSS Circuit 5 Circuit 6 VIN VSEN A VIN VOUT VSEN XC6118 Series VOUT XC6118 Series Cd A Cd VSS VSS Circuit 8 Circuit 7 RPULL =100kΩ VIN VSEN VIN (No resistor needed for VOUT CMOS output products) VSEN XC6118 Series Cd V VOUT XC6118 Series V V Cd VSS VSS Circuit 9 RPULL =100kΩ VIN VSEN (No resistor needed for CMOS output products) VOUT XC6118 Series Waveform Measurement Point Cd VSS 10/21 *No delay capacitance pin available in the XC6118xxxC/D series. XC6118 Series ■OPERATIONAL EXPLANATION A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2. VIN *The XC6118N series (N-ch open drain output) requires a pull-up resistor for pulling up output. M2 VSEN M4 ＲＳEN=R1+R2+R3 Rdelay Comparator Inverter VOUT R1 VIN VSEN R2 R3 M3 Vref M5 M1 VSS Cd Cd Figure 1: Typical application circuit example Sense Pin Voltage: VSEN(MIN.:0V, MAX.:6.0V) Release Voltage: VDF+VHYS Detect Voltage: VDF Delay Capacitance Pin Voltage: VCD(MIN.:VSS, MAX.:VIN) Delay Capacitance Pin Threshold Voltage: VTCD Output Voltage Pin Voltage: VOUT (MIN.:VSS ① ② ③ ④ ⑤ ⑥ ⑦ Figure 2: The timing chart of Figure 1 ① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged to the power supply input voltage, (VIN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to reach the detect voltage (VDF) (VSEN>VDF), the output voltage (VOUT) keeps the “High” level (=VIN). * If a pull-up resistor of the XC6118N series (N-ch open drain) is connected to added power supply different from the input voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected. ② When the sense pin voltage keeps dropping and becomes equal to the detect voltage (VSEN =VDF), an N-ch transistor (M1) for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An inverter (Inv.1) operates as a comparator of the reference voltage VIN, and the output voltage changes into the “Low” level (=VSS). The detect delay time [tDF] is defined as time which ranges from VSEN=VDF to the VOUT of “Low” level (especially, when the Cd pin is not connected: tDF0). ③ While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground voltage (=VSS) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to reach the release voltage (VSEN< VDF +VHYS). 11/21 XC6118 Series ■OPERATIONAL EXPLANATION (Continued) ④ When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor (M1) for the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay resistor (RDELAY). The inverter (Inv.1) will operate as a comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic Threshold: VTHL=VSS) while the sense pin voltage keeps higher than the detect voltage (VSEN > VDF). ⑤ While the delay capacitance pin voltage (VCD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC series circuit. Assuming the time to the release delay time (tDR), it can be given by the formula (1). tDR=-RDELAY×Cd×ln(1-VTCD/VIN) …(1) The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and the delay capacitance pin threshold voltage is VIN /2 (TYP.) tDR=RDELAY×Cd×0.69 …(2) *：RDELAY is 2.0MΩ(TYP.) As an example, presuming that the delay capacitance is 0.68μF, tDR is : 2.0×106×0.68×10-6×0.69=938(ms) * Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the ground (=VSS) level because time described in ③ is short. ⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (VCD=VTCD), the inverter (Inv.1) will be inverted. As a result, the output voltage changes into the “High” (=VIN) level. tDR0 is defined as time which ranges from VSEN=VDF+VHYS to the VOUT of “High” level without connecting to the Cd. ⑦ While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the delay capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=VIN) level. ●Function Chart VSEN Cd L H L H L H L H L TRANSITION OF VOUT CONDITION *1 ① ② L ⇒ L L ⇒ L H ⇒ H ⇒ H ●Example ex. 1) VOUT ranges from ‘L’ to ‘H’ in case of VSEN = ‘H’ (VDR≧VSEN), Cd=’H’ (VTCD≧Cd) while VOUT is ‘L’. ex. 2) VOUT maintains ‘H’ when Cd ranges from ‘H’ to ‘L’, VSEN=’H’ and Cd=’L’ when VOUT becomes ‘H’ in ex.1. ●Release Delay Time Chart DELAY CAPACITANCE [Cd] (μF) 0.010 0.022 0.047 0.100 0.220 0.470 1.000 RELEASE DELAY TIME [tDR] (TYP.) (ms) 13.8 30.4 64.9 138 304 649 1380 * The release delay time values above are calculated by using the formula (2). *2: The release delay time (tDR) is influenced by the delay capacitance Cd. 12/21 RELEASE DELAY TIME [tDR] *2 (MIN. ~ MAX.) (ms) 11.0 ~ 16.6 24.3 ~ 36.4 51.9 ~ 77.8 110 ~ 166 243 ~ 364 519 ~ 778 1100 ~ 1660 XC6118 Series ■NOTES ON USE 1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is liable to malfunction should the ratings be exceeded. 2. The power supply input pin voltage drops by the resistance between power supply and the VIN pin, and by through current at operation of the IC. At this time, the operation may be wrong if the power supply input pin voltage falls below the minimum operating voltage range. In CMOS output, for output current, drops in the power supply input pin voltage similarly occur. Moreover, in CMOS output, when the VIN pin and the sense pin are short-circuited and used, oscillation of the circuit may occur if the drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis voltage. Note it especially when you use the IC with the VIN pin connected to a resistor. 3. When the setting voltage is less than 1.0V, be sure to separate the VIN pin and the sense pin, and to apply the voltage over 1.0V to the VIN pin. 4. Note that a rapid and high fluctuation of the power supply input pin voltage may cause a wrong operation. 5. Power supply noise may cause operational function errors, Care must be taken to put the capacitor between VIN-GND and test on the board carefully. 6. If the VIN pin voltage drops sharply (example: 6.0V to 0V) during the release operation with a Cd (delay capacitance) connected to the Cd pin, an overcurrent will flow through the diode between the Cd and VIN pin. If the fluctuation range of the VIN pin during the release operation is less than 1.0V, no special measures are required, but if the Cd is 0.1μF or more and the power supply voltage fluctuation is 0.01V/μs or more, please take either one of the following measures. ・ To place a Schottky diode between the VIN pin and the Cd pin. (See Figure 3) ・ To place a resistance (RCd) of 500Ω to 1kΩ between the Cd and Cd pin. (See Figure 4) * Please note if the RCd is connected between the Cd and Cd pin, the Cd discharge time will be longer. When connecting the RCd, please confirm in advance that there is no problem in actual operation. VIN VIN Rpull VSEN VSEN VOUT VIN Cd VSEN VOUT VIN VOUT RCd Figure 3: Circuit example with a Schottky diode connected to the Cd pin VOUT Cd VSS Cd Rpull VSEN VSS Cd Figure 4: Circuit example with a resistor connected to the Cd pin 13/21 XC6118 Series ■NOTES ON USE 7. In N-channel open drain output, VOUT voltage at detect and release is determined by resistance of a pull up resistor connected at the VOUT pin. Please choose proper resistance values with refer to Figure 5; During detection: VOUT = VPULL / (1+RPULL / RON) VPULL: Pull up voltage RON(※1)：On resistance of N channel driver M3 can be calculated as VDS / IOUT1 from electrical characteristics, For example, when (※2) RON = 0.5 / 0.8×10-3 = 625Ω(MAX.)at VIN=2.0V, VPULL = 3.0V and VOUT ≦0.1V at detect, RPULL= (VPULL /VOUT-1)×RON= (3 / 0.1-1)×625≒18kΩ In this case, RPULL should be selected higher or equal to 18kΩ in order to keep the output voltage less than 0.1V during detection. (※1) RON is bigger when VIN is smaller, be noted. (※2) For calculation, Minimum VIN should be chosen among the input voltage range. During releasing：VOUT = VPULL / (1 + RPULL / ROFF) VPULL：Pull up voltage ROFF：On resistance of N channel driver M3 is 15MΩ(MIN.) when the driver is off (as to VOUT / ILEAK) For example：when VPULL = 6.0V and VOUT ≧ 5.99V, RPULL = (VPULL / VOUT-1)×ROFF = (6/5.99-1)×15×106 ≒25 kΩ In this case, RPULL should be selected smaller or equal to 25 kΩ in order to obtain output voltage higher than 5.99V during releasing. VPULL VIN M2 VSEN ＲＳEN=R1+R2+R3 RPULL RDELAY Comparator Inverter ILEAK R1 VIN VSEN VOUT M3 R2 Vref R3 M5 M1 VSS Cd Figure 5: Circuit example of XC6118N 8. Torex places an importance on improving our products and their reliability. We request that users incorporate fail-safe designs and post-aging protection treatment when using Torex products in their systems. 14/21 XC6118 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (1) Supply Current vs. Sense Voltage Supply Current: ISS (μA) XC6118C25Ax VIN=3.0V 2.0 Ta=85℃ 1.5 25℃ 1.0 0.5 -40℃ 0.0 0 1 2 3 4 5 6 Sense Voltage: VSEN (V) (2) Supply Current vs. Input Voltage XC6118C25Ax VSEN=2.25V 1.2 1.0 Ta=85℃ 0.8 25℃ 0.6 0.4 -40℃ 0.2 0.0 0 2 1 3 4 Ta=85℃ 1.0 0.8 0.6 25℃ 0.4 -40℃ 0.2 0.0 0 6 5 VSEN=2.75V 1.2 Supply Current: ISS (μA) Supply Current: ISS (μA) XC6118C25Ax 2 3 4 5 6 Input Voltage: VIN (V) Input Voltage: VIN (V) (3) Detect Voltage vs. Ambient Temperature (4) Detect Voltage vs. Input Voltage XC6118C25Ax XC6118C25Ax VIN=4.0V 2.55 Detect Voltage: VDF (V) 2.55 Detect Voltage: VDF (V) 1 2.50 2.45 Ta=25℃ 85℃ 2.50 -40℃ 2.45 -50 -25 0 25 50 75 Ambient Temperature: Ta (℃) 100 1.0 2.0 3.0 4.0 5.0 6.0 Input Voltage: VIN (V) 15/21 XC6118 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (5) Hysteresis Voltage vs. Ambient Temperature (6) CD Pin Sink Current vs. Input Voltage XC6118C25Ax VIN=4.0V 0.20 Cd PIN Current: ICD (mA) Hysteresis Voltage: VHYS (V) XC6118C25Ax 0.15 0.10 0.05 -50 -25 0 25 50 75 VSEN=0V VDS=0.5V 3.0 2.5 Ta=-40℃ 2.0 25℃ 1.5 1.0 85℃ 0.5 0.0 0 100 1 6.0 Output Voltage: VOUT (V) Output Voltage: VOUT (V) Ta=25℃ 7.0 VIN=6.0V 5.0 4.0 4.0V 3.0 2.0 1.0 1.0V 0.0 -1.0 3 5 6 XC6118N25Ax XC6118C25Ax 2 4 (8) Output Voltage vs. Input Voltage (7) Output Voltage vs. Sense Voltage 1 3 Input Voltage : VIN (V) Ambient Temperature: Ta (℃) 0 2 4 5 VSEN=VIN Pull-up=VIN R=100kΩ 4.0 3.0 Ta=85℃ 2.0 25℃ 1.0 -40℃ 0.0 -1.0 0 6 0.5 1 1.5 2 2.5 3 Input Voltage : VIN (V) Sense Voltage: VSEN (V) (9) Output Current vs. Input Voltage XC6118C25Ax VDS(Nch)=0.5V 4.0 3.5 Output Current: Iout (mA) Output Current: Iout (mA) XC6118C25Ax Ta=-40℃ 3.0 25℃ 2.5 2.0 1.5 85℃ 1.0 0.5 0.0 Ta=85℃ -0.5 -1.0 25℃ -1.5 -40℃ -2.0 0 1 2 3 4 5 Input Voltage : VIN (V) 16/21 VDS(Pch)=0.5V 0.0 6 0 1 2 3 4 5 Input Voltage : VIN (V) 6 XC6118 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (10) Delay Resistance vs. Ambient Temperature (11) Release Delay Time vs. Delay Capacitance XC6118C25Ax VSEN=6.0V VCD=0.0V VIN=5.0V 4 3.5 3 2.5 2 1.5 1 -50 25 0 -25 50 Release Delay time: TDR (ms) Delay Resistance: Rdelay (MΩ) XC6118C25Ax 100 75 100 10 1 tDR=Cd×2.0×10 6 ×0.69 0.1 0.0001 0.001 Leak Current: ILEAK (μA) VIN=6.0V 4.0V 3.0V 2.0V 1.0V 1 0.0001 0.001 0.01 1 XC6118N25Ax Ta=25℃ 10 0.1 (13) Leakage Current vs. Ambient Temperature XC6118C25Ax 100 0.01 Delay Capacitor: Cd (μF) (12) Detect Delay Time vs. Delay Capacitance Detect Delay time: TDF (μs) VIN=1.0V 3.0V 6.0V 1000 Ambient Temperature: Ta (℃) 1000 Ta=25℃ 10000 0.1 1 Delay Capacitor: Cd (μF) VIN=VSEN=6.0V VOUT=6.0V 0.25 0.20 0.15 0.10 -50 -25 0 25 50 75 100 Ambient Temperature: Ta (℃) (14) Leakage Current vs. Supply Voltage Leak Current: ILEAK (μA) XC6118N25Ax VIN=VSEN=6.0V 0.25 0.20 0.15 0.10 0 1 2 3 4 5 6 Output Voltage: VOUT (V) 17/21 XC6118 Series ■PACKAGING INFORMATION For the latest package information go to, www.torexsemi.com/technical-support/packages PACKAGE OUTLINE / LAND PATTERN THERMAL CHARACTERISTICS USP-4 USP-4 PKG USP-4 Power Dissipation SOT-25 SOT-25 PKG SOT-25 Power Dissipation 18/21 XC6118 Series ■MARKING RULE ●SOT-25 ① represents output configuration and integer number of detect voltage CMOS Output (XC6118C Series) N-ch Open Drain Output (XC6118N Series) MARK VOLTAGE (V) MARK VOLTAGE (V) L 0.X T 0.X M 1.X U 1.X N 2.X V 2.X P 3.X X 3.X R 4.X Y 4.X S 5.X Z 5.X 5 ① 4 ② 1 ③ ④ 2 ⑤ 3 SOT-25 (TOP VIEW) ② represents decimal number of detect voltage (ex.) MARK VOLTAGE (V) PRODUCT SERIES 3 0 X.3 X.0 XC6118**3*** XC6118**0*** ③ represents options MARK A B C D OPTIONS Built-in delay capacitance pin with hysteresis 5% (TYP.) (Standard) Built-in delay capacitance pin with hysteresis less than 1% (Standard) No built-in delay capacitance pin with hysteresis 5% (TYP.) (Semi-custom) No built-in delay capacitance pin with hysteresis less than 1% (Semi-custom) PRODUCT SERIES XC6118***A** XC6118***B** XC6118***C** XC6118***D** ④⑤ represents production lot number 0 to 9 A to Z, or inverted characters of 0 to 9, A to Z repeated. (G, I, J, O, Q, and W excluded) *No character inversion used. 19/21 XC6118 Series ■MARKING RULE (Continued) ●USP-4 ① represents output configuration and integer number of detect voltage N-ch Open Drain Output (XC6118N Series) VOLTAGE (V) 0.X 1.X 2.X 3.X 4.X 5.X 1 2 USP-4 (TOP VIEW) ② represents decimal number of detect voltage (ex.) MARK 3 0 VOLTAGE (V) X.3 X.0 PRODUCT SERIES XC6118**3*** XC6118**0*** ③ represents options MARK OPTIONS Built-in delay capacitance pin with hysteresis 5% (TYP.) A (Standard) Built-in delay capacitance pin with hysteresis less than 1% B (Standard) No built-in delay capacitance pin with hysteresis 5% (TYP.) C (Semi-custom) No built-in delay capacitance pin with hysteresis less than 1% D (Semi-custom) ④⑤ represents production lot number 0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated. (G, I, J, O, Q, and W excluded) *No character inversion used. 20/21 ① ② ③ MARK T U V X Y Z ④ ⑤ CMOS Output (XC6118C Series) MARK VOLTAGE (V) L 0.X M 1.X N 2.X P 3.X R 4.X S 5.X PRODUCT SERIES XC6118***A** XC6118***B** XC6118***C** XC6118***D** 4 3 XC6118 Series 1. The product and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. The information in this datasheet is intended to illustrate the operation and characteristics of our products. We neither make warranties or representations with respect to the accuracy or completeness of the information contained in this datasheet nor grant any license to any intellectual property rights of ours or any third party concerning with the information in this datasheet. 3. Applicable export control laws and regulations should be complied and the procedures required by such laws and regulations should also be followed, when the product or any information contained in this datasheet is exported. 4. The product is neither intended nor warranted for use in equipment of systems which require extremely high levels of quality and/or reliability and/or a malfunction or failure which may cause loss of human life, bodily injury, serious property damage including but not limited to devices or equipment used in 1) nuclear facilities, 2) aerospace industry, 3) medical facilities, 4) automobile industry and other transportation industry and 5) safety devices and safety equipment to control combustions and explosions. Do not use the product for the above use unless agreed by us in writing in advance. 5. Although we make continuous efforts to improve the quality and reliability of our products; nevertheless Semiconductors are likely to fail with a certain probability. So in order to prevent personal injury and/or property damage resulting from such failure, customers are required to incorporate adequate safety measures in their designs, such as system fail safes, redundancy and fire prevention features. 6. Our products are not designed to be Radiation-resistant. 7. Please use the product listed in this datasheet within the specified ranges. 8. We assume no responsibility for damage or loss due to abnormal use. 9. All rights reserved. No part of this datasheet may be copied or reproduced unless agreed by Torex Semiconductor Ltd in writing in advance. TOREX SEMICONDUCTOR LTD. 21/21