XC6124F641MR-G

XC6121/XC6122 XC6123/XC6124 Series ETR0209-011b Voltage Detector with Watchdog Function and ON/OFF Control (VDF=1.6V~5.0V) ■GENERAL DESCRIPTION The XC6121/XC6122/XC6123/XC6124 series is a group of high-precision, low current consumption voltage detectors with watchdog functions incorporating CMOS process technology. The series consist of a reference voltage source, delay circuit, comparator, and output driver. With the built-in delay circuit, the series do not require any external components to output signals with release delay time. The output type is VDFL low when detected. The EN/ENB pin can control ON and OFF of the watchdog functions. By setting the EN/ENB pin to low or high level, the watchdog function can be OFF while the voltage detector remains operation. Since the EN/ENB pin of the XC6122 and XC6124 series is internally pulled up to the VIN pin or pulled down to the VSS pin, these series can be used with the EN/ENB pin left open when the watchdog functions is used. The detect voltages are internally fixed 1.6V ~ 5.0V in increments of 0.1V, using laser trimming technology. Six watchdog timeout periods are available in a range from 50ms to 1.6s. Five release delay times are available in a range from 3.13ms to 400ms. ■APPLICATIONS ■FEATURES ●Microprocessor watchdog monitoring and reset circuits ●Memory battery backup circuits ●System power-on reset circuits ●Power failure detection Detect Voltage Range : 1.6V ~ 5.0V, +2% (0.1V increments) : VDFL x 5% (TYP.) : 1.0V ~ 6.0V Hysteresis Width Operating Voltage Range Detect Voltage Temperature Characteristics : +100ppm/OC (TYP.) Output Configuration : N-channel open drain Watchdog Pin : Watchdog input If watchdog input maintains ‘H’ or ‘L’ within the watchdog timeout period, a reset signal is output from the RESETB pin. EN/ENB Pin : When the EN/ENB pin voltage is set to low or high level, the watchdog function is forced off. Release Delay Time : 400ms, 200ms, 100ms, 50ms, 3.13ms (TYP.) Watchdog Timeout Period : 1.6s, 800ms, 400ms, 200ms, 100ms, 50ms (TYP.) Operating Ambient Temperature : -40℃~ +85℃ Packages : SOT-25, USP-6C Environmentally Friendly : EU RoHS Compliant, Pb Free ■TYPICAL APPLICATION CIRCUIT ■TYPICAL PERFORMANCE CHARACTERISTICS ●Supply Current vs. Input Voltage ＸＣ６１２１～ＸＣ６１２４(VDF=２.７Ｖ） 14.0 10.0 Supply Current:　I SS (μA) Ta=85℃ 12.0 8.0 Ta=25℃ Ta=-40℃ 6.0 4.0 2.0 0 0 1 2 3 4 Input Voltage:　V IN (V) 5 6 1/26 XC6121/XC6122/XC6123/XC6124 Series ■PIN CONFIGURATION USP-6C (BOTTOM VIEW) SOT-25 (TOP VIEW) * The dissipation pad for the USP-6C package should be solder-plated in reference mount pattern and metal masking so as to enhance mounting strength and heat release. If the pad needs to be connected to other pins, it should be connected to the VSS (No. 5) pin. ■PIN ASSIGNMENT PIN NUMBER 2/26 PIN NAME FUNCTION 4 RESETB Reset Output 2 5 VSS Ground 3 2 EN/ENB Watchdog ON/OFF Control 4 1 WD Watchdog 5 6 VIN Power Input - 3 NC No Connection SOT-25 USP-6C 1 XC6121/XC6122/XC6123/XC6124 Series ■PRODUCT CLASSIFICATION ●Selection Guide RESET OUTPUT SERIES EN/ENB PIN FUNCTION HYSTERESIS EN/ENB Input VDFL (RESETB) (*1) VDFH (RESET) XC6121 N-channel open drain - EN XC6122 N-channel open drain - EN XC6123 N-channel open drain - XC6124 N-channel open drain - Logic Available: VDFL x 5% (TYP.) (*2) ENB ENB (*1) The output type of RESETB is set to L level at the time of detection. (*2) EN input logic: The watchdog function turns on when the EN pin becomes high level. Pull-Up or Down Resistor With No Pull-Up Resistor With Pull-Up Resistor With No Pull-Down Resistor With Pull-Down Resistor ENB input logic: The watchdog function turns on when the ENB pin becomes low level. ●Ordering Information XC6121①②③④⑤⑥-⑦(*2): N-channel Open Drain Output (RESETB), EN Pin: No Pull-Up Resistor XC6122①②③④⑤⑥-⑦(*2): N-channel Open Drain Output (RESETB), EN Pin: Pull-Up Resistor XC6123①②③④⑤⑥-⑦(*2): N-channel Open Drain Output (RESETB), ENB Pin: No Pull-Down Resistor XC6124①②③④⑤⑥-⑦(*2): N-channel Open Drain Output (RESETB), ENB Pin: Pull-Down Resistor DESIGNATOR ① ② ITEM SYMBOL Release Delay Time (*1) Watchdog Timeout Period A 3.13ms (TYP.) C 50ms (TYP.) D 100ms (TYP.) E 200ms (TYP.) F 400ms (TYP.) 2 50ms (TYP.) 3 100ms (TYP.) 4 200ms (TYP.) 5 400ms (TYP.) 6 1.6s (TYP.) 7 ③④ ⑤⑥-⑦(*2) (*1) (*2) Detect Voltage Packages (Order Unit) DESCRIPTION 16 ~ 50 800ms (TYP.) Detect voltage ex.) 4.5V: ③⇒4, ④⇒5 MR SOT-25 (3,000/Reel) MR-G SOT-25 (3,000/Reel) ER USP-6C (3,000/Reel) ER-G USP-6C (3,000/Reel) Please set the release delay time shorter than or equal to the watchdog timeout period. ex.) XC6121D327MR or XC6121D627MR The “-G” suffix denotes Halogen and Antimony free as well as being fully EU RoHS compliant. 3/26 XC6121/XC6122/XC6123/XC6124 Series ■BLOCK DIAGRAMS ●XC6121 Series N-ch Open Drain Output ●XC6122 Series N-ch Open Drain Output 4/26 XC6121/XC6122/XC6123/XC6124 Series ■BLOCK DIAGRAMS (Continued) ●XC6123 Series N-ch Open Drain Output ●XC6124 Series N-ch Open Drain Output 5/26 XC6121/XC6122/XC6123/XC6124 Series ■ABSOLUTE MAXIMUM RATINGS Ta=25OC PARAMETER SYMBOL RATINGS VSS -0.3 ~ 7.0 VSS-0.3～VIN+0.3≦7.0 Output Current VIN VEN/VENB VWD IRBOUT Output Voltage VRESETB Input Voltage SOT-25 Power Dissipation USP-6C Operating Ambient Temperature Storage Temperature 6/26 Pd Topr Tstg VSS -0.3 ~ 7.0 20 VSS -0.3 ~ 7.0 250 120 -40 ~ +85 -55 ~ +125 UNITS V V V mA V mW C C O O XC6121/XC6122/XC6123/XC6124 Series ■ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Detect Voltage VDFL VEN=VSS Hysteresis Width VHYS VEN=VSS Supply Current (*1) ISS Operating Voltage VIN Output Current IRBOUT Temperature Characteristics △Topr・VDFL Ta=25 OC CONDITIONS WD=OPEN N-ch. VDS=0.5V MIN. TYP. VDFL(T) VDFL(T) × 0.98 VDFL VDFL × 0.02 × 0.05 VIN=VDFL(T)×0.9V 5 VIN=VDFL(T)×1.1V 10 VIN=6.0V 12 1.0 VIN=1.0V 0.15 0.5 VIN=2.0V (VDFL(T)> 2.0V) 2.0 2.5 VIN=3.0V (VDFL(T) >3.0V) 3.0 3.5 VIN=4.0V (VDFL(T) >4.0V) 3.5 4.0 △VDFL / -40OC < Topr < 85 OC MAX. VDFL(T) × 1.02 VDFL × 0.08 11 16 18 6.0 - - +100 - 2.00 37 75 150 300 2.00 37 75 150 300 3.13 50 100 200 400 3.13 50 100 200 400 5.00 63 125 250 500 5.00 63 125 250 500 UNITS CIRCUIT V ① V ① μA ② V ① mA ③ ppm/ OC ① ms ④ ms ④ tDR Time until VIN is increased from 1.0V to 2.0V and attains to the release time level, and the Reset output pin releases. Release Delay Time (VDFL>1.9V) tDR Time until VIN is increased from 1.0V to (VDFL x 1.1V) and attains to the release time level, and the Reset output pin releases. Detect Delay Time tDF Time until VIN is decreased from 6.0V to 1.0V and attains to the detect voltage level, and the Reset output pin detects while the WD pin left open. - 5.5 33 μs ④ VDFL Leakage Current ILEAK VIN=6.0V, VRESETB=6.0V - 0.01 0.1 μA ③ 37 75 150 300 600 1200 37 75 150 300 600 1200 50 100 200 400 800 1600 50 100 200 400 800 1600 63 125 250 500 1000 2000 63 125 250 500 1000 2000 ms ⑤ ms ⑤ Release Delay Time (VDFL VDFL * Please refer to the block diagrams for R1, R2, R3 and Vref. * Hysteresis width is selectable from VDFL x 0.05V (TYP.). The series use a watchdog timer to detect malfunction or “runaway” of the microprocessor. If neither rising nor falling signals are applied from the microprocessor within the watchdog timeout period, the RESETB pin output maintains the detection state for the release delay time (tDR), and thereafter the RESETB pin outputs low to high signal. The watchdog pin is pulled down to the VSS internally. When the watchdog pin is not connected, A reset signal comes out after the watchdog timeout period. Six watchdog timeout period settings (tWD) are available in 1.6s, 800ms, 400ms, 200ms, 100ms, and 50ms. In case where the watchdog function is not used, When the EN pin input driven to low level, only the watchdog function is forced off while the detect voltage circuit remains operation. For using the watchdog function, the EN pin should be used in high level. Even after the input voltage and the EN pin voltage are driven back high, the RESETB pin output maintains the detection state for the release delay time (TDR). (Refer to the TIMING CHART 1-①.) The watchdog function recovers immediately when the input voltage becomes higher than the release voltage and the EN pin voltage driven from low to high level. (Refer to the TIMING CHART 1-②.) A diode, which is an input protection element, is connected between the EN pin and VIN pin. Therefore, if the EN pin is applied voltage that exceeds VIN, the current will flow to VIN through the diode. For avoiding any damage to the IC, please use this IC within the stated maximum ratings (VSS -0.3 ~ VIN +0.3) on the EN pin. In case where the watchdog function is not used, when the ENB pin input driven to high level, only the watchdog function is forced off while the detect voltage circuit remains operation. For using the watchdog function, the ENB pin should be used in low level. Even after the input voltage and the ENB pin voltage are driven back low, the RESETB pin output maintains the detection state for the release delay time (tDR). (Refer to the TIMING CHART 2-①.) The watchdog function recovers immediately when the input voltage becomes higher than the release voltage and the ENB pin voltage driven from high to low level. (Refer to the TIMING CHART 2-②.) A diode, which is an input protection element, is connected between the ENB pin and VIN pin. Therefore, if the ENB pin is applied voltage that exceeds VIN, the current will flow to VIN through the diode. For avoiding any damage to the IC, please use this IC within the stated maximum ratings (VSS -0.3 ~ VIN +0.3) on the ENB pin. Release delay time (tDR) is the time that elapses from when the VIN pin reaches the release voltage, or when the watchdog timeout period expires with no rising signal applied to the WD pin, until the RESETB pin output is released from the detection state. Five release delay time (tDR) watchdog timeout period settings are available in 400ms, 200ms, 100ms, 50ms, and 3.13ms. Detect Delay Time (tDF) is the time that elapses from when the VIN pin voltage falls to the detect voltage until the RESETB pin output goes into the detection state. 9/26 XC6121/XC6122/XC6123/XC6124 Series ■TIMING CHARTS 1. XC6121/XC6122 Series (EN products) ●N-ch Open Drain Output (Rpull=100kΩ) Hysteresis Width ●tDF (N-ch Open Drain Output, Rpull=100kΩ) 10/26 XC6121/XC6122/XC6123/XC6124 Series ■TIMING CHARTS (Continued) 2. XC6123/XC6124 Series (ENB products) ●N-ch Open Drain Output (Rpull=100kΩ) Hysteresis Width ●tDF (N-ch Open Drain Output, Rpull=100kΩ) 11/26 XC6121/XC6122/XC6123/XC6124 Series ■NOTES ON USE 1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is liable to malfunction should the ratings be exceeded. 2. When a resistor is connected between the VIN pin and the input, the VIN voltage drops while the IC is operating and a malfunction may occur as a result of the IC’s through current. 3. In order to stabilize the IC’s operations, please ensure that the VIN pin’s input frequency’s rise and fall times are more than 1 μ s/V. 4. Noise at the power supply may cause a malfunction of the watchdog operation or the voltage detector. In such case, please strength VIN and GND lines. Also, please connect a capacitor such as 0.22μF between the VIN pin and the GND pin and evaluate the device on the actual board carefully before use. 5. Protecting against a malfunction while the watchdog time out period, an ignoring time (no reaction time) occurs to the rise and fall times. Referring to the figure below, the ignoring time (no reaction time) lasts for 900μs at maximum. (refer to the Figure1 below) 6. The EN pin of the XC6121 series is not internally pulled up. When using the watchdog function, please drive the VEN pin in high level. The EN pin of the XC6122 series is internally pulled up. The watchdog function can be used even the EN pin left open. The ENB pin of the XC6123 series is not internally pulled down. When using the watchdog function, please drive the VENB pin in low level. The ENB pin of the XC6124 series is internally pulled down. The watchdog function can be used even the ENB pin left open. 7. Torex places an importance on improving our products and its reliability. However, by any possibility, we would request user fail-safe design and post-aging treatment on system or equipment. [Figure1] 12/26 XC6121/XC6122/XC6123/XC6124 Series ■PIN LOGIC CONDITIONS PIN NAME LOGIC CONDITIONS H VIN>VDFL+VHYS L VINVWDH for more than tWD The state maintaining WD