XC6129C36J7R-G

XC6129 Series ETR0222-005 Voltage Detector with Delay Time Adjustable ■GENERAL DESCRIPTION XC6129 series is an ultra small highly accurate voltage detector with external capacitor type delay function. The device includes a highly accurate reference voltage source, manufactured using CMOS process and laser trimming technology, it maintains low power consumption and high accuracy. The device includes the built-in delay circuit. A release delay time or detect delay time can be set freely by connecting an external delay capacitor to Cd pin. There are two kinds of the output configuration for the XC6129 such as CMOS or N-channel open drain. The series has a function to prevent an indefinite operation. Therefore, when the input pin voltage is under minimum operating voltage, the function controls an output pin voltage in the indefinite operation less than 0.4V (MAX.). Also, the series allows a choice of an output logic when detection; therefore, it is suitable for various electric devices using Microcontrollers. Ultra small package USPN-4,USPQ-4B05 and SSOT-24 (standard) are ideally suited for small design of portable devices and high densely mounting applications. ■FEATURES ■APPLICATIONS ● Microprocessor High Accuracy : ±0.8% (Ta=25℃) ● Logic circuit reset circuitry Temperature Characteristic : ±50ppm/℃ (TYP.) ● Battery check Hysteresis Width : VDFx5% (TYP.) Low Power Consumption : 0.42μA TYP. (at Detect, VDF=2.7V) ● Charge voltage monitors 0.58μA TYP. (at Release, VDF=2.7V) ● Memory battery back-up switch circuits Detect Voltage Options : 1.5V ~ 5.5V (0.1V increments) ● System power on reset Operating Voltage Range : 1.3V ~ 6.0V ● Power failure detection circuits Output Configuration : CMOS or N-channel Open Drain ● Delay circuit Output Logic : Active High or Active Low Release Delay Time : 13.9ms (Cd=0.01μF, RP=2MΩ) Detect Delay Time : 17.9ms (Cd=0.01μF, Rn=2MΩ) Manual Reset Input : When Cd pin is “L” level, detect state Operating Ambient Temperature : -40℃ ~ 85℃ Packages : USPN-4, SSOT-24, USPQ-4B05 Environmentally Friendly : EU RoHS Compliant, Pb Free ● ■TYPICAL APPLICATION CIRCUIT ■ TYPICAL PERFORMANCE CHARACTERISTICS μP VCC RESETB/RESET INPUT Cd/MRB VSS Cd VSS μP VPULL XC6129N Series RESETB RESET VIN VCC RPULL RESETB/RESET INPUT 200 Release Delay Time : DR t (ms) RESETB RESET VIN 180 160 140 120 100 -50 Cd/MRB Cd VSS VIN=VDF×0.9V→ VDF×1.1V Cd=0.1 μ F (tDR=139ms) XC6129 XC6129C Series -25 0 25 50 75 100 Ambient Temperature : Ta (℃) VSS 1/27 XC6129 Series ■BLOCK DIAGRAM 1) XC6129C Series (Type A/B/C/D/E/F) VIN M2 R1 Comparator M4 Rp DELAY/MR CONTROL BLOCK R2 Rn Vre f RESETB M3 M1 VSS Cd/ MRB 2) XC6129C Series (Type G/J/L) VIN M2 R1 Comparator M4 Rp DELAY/MR CONTROL BLOCK R2 Rn Vre f RESET M3 M1 VSS Cd/ MRB * Diodes inside the circuits are ESD protection diodes and parasitic diodes. 2/27 XC6129 Series ■BLOCK DIAGRAM 3) XC6129N Series (Type A/C/E) VIN M2 R1 Comparator Rp DELAY/MR CONTROL BLOCK R2 Rn Vre f RESETB M3 M1 VSS Cd/ MRB 4) XC6129N Series (Type G/J/L) VIN M2 R1 Comparator Rp DELAY/MR CONTROL BLOCK R2 Rn Vre f RESET M3 M1 VSS Cd/ MRB * Diodes inside the circuits are ESD protection diodes and parasitic diodes. 3/27 XC6129 Series ■PRODUCT CLASSIFICATION ●Ordering Information XC6129①②③④⑤⑥-⑦(*1) DESIGNATOR ITEM SYMBOL ① Output Configuration ②③ Detect Voltage DESCRIPTION C CMOS output N Nch open drain output 15~55 e.g. 1.8V → ②=1, ③=8 A B C D ④ Type E Refer to Selection Guide F ⑤⑥-⑦ (*1) (*1) Packages (Order Unit) G J L NR-G SSOT-24 (3,000pcs/Reel) 7R-G USPN-4 (5,000pcs/Reel) 9R-G USPQ-4B05 (5,000pcs/Reel) The “-G” suffix denotes Halogen and Antimony free as well as being fully EU RoHS compliant. ●Selection Guide TYPE RESETB/RESET OUTPUT HYSTERESIS WIDTH A B C D Reset Active Low E 5% (TYP.) F G J Reset Active High L (*2) Only supported with CMOS output. 4/27 RELEASE DELAY DETECT DELAY Yes No No Yes Yes Yes Yes No No Yes Yes Yes Undefined Operation Protect No Yes (*2) No Yes (*2) No Yes (*2) No XC6129 Series ■PIN CONFIGURATION RESETB Cd/MRB RESET 4 3 1 2 VIN VSS VIN 4 RESETB 1 RESET VSS 3 2 Cd/MRB VSS 3 VIN 4 2 1 Cd/MRB RESETB RESET USPN-4 (BOTTOM VIEW) SSOT-24 (TOP VIEW) USPQ-4B05 (BOTTOM VIEW) *The dissipation pad for the USPQ-4B05 packages should be solder-plated in reference mount pattern and metal masking so as to enhance mounting strength and heat release. If the pad needs to be connected to other pins, it should be connected to the V SS (No. 3) pin. ■PIN ASSIGNMENT PIN NUMBER (*1) (*2) PIN NAME FUNCTIONS 4 VIN Power Input 3 3 VSS Ground 3 2 2 Cd/MRB Adjustable Pin for DelayTime /Manual Reset 4 1 1 RESETB Reset Output (Active Low) (*1) RESET Reset Output (Active High) (*2) SSOT-24 USPN-4 USPQ-4B05 1 4 2 Type A ~ F (Refer to the ④ in Ordering Information table) Type G ~ M (Refer to the ④ in Ordering Information table) 5/27 XC6129 Series ■FUNCTION PIN NAME SIGNAL STATUS L Forced Reset H Release OPEN Normal Operation Cd/MRB Refer to the table below. 1) Output Logic: Active Low ●Function VIN VIN≧VDF+VHYS VIN≦VDF VCd//MRB Transition of VRESETB Condition VCd/MRB≦VMRL Reset (Low Level) (*1) VCd/MRB≧VMRH Release (High Level) (*2) VCd/MRB≦VMRL Reset (Low Level) (*1) VCd/MRB≧VMRH Undefined (*3) VCd/MRB Transition of VRESET Condition VCd/MRB≦VMRL Reset (High Level) (*2) VCd/MRB≧VMRH Release (Low Level) (*1) VCd/MRB≦VMRL VCd/MRB≧VMRH Reset (High Level) (*2) Undefined (*3) 2) Output Logic: Active High ●Function VIN VIN≧VDF+VHYS VIN≦VDF (* 1) CMOS output: VIN × 0.1 or less, N-ch open drain output, pull-up voltage × 0.1 or less. (* 2) CMOS output: VIN × 0.9 or higher, N-ch open drain output, pull-up voltage × 0.9 or higher. (* 3) Refer to the OPERATING DESCRIPTION below. 6/27 XC6129 Series ■ABSOLUTE MAXIMUM RATINGS Ta=25℃ PARAMETER SYMBOL RATINGS UNITS Input Voltage VIN -0.3 ~ 6.5 V IRBOUT IROUT ±50 VRESETB VRESET VSS - 0.3 ~ VIN + 0.3 or 6.5 (*3) Cd/MRB Pin Voltage VCd/MRB VSS - 0.3 ~ VIN + 0.3 V Cd/MRB Pin Current ICd/MRB ±5 mA Output Current Output Voltage XC6129C (*1) XC6129N (*2) XC6129C (*1) XC6129N (*2) 50 SSOT-24 Power Dissipation USPN-4 VSS - 0.3 ~ 6.5 mA V 150 Pd USPQ-4B05 100 mW 550 Operating Ambient Temperature Topr -40 ~ 85 ℃ Storage Temperature Tstg -55 ~ 125 ℃ * All voltages are described based on the VSS. (*1) CMOS Output (*2) N-ch Open Drain Output (*3) The maximum value should be either VIN+0.3V or 6.5V in the lowest. 7/27 XC6129 Series ■ELECTRICAL CHARACTERISTICS ●XC6129xxxA~XC6129xxxF Series (Output Logic: Active Low) PARAMETER SYMBOL Detect Voltage VDF VDF(T) (*1)=1.5V~5.5V Temperature Characteristics ΔVDF/ (ΔTopr・VDF) -40℃≦Topr≦85℃ Hysteresis Width VHYS - Supply Current 1 ISS1 VIN= VDF×0.9 (Detect) E-2 (*2) Supply Current 2 ISS2 VIN=VDF×1.1 E-3 (*2) Operating Voltage VIN IRBOUT1 Output Current IRBOUT2 (*7) CONDITIONS Leakage Current N-ch Open Drain Output VDF(T)×0.992 TYP. MAX. VDF(T) VDF(T)×1.008 E-1(*2) ① VDF×0.03 VDF×0.05 VDF×0.07 V ① μA ② V - mA ③ μA ③ (Type:A,C,E) E-31 (*2) - 6.0 3.0 - VIN=2.0V(*3), VRESETB=0.5V (N-ch) 5.2 6.7 - , VRESETB=0.5V (N-ch) 8.6 10.2 - VIN=4.0V(*5), VRESETB=0.5V (N-ch) 10.6 12.3 - VIN=5.0V(*6), VRESETB=0.5V (N-ch) 11.7 13.5 - VIN=2.0V(*8), VRESETB=VIN-0.5V (P-ch) - -1.9 -0.9 VIN=3.0V(*9), VRESETB=VIN-0.5V (P-ch) - -3.1 -2.1 VIN=4.0V(*10), VRESETB=VIN-0.5V (P-ch) - -4.0 -3.0 , VRESETB=VIN-0.5V (P-ch) - -4.7 -3.7 VIN=6.0V, VRESETB=VIN-0.5V (P-ch) - -5.2 -4.2 VIN=VDF×0.9, VRESETB=0V - -0.01 - VIN=6.0V, VRESETB=6.0V - 0.01 0.1 1.8 2.0 2.15 MΩ ④ ILEAK Rp Delay Resistance (*12) Rn T ① ppm/℃ 1.7 (*11) V - VIN=1.3V, VRESETB=0.5V (N-ch) VIN=3.0V Ta=25℃ CIRCUIT ±50 1.3 (*4) UNITS - (Type:B,D,F) (Release) - VIN=5.0V CMOS Output (P-ch) MIN. VIN=6.0V, VCd/MRB =0V (Type: A, B, E, F) VIN=VCd/MRB=VDF×0.9 (Type: C, D, E, F) Undefined Operation (*13) VUNS VINVDF), the output pin voltage VRESETB is at High level. (2) The power input pin voltage continues to drop, and when it reaches the detect voltage (VIN=VDF), the Nch transistor for delay capacitance discharge turns ON and discharge of the delay capacitance starts. When the delay capacitance pin drops below the delay capacitance pin threshold voltage, VRESETB changes to Low level. The time from VIN=VDF until VRESETB changes to Low level is the detect delay tDF (the detect time when the delay capacitance pin is open is tDF0). 13/27 XC6129 Series ■OPERATIONAL DESCRIPTION (Continued) (3) The power input pin voltage drops further, and during the interval when it is below the detect voltage V DF and higher than 1.3V, the delay capacitance pin is discharged to ground level and the output pin voltage V RESETB maintains Low level. (4) During the interval in which the power input pin voltage drops below 1.3V and then rises back to 1.3V or higher, the output pin voltage VRESETB may not be able to maintain Low level. Operation during this interval is called “unstable operation”, and the voltage that appears in VRESETB is called the “unstable operation voltage VUNS”. (5) The power input pin voltage rises, and during the interval that it is higher than 1.3V until it reaches the release voltage (1.3V≤VINVDF), the output pin voltage VRESETB maintains High level. The above operational explanation is for detection using Active Low products. For Active High products, reverse the logic of VRESETB. 14/27 XC6129 Series ■OPERATIONAL DESCRIPTION (Continued) The release delay time and detect delay time are determined by the delay resistance (Rp and Rn) and the delay capacitance (Cd). The delay resistance is set to 2MΩ (TYP.) internally in the circuit, and thus the delay time can be changed using the delay capacitance. You can select a product type that has or does not have the release delay time function and the detect delay time function. (Refer to the Selection Guide.) The release delay tDR is calculated using equation (1). tDR=Rp×Cd×{-ln(1-VTCD/VIN)}+tDR0 …(1) * ln is the natural logarithm. Rn : Delay resistance 2.0MΩ (TYP.) VTCD : Delay capacitance pin threshold voltage VIN/2 (TYP.) When tDR0 can be neglected, this can be calculated in a simple manner using equation (2). tDR=Rp×Cd×[-ln{1-(VIN/2)/VIN}]=Rp×Cd×0.693 …(2) Example: When the delay capacitance Cd is 0.68μF, the release delay time t DR is 2.0×106×0.68×10-6×0.693=942(ms). The detect delay tDF is calculated using equation (3). tDF=Rn×Cd×｛-ln(VTCD/VIN1)}+tDF0 …(3) * ln is the natural logarithm. Rn: Delay resistance 2.0MΩ (TYP.) VTCD: Delay capacitance pin threshold voltage VIN2/2 (TYP.) *VIN2 is the power input pin voltage at detection. VIN1: Power input pin voltage at release When VIN=VDF×1.1→VDF×0.9 and tDF0 can be neglected, this can be calculated in a simple manner using equation (4). tDF=Rn×Cd×{-ln(VIN2/2)/VIN1}=Rn×Cd×[-ln{(VDF×0.9×0.5)/(VDF×1.1)}]=Rn×Cd×0.894 …(4) For details of the detect delay time of equation (4), refer to Fig. 3. Example: When the delay capacitance Cd is 0.68μF at VIN=VDF×1.1→VDF×0.9, the detect delay time tDF is 2.0×106×0.68×10-6×0.894=1216(ms). VIN=VDF x 1.1V Power input pin voltage: VIN VIN2=VDF x 0.9V Release state (VIN1) Detect delay time: tDF Output pin voltage: VRESETB Detect state (VSS) Release state (VIN1) VIN1=VDF x 1.1V Delay capacitance pin threshold voltage Delay capacitance pin voltage: VCd/MRB VTCD=VIN2/2=0.9x0.5 Fig. 3: Detect delay time of equation (4) (timing chart) Delay time table Delay capacitance Cd (μF) Release delay time tDR (ms) (*1) TYP. MIN.to MAX. (*2) Detect delay time tDF (ms) (*1) TYP. MIN.to MAX. (*2) 12.7 to 22.0 0.01 13.9 10.4 to 17.7 17.9 0.022 30.5 22.9 to 38.9 39.3 28.0 to 48.4 0.047 65.1 48.9 to 83.0 84.0 59.8 to 103.3 127 to 220 0.1 139 104 to 177 179 0.22 305 229 to 389 393 280 to 484 0.47 651 489 to 830 840 598 to 1033 1 1386 1042 to 1766 1788 1274 to 2198 The release delay time values are the values calculated from equation (2). The detect delay time values are the values calculated from equation (4). (*1) Note that the delay time will vary depending on the actual capacitance value of the delay capacitance Cd. (*2) The values are calculated with consideration given to deviations in the delay resistance and delay capacitance pin threshold voltage. 15/27 XC6129 Series ■OPERATIONAL DESCRIPTION (Continued) The reset output pin signal can be forced into the detect state by inputting a voltage into the delay capacitance pin when in the release state. When the delay capacitance pin voltage input reaches an H→L level signal, the reset output pin outputs an H→L level signal. (RESETB：Active Low type) When the delay capacitance pin voltage input reaches an H→L level signal, the reset output pin outputs an L→H level signal. (RESET：Active High type) * During manual reset, there is no delay time even when a delay capacitance is connected. * When the delay capacitance pin voltage input reaches an L→H level signal in the detection state, the reset output pin outputs an L→H level signal. (RESETB：Active Low type) * When the delay capacitance pin voltage input reaches an L→H level signal in the detection state, the reset output pin outputs an H→L level signal. (RESET：Active High type) Under the detect condition, the condition will be kept even if the RESET switch turns on and off. In the case that either H level or L level is fed to the Cd/MRB pin without the RESET switch, the behavior of the XC6129 follows the timing chart in Fig. 4. L level is fed to the MRB pin under the detect condition, the RESET switch will be kept. H level is fed to the MRB pin under the detect condition, the RESET switch will be undefined. Even though the voltage at the VSEN pin changes from a higher voltage than the detect voltage to a lower voltage, as long as H level is fed to the MRB pin, the release condition is kept. If H level or L level is fed to the Cd/MRB pin forcibly, then even though Cd is connected to the pin, the XC6129 can’t have any delay time. Release voltage:VDF+VHYS Detect voltage:VDF Input Voltage:VIN（MIN.:0V,MAX.:6.0V) MRB High level voltage:VMRH Cd pin threshold voltage:VTCd MRB Low level voltage:VMRL Cd/MRB pin voltage:VCd/MRB (MIN.:VSS,MAX.:VIN) Release voltage:VDF+VHYS Detect voltage:VDF Undefined Output voltage:VRESETB (MIN.:VSS,MAX.:VIN(CMOS),Vpull(Nch open drain)) Fig. 4: Manual reset operation by the delay capacitance pin (Active Low product) Types B/D/F of the XC6129C series include an unstable operation prevention function. When the power input pin voltage is less than the minimum operation voltage, the output pin voltage due to unstable operation is limited to 0.4V (MAX.) or less. * Types A/C/E of the XC6129C series and each of the XC6129N series do not have an unstable operation prevention function. 16/27 XC6129 Series ■NOTE ON USE 1) Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is liable to malfunction should the ratings be exceeded. 2) The power input pin voltage may fall due to the flow through current during IC operation and the resistance component between the power supply and the power input pin. In the case of CMOS output, a drop in the power input pin voltage may occur in the same way due to the output current. When this happens, if the power input pin voltage drops below the minimum operating voltage, malfunctioning may occur. In addition, when the power input pin voltage is below the detect voltage, the output pin voltage may oscillate. Exercise caution in particular if a resistor is connected to the power input pin. 3) Note that large, sharp changes of the power input pin voltage may cause malfunctioning. 4) Power supply noise is sometimes a cause of malfunctioning. Sufficiently test using the actual device, such as inserting a capacitor between VIN and GND. 5) When an N-ch open drain output is used, the VRESETB voltage at detection and release is determined by the pull-up resistance connected to the output pin. Refer to the following when selecting the resistance value. At detection: VRESETB=Vpull/(1+Rpull/RON) Vpull : Voltage after pull-up RON(*1): ON resistance of N-ch driver M3 (calculated from VRESETB/IRBOUT1 based on electrical characteristics) Example: When VIN=2.0V(*2), RON=0.5/5.2×10-3=96Ω (MAX.). If it is desired to make VRESETB at detection 0.1V or less when Vpull is 3.0V, Rpull=(Vpull/VRESETB-1)×RON=(3/0.1-1)×96≒2.8kΩ Therefore, to make the output voltage at detection 0.1V or less under the above conditions, the pull-up resistance must be 2.8kΩ or higher. (*1) Note that RON becomes larger as VIN becomes smaller. (*2) For VIN in the calculation, use the lowest value of the input voltage range you will use. At release: VRESETB=Vpull/(1+Rpull/Roff) Vpull: Voltage after pull-up Roff: Resistance when N-ch driver M3 is OFF (calculated from VRESETB/ILEAK based on electrical characteristics) Example: When Vpull is 6.0V, Roff=6/(0.1×10-6)=60MΩ (MIN.). If it is desired to make VRESETB 5.99V or higher, Rpull=(Vpull/VRESETB-1)×Roff=(6/5.99-1)×60×106≒100kΩ Therefore, to make the output voltage at release 5.99V or higher under the above conditions, the pull-up resistance must be 100kΩ or less. 17/27 XC6129 Series ■NOTE ON USE (Continued) 6) If the discharge time of the delay capacitance Cd at detection is short and the delay capacitance Cd cannot be discharged to ground level, charging will take place at the next release operation with electric charge remaining in the delay capacitance Cd, and this may cause the release delay time to become noticeably short. 7) If the charging time of the delay capacitance Cd at release is short and the delay capacitance Cd cannot be charged to the V IN level, the delay capacitance Cd will discharge from less than the V IN level at the next detection operation, and this may cause the detect delay time to become noticeably short. 8) Even with a non-delay type, a delay time is added when a delay capacitance Cd is connected. 9) For a manual reset function, in case when the function is activated by feeding either MRB H level or MRB L level to Cd/MRB pin instead of using a reset switch, please note these phenomena below; ・The RESET output signal will be undefined when MRB H is fed to Cd/MRB pin under the detect condition. ・The RESET output signal will be undefined based on the voltage relationship between VSEN pin and Cd/MRB pin. 10) Torex places an importance on improving our products and their reliability. We request that users incorporate fail-safe designs and post-aging protection treatment when using Torex products in their systems. 18/27 XC6129 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (1) Detect, Release Voltage vs. Ambient Temperature XC6129 (V DF(T)=1.5V) XC6129 (V DF(T)=2.7V) 2.90 Detect, Release Voltage : VDFL, V DR (V) Detect, Release Voltage : VDFL, V DR (V) 1.600 1.575 VDR 1.550 1.525 1.500 VDF 1.475 VDR 2.85 2.80 2.75 2.70 VDF 1.450 2.65 -50 -25 0 25 50 75 100 -50 -25 Ambient Temperature : Ta (℃) 0 25 50 75 100 Ambient Temperature : Ta (℃) (2) Detect, Release Voltage vs. Input Voltage XC6129 (V DF(T)=5.5V) XC6129C (V DF(T)=1.5V) Type : A/C/E No Pull-up 6 5.80 OutPut Voltage : VRESETB (V) Detect, Release Voltage : VDFL, V DR (V) 5.85 5.75 VDR 5.70 5.65 5.60 5.55 5.50 ↓ : V DF側 ↑ : V DR側 5 4 Ta=-40℃ 3 Ta=25℃ Ta=85℃ 2 1 5.45 VDF 0 5.40 -50 -25 0 25 50 75 0 100 1 2 3 4 5 XC6129C (V DF(T)=2.7V) XC6129C (V DF(T)=5.5V) Type : A/C/E No Pull-up Type : A/C/E No Pull-up 6 6 ↓ : V DF側 ↑ : V DR側 5 Output Voltage : V RESETB (V) Output Voltage : V RESETB (V) 6 Input Voltage : V IN (V) Ambient Temperature : Ta (℃) 4 Ta=-40℃ 3 Ta=25℃ 2 Ta=85℃ 1 ↓ : V DF側 ↑ : V DR側 5 4 3 Ta=-40℃ 2 Ta=25℃ Ta=85℃ 1 0 0 0 1 2 3 Input Voltage : V IN (V) 4 5 6 0 1 2 3 4 5 6 Input Voltage : V IN (V) 19/27 XC6129 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (2) Detect, Release Voltage vs. Input Voltage (Continued) (3) Supply Current vs. Input Voltage XC6129 (V DF(T)=1.5V) 1.50 1.35 Ta=-40℃ Supply Current : ISS ( μ A) 1.20 Ta=25℃ 1.05 Ta=85℃ 0.90 0.75 0.60 0.45 0.30 0.15 0.00 0 1 2 3 4 5 6 4 5 6 Input Voltage: V IN (V) XC6129 (V DF(T)=2.7V) XC6129 (V DF(T)=5.5V) 1.50 1.50 1.35 1.35 Ta=-40℃ Ta=25℃ 1.05 Ta=85℃ 0.90 0.75 0.60 0.45 Ta=85℃ 0.90 0.75 0.60 0.45 0.30 0.15 0.15 0.00 Ta=25℃ 1.05 0.30 0.00 0 1 2 3 Input Voltage: V IN (V) 20/27 Ta=-40℃ 1.20 Supply Current : ISS ( μ A) Supply Current : ISS ( μ A) 1.20 4 5 6 0 1 2 3 Input Voltage: V IN (V) XC6129 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (4) Supply Current vs. Ambient Temperature XC6129 (V DF(T)=1.5V) XC6129 (V DF(T)=2.7V) V IN=V DF×0.9V (Detect) V IN=V DF×1.1V (Release) V IN=V DF×0.9V (Detect) V IN=V DF×1.1V (Release) 1.50 1.50 1.35 1.20 Detect 1.05 Release Supply Current : ISS (μ A) Supply Current : ISS (μ A) 1.35 0.90 0.75 0.60 0.45 1.20 Detect 1.05 Release 0.90 0.75 0.60 0.45 0.30 0.30 0.15 0.15 0.00 0.00 -50 -25 0 25 50 75 100 -50 -25 0 Ambient Temperature : Ta (℃) 25 50 75 100 Ambient Temperature : Ta (℃) (5) Output Current vs. Input Voltage XC6129x55A XC6129 (V DF(T)=5.5V) V IN=V DF×0.9V (Detect) V IN=V DF×1.1V (Release) V RESETB =0.5V (Nch) 25 1.50 Detect 1.05 Release Output Current : IRBOUT (mA) 1.20 0.90 0.75 0.60 0.45 20 Ta=-40℃ Ta=25℃ Ta=85℃ 15 10 5 0.30 0.15 0 0.00 -50 -25 0 25 50 75 0.0 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Voltage : VIN (V) Ambient Temperature : Ta (℃) XC6129C15A V RESETB =V IN-0.5V (Pch) 0 -1 Output Current : IRBOUT (mA) Supply Current : ISS (μ A) 1.35 -2 -3 -4 -5 -6 Ta=-40℃ -7 Ta=25℃ -8 Ta=85℃ -9 -10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Voltage : VIN (V) 21/27 XC6129 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (5) Output Current vs. Input Voltage (Continued) (6) Delay Resistance vs. Ambient Temperature XC6129x V IN=6.0V , V CD/MRB =0V (Type : A,B,E,F) 2.5 Delay Resistance : Rp (MΩ) 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 -50 -25 0 25 50 75 100 Ambient Temperature : Ta (℃) (7) Release Delay Time vs. Ambient Temperature XC6129x XC6129 20 2.4 19 Release Delay Time : DR t (ms) Delay Resistance : Rn (MΩ) V IN=V DF×0.9V , V CD/MRB =6.0V (Type : C,D,E,F) 2.5 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 V IN=V DF×0.9V → V DF×1.1V Cd=0.01μ F (tDR=13.9ms) 18 17 16 15 14 13 12 11 1.5 10 -50 -25 0 25 50 75 100 -50 -25 Ambient Temperature : Ta (℃) 0 25 50 75 100 Ambient Temperature : Ta (℃) (8) Detect Delay Time vs. Ambient Temperature XC6129 XC6129 V IN=V DF×0.9V → V DF×1.1V Cd=0.1μ F (tDR=139ms) 190 19 180 18 Detect Delay Time : DF t (ms) Release Delay Time : DR t (ms) 200 170 160 150 140 130 120 V IN=V DF×1.1V → V DF×0.9V Cd=0.01μ F (tDR=17.9ms) 20 17 16 15 14 13 12 11 110 10 100 -50 -25 0 25 50 Ambient Temperature : Ta (℃) 22/27 75 100 -50 -25 0 25 50 Ambient Temperature : Ta (℃) 75 100 XC6129 Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (8) Detect Delay Time vs. Ambient Temperature (Continued) (9) Cd pin MRB High Level Voltage vs. Ambient Temperature XC6129x XC6129 Detect Delay Time : DF t (ms) 190 180 170 160 150 140 130 120 110 MRB HighLevel Threshold Voltage : VMRH (V) V IN=V DF×1.1V → V DF×0.9V Cd=0.1μ F (tDR=179ms) 200 4.0 100 V IN=6.0V 3.0 2.0 V IN=4.0V 1.0 V IN=2.0V 0.0 -50 -25 0 25 50 75 100 -50 -25 Ambient Temperature : Ta (℃) 0 (10) Cd pin MRB High Level Voltage vs. Input Voltage 50 75 100 (11) Cd pin MRB Low Level Voltage vs. Ambient Temperature XC6129x XC6129 1.5 3.5 MRB LowLevel Threshold Voltage : V MRL (V) 4.0 MRB HighLevel Threshold Voltage : VMRH (V) 25 Ambient Temperature : Ta (℃) Ta=-40℃ Ta=25℃ 3.0 Ta=85℃ 2.5 2.0 1.5 1.0 0.5 0.0 V IN=6.0V 1.2 0.9 V IN=4.0V 0.6 0.3 V IN=2.0V 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Voltage : V IN (V) -50 -25 0 25 50 75 100 Ambient Temperature : Ta (℃) (12) Cd pin MRB Low Level Voltage vs. Input Voltage XC6129 MRB HighLevel Threshold Voltage : VMRH (V) 1.50 1.35 Ta=-40℃ 1.20 Ta=25℃ 1.05 Ta=85℃ 0.90 0.75 0.60 0.45 0.30 0.15 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Voltage : V IN (V) 23/27 XC6129 Series ■PACKAGING INFORMATION For the latest package information go to, www.torexsemi.com/technical-support/packages PACKAGE OUTLINE / LAND PATTERN THERMAL CHARACTERISTICS SSOT-24 SSOT-24 PKG SSOT-24 Power Dissipation USPN-4 USPN-4 PKG USPN-4 Power Dissipation USPQ-4B05 USPQ-4B05 PKG USPQ-4B05 Power Dissipation 24/27 XC6129 Series ■MARKING RULE ●SSOT-24 (with underline mark) Indicates mark (1) product series. Indicates the detect voltage range and output type. Mark (1)-1 (XC6129C*****-G is underline mark specification.) MARK OUTPUT DETECT VOLTAGE TYPE PRODUCT SERIES A B C D E F G J L A B C D E F G J L XC6129C15A**-G to XC6129C55A**-G XC6129C15B**-G to XC6129C55B**-G XC6129C15C**-G to XC6129C55C**-G XC6129C15D**-G to XC6129C55D**-G XC6129C15E**-G to XC6129C55E**-G XC6129C15F**-G to XC6129C55F**-G XC6129C15G**-G to XC6129C55G**-G XC6129C15J**-G to XC6129C55J**-G XC6129C15L**-G to XC6129C55L**-G XC6129C16A**-G to XC6129C54A**-G XC6129C16B**-G to XC6129C54B**-G XC6129C16C**-G to XC6129C54C**-G XC6129C16D**-G to XC6129C54D**-G XC6129C16E**-G to XC6129C54E**-G XC6129C16F**-G to XC6129C54F**-G XC6129C16G**-G to XC6129C54G**-G XC6129C16J**-G to XC6129C54J**-G XC6129C16L**-G to XC6129C54L**-G RANGE (V) ●USPQ-4B05 (with underline mark) 0 1 2 3 4 5 6 8 A C D E F H K L N R Mark (1)-2 ●SSOT-24 (with overline mark) MARK Odd number CMOS Even number (XC6129N*****-G is overline mark specification.) OUTPUT DETECT VOLTAGE TYPE PRODUCT SERIES 0 A XC6129N15A**-G ～ XC6129N55A**-G 2 C XC6129N15C**-G ～ XC6129N55C**-G 4 E XC6129N15E**-G ～ XC6129N55E**-G G XC6129N15G**-G ～ XC6129N55G**-G J XC6129N15J**-G ～ XC6129N55J**-G RANGE (V) Odd number 6 8 L XC6129N15L**-G ～ XC6129N55L**-G C A XC6129N16A**-G ～ XC6129N54A**-G E C XC6129N16C**-G ～ XC6129N54C**-G E XC6129N16E**-G ～ XC6129N54E**-G A ●USPQ-4B05 (with overline mark) N-ch H Even number L G XC6129N16G**-G ～ XC6129N54G**-G N J XC6129N16J**-G ～ XC6129N54J**-G R L XC6129N16L**-G ～ XC6129N54L**-G ② represents detect voltage MARK DETECT VOLTEGE(V) MARK DETECT VOLTEGE(V) MARK DETECT VOLTEGE(V) A 1.5 1.6 K 2.9 3.0 T 4.3 4.4 B 1.7 1.8 L 3.1 3.2 U 4.5 4.6 C 1.9 2.0 M 3.3 3.4 V 4.7 4.8 D 2.1 2.2 N 3.5 3.6 X 4.9 5.0 E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2 F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4 H 2.7 2.8 S 4.1 4.2 0 5.5 - ③,④ represents production lot number 01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ, B1～ZZ repeated. (G，I，J，O，Q，W excluded) * No character inversion used. 25/27 XC6129 Series ■MARKING RULE (Continued) ●USPN-4 ① represents detect voltage MARK OUTPUT K CMOS L N-ch PRODUCT SERIES XC6129C15A**-G ～ XC6129C55A**XC6129C*****-G G XC6129N*****-G ② represents detect voltage range and product series MARK DETECT VOLTAGE RANGE (V) TYPE PRODUCT SERIES 0 1 A XC6129*15A**-G ～ XC6129*55A**-G B(*) XC6129*15B**-G ～ XC6129*55B**-G 2 C XC6129*15C**-G ～ XC6129*55C**-G 3 4 Odd number XC6129*15D**-G ～ XC6129*55D**-G E XC6129*15E**-G ～ XC6129*55E**-G (*) 5 F 6 G XC6129*15F**-G ～ XC6129*55F**-G XC6129*15G**-G ～ XC6129*55G**-G 8 J XC6129*15J**-G ～ XC6129*55J**-G A L XC6129*15L**-G ～ XC6129*55L**-G C A XC6129*16A**-G ～ XC6129*54A**-G D B(*) XC6129*16B**-G ～ XC6129*54B**-G E C XC6129*16C**-G ～ XC6129*54C**-G D XC6129*16D**-G ～ XC6129*54D**-G E XC6129*16E**-G ～ XC6129*54E**-G (*) F H (*) D (*) Even number (*) K F L G XC6129*16F**-G ～ XC6129*54F**-G XC6129*16G**-G ～ XC6129*54G**-G N J XC6129*16J**-G ～ XC6129*54J**-G R L XC6129*16L**-G ～ XC6129*54L**-G Only supported with CMOS output. ③ represents detect voltage MARK DETECT VOLTEGE(V) MARK DETECT VOLTEGE(V) MARK A 1.5 1.6 K 2.9 3.0 T 4.3 4.4 B 1.7 1.8 L 3.1 3.2 U 4.5 4.6 C 1.9 2.0 M 3.3 3.4 V 4.7 4.8 D 2.1 2.2 N 3.5 3.6 X 4.9 5.0 E 2.3 2.4 P 3.7 3.8 Y 5.1 5.2 F 2.5 2.6 R 3.9 4.0 Z 5.3 5.4 H 2.7 2.8 S 4.1 4.2 0 5.5 - ④,⑤ represents production lot number 01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ, B1～ZZ repeated. (G，I，J，O，Q，W excluded) * No character inversion used. 26/27 DETECT VOLTEGE(V) XC6129 Series 1. The product and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. The information in this datasheet is intended to illustrate the operation and characteristics of our products. We neither make warranties or representations with respect to the accuracy or completeness of the information contained in this datasheet nor grant any license to any intellectual property rights of ours or any third party concerning with the information in this datasheet. 3. Applicable export control laws and regulations should be complied and the procedures required by such laws and regulations should also be followed, when the product or any information contained in this datasheet is exported. 4. The product is neither intended nor warranted for use in equipment of systems which require extremely high levels of quality and/or reliability and/or a malfunction or failure which may cause loss of human life, bodily injury, serious property damage including but not limited to devices or equipment used in 1) nuclear facilities, 2) aerospace industry, 3) medical facilities, 4) automobile industry and other transportation industry and 5) safety devices and safety equipment to control combustions and explosions. Do not use the product for the above use unless agreed by us in writing in advance. 5. Although we make continuous efforts to improve the quality and reliability of our products; nevertheless Semiconductors are likely to fail with a certain probability. So in order to prevent personal injury and/or property damage resulting from such failure, customers are required to incorporate adequate safety measures in their designs, such as system fail safes, redundancy and fire prevention features. 6. Our products are not designed to be Radiation-resistant. 7. Please use the product listed in this datasheet within the specified ranges. 8. We assume no responsibility for damage or loss due to abnormal use. 9. All rights reserved. No part of this datasheet may be copied or reproduced unless agreed by Torex Semiconductor Ltd in writing in advance. TOREX SEMICONDUCTOR LTD. 27/27