XC6132 Series
ETR02032-002
Delay capacitor adjustable voltage detectors with sense pin isolation,
surge voltage protection and HYS external adjustment
■GENERAL DESCRIPTION
The XC6132 series are ultra-small delay capacitor adjustable type voltage detectors that have high accuracy and sense pin
isolation. High accuracy and a low supply current are achieved by means of a CMOS process, a highly accurate reference
power supply, and laser trimming technology.
The sense pin is isolated from the power input pin to enable monitoring of the voltage of another power supply. Output can
be maintained in the detection state even if the voltage of the power supply that is monitored drops to 0V. The sense pin is
also suitable for detecting high voltages, and the detection and release voltage can be set as desired using external
resistors. An internal surge voltage protection circuit and an internal delay circuit are also provided.
By connecting a capacitor to the Cd/MRB pin, any release delay time and detect delay time can be set and the pin can also
be used as a manual reset pin.
The HYS external adjustment pin can be used to establish a sufficient hysteresis width.
■FEATURES
■APPLICATIONS
●Microcontroller reset and malfunction monitoring
●Battery voltage monitoring
●System power-on reset
●Power failure detection
Operating Ambient Temperature
Operating voltage range
Detect voltage range
Detect voltage accuracy
(Ta=25℃)
Detect voltage accuracy
(Ta=-40～125℃)
Temperature Characteristics
Hysteresis width
Adjustable Pin for Hysteresis Width
Low supply current
Manual reset function
Output type
Output logic
Delay capacitance pin
Sense pin
Packages
Environment friendly
: -40℃～+125℃
: 1.6V～6.0V
: 0.8V～2.0V
: ±18mV(VDF＜1.5V)
: ±1.2%(1.5V≦VDF≦2.0V)
: ±36mV(VDF＜1.5V)
: ±2.7%(1.5V≦VDF≦2.0V)
: ±50ppm/℃(TYP.)
: VDF×0.1％(TYP.)
: Yes
: 1.28μA(TYP.)
VIN=1.6V(At detection)
: 1.65μA(TYP.)
VIN=6.0V(At release)
: Yes (For details, refer to
FUNCTION CHART)
: CMOS or Nch open drain
: H level or L level at detection
: Release delay / detection delay
can be set in 5 time ratio options
(For details, refer to Selection Guide).
: Includes a surge voltage protection
function
: USP-6C,SOT-26
: EU RoHS compliant, Pb free
■TYPICAL APPLICATION CIRCUIT ■TYPICAL PERFORMANCE
CHARACTERISTICS
+B
VDD
VIN=3.3V
VSEN=0V→10V→0V
R2=100kΩ、R3=330kΩ
XC6132C10E
R3
R1
HYS
VIN
4.0
Rpull(*1)
3.5
RESET
RESETB
R2
GND
RESET
SW
Cd
Cd/MRB
VSS
Battery (+B) voltage monitoring: Detects high voltage
via R1/R2 resistance division.
A hysteresis width can be added as desired by
connecting R3 between the VSEN and HYS pins
Output Voltage : VRESET(V)
VSEN
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
8
9
10
Voltage Sense : VSEN(V)
OPEN
R1=330kΩ
R1=560kΩ
(For details, refer to OPERATIONAL DESCRIPTION).
1/30
XC6132 Series
■BLOCK DIAGRAMS
(1)XC6132C Series A/B/C/D/L type (RESET OUTPUT: CMOS/Active High)
VSEN
HYS
VIN
M3
RSEN=RA+RB+RC
M5
M7
+
RA
-
SURGE
VOLTAGE
PROTECT
BLOCK
Rp
VREF
M1
M4
RB
Rn
DELAY/
MRB
CONTROL
BLOCK
RESET
M6
Cd/MRB
RC
M2
VSS
* Diodes inside the circuit are an ESD protection diode and a parasitic diode.
(2)XC6132C Series E/F/H/K/M type (RESETB OUTPUT: CMOS/Active Low)
HYS
VSEN
VIN
M3
RSEN=RA+RB+RC
M5
M7
+
RA
M1
-
SURGE
VOLTAGE
PROTECT
BLOCK
Rp
VREF
M4
RB
Rn
DELAY/
MRB
CONTROL
BLOCK
RESETB
M6
Cd/MRB
RC
M2
VSS
* Diodes inside the circuit are an ESD protection diode and a parasitic diode.
2/30
XC6132
Series
■BLOCK DIAGRAMS (Continued)
(3)XC6132N Series A/B/C/D/L type (RESET OUTPUT: Nch open drain/Active High)
VSEN
HYS
VIN
M3
RSEN=RA+RB+RC
M5
Rp
+
RA
-
SURGE
VOLTAGE
PROTECT
BLOCK
VREF
M1
M4
RB
Rn
DELAY/
MRB
CONTROL
BLOCK
RESET
M6
Cd/MRB
RC
M2
VSS
* Diodes inside the circuit are an ESD protection diode and a parasitic diode.
(4)XC6132N Series E/F/H/K/M type (RESETB OUTPUT: Nch open drain/Active Low)
HYS
VSEN
VIN
M3
RSEN=RA+RB+RC
M5
Rp
+
RA
M1
-
SURGE
VOLTAGE
PROTECT
BLOCK
VREF
M4
RB
Rn
DELAY/
MRB
CONTROL
BLOCK
RESETB
M6
Cd/MRB
RC
M2
VSS
* Diodes inside the circuit are an ESD protection diode and a parasitic diode.
3/30
XC6132 Series
■PRODUCT CLASSIFICATION
●Ordering Information
XC6132①②③④⑤⑥-⑦(*1)
DESIGNATOR
ITEM
①
Output Configuration
②③
Detect Voltage
08～20
e.g. 1.0V → ②=1, ③=0
④
TYPE
A～M
Refer to Selection Guide
⑤⑥-⑦(*1)
Packages (Order Unit)
MR-G
SOT-26 (3,000pcs/Reel)
ER-G
USP-6C (3,000pcs/Reel)
(*1)
SYMBOL
DESCRIPTION
C
CMOS output
N
Nch open drain output
The “-G” suffix denotes Halogen and Antimony free as well as being fully EU RoHS compliant.
●Selection Guide
TYPE
RESET/RESETB OUTPUT
A
Active High(*2)
1：0
144kΩ：0Ω
0.1%(TYP)
B
↑
1：0.125
144kΩ：18kΩ
↑
C
↑
1：1
144kΩ：144kΩ
↑
D
↑
2：1
288kΩ：144kΩ
↑
L
↑
0.076：1
11kΩ：144kΩ
↑
E
Low(*2)
(*2)
Active
DELAY(Rp:Rn)
HYSTERESIS
1：0
144kΩ：0Ω
↑
F
↑
1：0.125
144kΩ：18kΩ
↑
H
↑
1：1
144kΩ：144kΩ
↑
K
↑
2：1
288kΩ：144kΩ
↑
M
↑
0.076：1
11kΩ：144kΩ
↑
”Active High” is H level when detection occurs, and “Active Low” is L level when detection occurs.
4/30
XC6132
Series
■PIN CONFIGURATION
●A/B/C/D/L type
Cd/MRB
6
VSEN
4
VSS
5
1 HYS
VSEN 6
VSS 5
2
1
VIN
2 RESET
Cd/MRB 4
3
3 VIN
RESET HYS
SOT-26
(TOP VIEW)
USP-6C
(BOTTOM VIEW)
●E/F/H/K/M type
Cd/MRB
6
VSS
5
VSEN
4
1 HYS
VSEN 6
VSS 5
2
1
VIN
2 RESETB
Cd/MRB 4
3
3 VIN
RESETB HYS
SOT-26
(TOP VIEW)
USP-6C
(BOTTOM VIEW)
*The dissipation pad for the USP-6C package should be solder-plated in reference mount pattern and metal masking so as to
enhance mounting strength and heat release. If the pad needs to be connected to other pins, it should be connected to VSS (No.
5) pin.
■PIN ASSIGNMENT
PIN NUMBER
PIN NAME
FUNCTION
VIN
Power Input
RESETB
Reset Output (Active Low)(*1)
RESET
Reset Output (Active High)(*1)
1
HYS
Adjustable Pin for Hysteresis Width
4
6
VSEN
Voltage Sense
5
5
VSS
Ground
6
4
Cd/MRB
Adjustable Pin for Delay Time/
Manual Reset
SOT-26
USP-6C
1
3
2
2
3
(*1)
Refer to the ④ in Ordering Information table.
5/30
XC6132 Series
■FUNCTION CHART
PIN
NAME
SIGNAL
STATUS
L
Forced Reset
H
For details, refer to " Function Chart "
OPEN
Normal Operation
Cd/MRB
●Function Chart
1.6V≦VIN≦6.0Ｖ
Transition of VRESETB Condition
Transition of VRESET Condition
TYPE:A/B/C/D/L
TYPE:E/F/H/K/M
VCd/MRB≦VMRL
Reset (High Level)(*2)
Reset (Low Level)( *1)
VCd/MRB≧VMRH
Release (Low Level)(*1)
Release (High Level)(*2)
VCd/MRB≦VMRL
Reset (High Level)( *2)
Reset (Low Level)( *1)
VCd/MRB≧VMRH
Undefined(*3)
Undefined(*3)
VSEN
VCd/MRB
VSEN≧VDF+VHYS
VSEN≦VDF
(*1)
CMOS output: VIN × 0.1 or less, N-ch open drain output, pull-up voltage × 0.1 or less.
CMOS output: VIN × 0.9 or higher, N-ch open drain output, pull-up voltage × 0.9 or higher.
(*3) For details,refer to page 17＜Manual reset function＞.
Note: If used with VIN＜VSEN, the surge protection circuit will activate. Use with VIN≧VSEN.
(*2)
■ABSOLUTE MAXIMUM RATINGS
Ta=25℃
PARAMETER
SYMBOL
RATINGS
Input Voltage
VIN
-0.3～+7.0
VSEN Pin Voltage
VSEN
-0.3～+VIN+0.3 or
HYS Pin Voltage
VHYS
-0.3～+7.0
Cd/MRB Pin Voltage
Output Voltage
VCd/MRB
XC6132C(*2)
XC6132N(*3)
VRESETB
VRESET
UNITS
V
+7.0(*1)
V
V
-0.3～+VIN+0.3 or
+7.0(*1)
-0.3～+VIN+0.3 or
+7.0(*1)
V
V
-0.3～+7.0
V
±5.0
mA
±50
mA
+50
mA
IHYS
+50
mA
ISENSURGE(+)
+2.5(*4)
mA
ISENSURGE(-)
-2.5(*5)
mA
VSEN Pin Surge Voltage(+)
VSENSURGE(+)
+7.0(*4)
V
VSEN Pin Surge Voltage(-)
VSENSURGE(-)
-0.9 (*5)
V
Cd/MRB Pin Current
Output Current
XC6132C
ICd/MRB
(*2)
XC6132N(*3)
HYS Pin Current
VSEN Pin Surge Current(+)
VSEN Pin Surge Current(-)
IRBOUT
IROUT
250
SOT-26
Power Dissipation
Pd
USP-6C
600 (40mm x 40mm Standard board) (*6)
100
mW
1250 (JEDEC board) (*6)
Operating Ambient Temperature
Topr
-40～+125
℃
Storage Temperature
Tstg
-55～+125
℃
* All voltages are described based on the VSS.
(*1) The maximum value should be either V +0.3 or +7.0 in the lowest.
IN
(*2) CMOS Output
(*3) N-ch Open Drain Output
(*4) Transient≦200ms.
(*5) Transient≦20ms.
(*6) This is a reference data taken by using the test board. Please see the power dissipation page for the mounting condition.
6/30
XC6132
Series
■ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Operating Voltage
VIN
VSEN Input Voltage
VSEN
Detect Voltage
Temperature
Characteristics
Hysteresis Width
CONDITIONS
VIN：Refer to V-1(*2)
VSEN=VDF×0.9V,
VIN：Refer to V-1(*2)
VSEN=VDF×1.1V,
VIN=6.0V
Release Delay
Resistance
(TYPE:A/B/C/E/F/H)
Release Delay
Resistance
Rp
(TYPE:D/K)
Release Delay
Resistance
(TYPE:L/M)
Detect Delay
Resistance
(TYPE:C/D/H/K/L/M)
Detect Delay
(TYPE:B/F)
Detect Delay
Time(*6)
6.0
1.6
6.0
V
0
6.0
0
6.0
V
-
±50
-
-
±50
-
-
VDF
VDF
×0.001 ×0.007
-
VDF
VDF
×0.001 ×0.01
-
E-1(*3)
-
E-2(*3)
1.36
-
E-3(*3)
-
1.65
-
E-5(*4)
VIN=6.0V,VSEN=6.0V
2.80
-
1.36
-
1.65
E-6(*4)
-
ppm/℃
V
4.22
µA
②
MΩ
③
kΩ
④
µs
⑤
E-4(*3)
-
3.25
①
4.97
-
VIN=6.0V,VSEN=6.0V,
VCd/MRB=0V
130
144
158
122
144
166
VIN=6.0V,VSEN=6.0V,
VCd/MRB=0V
259
288
317
245
288
331
VIN=6.0V,VSEN=6.0V,
VCd/MRB=0V
8.3
11
18.4
7.6
11
20.0
VIN=6.0V,VSEN=0V,
VCd/MRB=6.0V
130
144
158
122
144
166
VIN=6.0V,VSEN=0V,
VCd/MRB=6.0V
16.8
18
19.1
16.2
18
19.8
20
102
-
20
136
Rn
Resistance
Release Delay
Time(*5)
1.6
V
VHYS
RSEN
MAX.
VDF(T)
VDF(T) VDF(T)
VDF(T)
VDF(T)
VDF(T)
×0.988
×1.012 ×0.973
×1.027
VSEN=VDF×1.1V,
SENSE Resistance
MIN.
VDF(T)(*1)=1.5V～2.0V
∆VDF/
-40℃≦Topr≦125℃
(∆Topr・VDF)
Iss2
TYP.
UNITS CIRCUIT
MAX.
V
VIN=6.0V
Supply Current 2
TYP.
VDF(T)(*1)=0.8V～1.4V
VDF
Iss1
MIN.
VDF(T)
VDF(T) VDF(T)
VDF(T)
VDF(T)
VDF(T)
-18mV
+18mV -36mV
+36mV
VSEN=VDF×0.9V,
Supply Current 1
-40℃≦Ta≦125℃(*7)
Ta=25℃
tDR0
VIN=6.0V,
VSEN=VDF×0.9V→VDF×1.1V
-
tDF0
VIN=6.0V,
VSEN=VDF×1.1V→VDF×0.9V
-
20
82
-
20
116
Unless otherwise specified in measurement conditions, Cd/MRB pin and HYS pin are open.
(*1)
VDF(T): Nominal detect voltage
(*2)
For VIN conditions, refer to SPEC TABLE (p.10).
(*3)
Refer to SPEC TABLE (p.10).
(*4)
Refer to SPEC TABLE (p.11).
(*5)
RESETB product: Time from when the VSEN pin voltage reaches the release voltage until the reset output pin reaches 5.4V
(VIN×90%).
RESET product: Time from when the VSEN pin voltage reaches the release voltage until the reset output pin reaches 0.6V(VIN×10%)
Release voltage (VDR)=Detect voltage (VDF)+Hysteresis width (VHYS).
(*6)
RESETB product: Time from when the VSEN pin voltage reaches the detect voltage until the reset output pin reaches 0.6V(VIN×10%).
RESET product: Time from when the VSEN pin voltage reaches the detect voltage until the reset output pin reaches 5.4V(VIN×90%).
(*7)
The ambient temperature range (-40℃≦Ta≦125℃) is a design Value.
7/30
XC6132 Series
■ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
SYMBOL
Hysteresis Output
Current
IHYSOUT
IHYSLEAK
Hysteresis Output
Leakage Current
CONDITIONS
-40℃≦Ta≦125℃(*12)
Ta=25℃
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
VIN=1.6V,
VSEN=0V,VHYS=0.3V
1.9
3.4
-
0.7
3.4
-
VIN=6.0V,VSEN=6.0V,
VHYS=6.0V
-
0.01
0.1
-
0.01
1.0
VIN=1.6V(*9)
1.9
3.4
-
0.7
3.4
-
VIN=2.0V
4.2
6.0
-
2.0
6.0
-
VIN=3.0V
8.6
10.5
-
4.3
10.5
-
VIN=4.0V
12.7
14.1
-
6.2
14.1
-
VIN=5.0V
15.6
17.0
-
7.3
17.0
-
VIN=6.0V
17.8
19.2
-
8.1
19.2
-
VIN=1.6V(*10)
-
-1.2
-0.7
-
-1.2
-0.48
VIN=3.0V
-
-3.0
-2.5
-
-3.0
-1.1
VIN=6.0V
-
-4.9
-4.4
-
-4.9
-2.5
VIN=1.6V(*10)
1.9
3.4
-
0.7
3.4
-
VIN=2.0V(*11)
4.2
6.0
-
2.0
6.0
-
VIN=3.0V
8.6
10.5
-
4.3
10.5
-
VIN=4.0V
12.7
14.1
-
6.2
14.1
-
VIN=5.0V
15.6
17.0
-
7.3
17.0
-
VIN=6.0V
17.8
19.2
-
8.1
19.2
-
VIN=1.6V(*9)
-
-1.2
-0.7
-
-1.2
-0.48
VIN=3.0V
-
-3.0
-2.5
-
-3.0
-1.1
VIN=6.0V
-
-4.9
-4.4
-
-4.9
-2.5
VIN=6.0V,VSEN=6.0V,
Nch. VRESETB=6.0V
-
0.01
0.1
-
0.01
1.0
ILEAKP
VIN=6.0V,VSEN=0V,
Pch. VRESETB=0V
-
-0.01
-
-
-0.01
-
ILEAKN(*8)
VIN=6.0V,VSEN=0V,
Nch. VRESET=6.0V
-
0.01
0.1
-
0.01
1.0
VIN=6.0V,VSEN=6.0V,
Pch. VRESET=0V
-
-0.01
-
-
-0.01
-
UNITS
CIRCUIT
mA
⑥
µA
VSEN=VDF×0.9V,
Nch. VRESETB=0.3V
IRBOUTN
RESETB
Output Current
mA
VSEN=VDF×1.1V,
IRBOUTP
Pch.
VRESETB=VIN-0.3V
VSEN=VDF×1.1V,
Nch. VRESET=0.3V
IROUTN
RESET
Output Current
⑦
mA
VSEN=VDF×0.9V,
Pch. VRESET=VIN-0.3V
IROUTP
RESETB Output
Leakage Current
RESET Output
Leakage Current
ILEAKN(*8)
ILEAKP
µA
Unless otherwise specified in measurement conditions, Cd/MRB pin and HYS pin are open.
(*8)
Max. value is for XC6132N (Nch open drain).
(*9)
For 0.8V≦VDF(T)≦1.7V only.
(*10)
For 0.8V≦VDF(T)≦1.4V only.
(*11)
For 0.8V≦VDF(T)≦1.8V only.
(*12)
The ambient temperature range (-40℃≦Ta≦125℃) is a design Value.
8/30
XC6132
Series
■ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
SYMBOL
Cd Pin Sink Current
(TYPE:A/E)
ICd
Cd Pin Threshold
Voltage(Release)
VTCd1
VIN:Refer to V-1(*13),
VSEN=0V→VDF×1.1V
Cd Pin Threshold
Voltage(Detect)
VTCd2
VIN:Refer to V-1(*13),
VSEN=VDF×1.1V→0V
MRB High Level
Voltage
VMRH
VMRL
MRB Low Level
Voltage
tMRIN(*14)
MRB Minimum
Pulse Width
tMRIN(*15)
CONDITIONS
VIN=1.6V,
VCd/MRB=0.5V,
VSEN=0V
-40℃≦Ta≦125℃(*16)
Ta=25℃
MIN.
TYP.
0.92
1.2
MAX.
MIN.
TYP.
0.66
1.2
MAX.
UNITS CIRCUIT
mA
⑧
VIN×0.46 VIN×0.5 VIN×0.54 VIN×0.46 VIN×0.5 VIN×0.54
V
⑨
VIN:1.6V～6.0V,
VSEN= VDF×1.1V,
VIN>VSEN
VIN×0.55
V
VIN:1.6V～6.0V,
VSEN= VDF×1.1V,
VIN>VSEN
0
VIN:Refer to V-1(*13),
VSEN=VDF×1.1V,
Apply pulse from
VDF×1.1V to 0V to the
MRB pin.
VIN
VIN×0.55
VIN
⑩
5.0
-
VIN×0.18
0
-
5.0
VIN×0.18
-
V
-
µs
32.0
-
-
32.0
-
⑪
-
Unless otherwise specified in measurement conditions, Cd/MRB pin and HYS pin are open.
(*13)
For VIN conditions, refer to SPEC TABLE (p.10).
(*14)
Specification is guaranteed for types A/B/C/D/L/E/F/H/K/M of the CMOS output product and types E/F/H/K/M of the Nch open drain
product.
(*15)
Specification is guaranteed for types A/B/C/D/L of the Nch open drain output product.
(*16)
The ambient temperature range (-40℃≦Ta≦125℃) is a design Value.
9/30
XC6132 Series
■ELECTRICAL CHARACTERISTICS (SPEC TABLE)
Table of Characteristics by Voltage Setting
NOMINAL
DETECT
VOLTAGE(V)
VDF(T)
10/30
V-1
INPUT
VOLTAGE
(V)
0.8
1.6
0.9
↑
1.0
↑
1.1
↑
1.2
↑
1.3
↑
1.4
↑
1.5
VDF×1.1
1.6
↑
1.7
↑
1.8
↑
1.9
↑
2.0
↑
E-1
E-2
E-3
E-4
Ta=25℃
-40℃≦Ta≦125℃
Ta=25℃
-40℃≦Ta≦125℃
Supply Current 1(µA)
Supply Current 2(µA)
TYP.
MAX.
TYP.
MAX.
TYP.
MAX.
TYP.
MAX.
1.28
2.65
1.28
3.92
1.32
2.75
1.32
4.26
1.30
2.70
1.30
4.02
1.43
2.91
1.43
4.49
XC6132
Series
■ELECTRICAL CHARACTERISTICS (SPEC TABLE) (Continued)
Table of Characteristics by Voltage Setting
NOMINAL
DETECT
E-5(Ta=25℃)
E-6(-40℃≦Ta≦125℃)
VOLTAGE(V)
SENSE Resistance(MΩ)
SENSE Resistance(MΩ)
VDF(T)
MIN.
TYP.
MIN.
TYP.
0.8
7.5
20.7
5.9
20.7
0.9
8.6
23.3
6.8
23.3
1.0
10.0
26.1
7.6
26.1
1.1
11.0
28.6
8.5
28.6
1.2
12.2
31.3
9.3
31.3
1.3
13.4
33.9
10.2
33.9
1.4
14.5
36.6
11.1
36.6
1.5
15.7
38.6
11.9
38.6
1.6
16.9
39.2
12.8
39.2
1.7
18.1
39.8
13.6
39.8
1.8
19.3
40.4
14.5
40.4
1.9
19.0
40.2
14.3
40.2
2.0
18.6
39.9
14.0
39.9
11/30
XC6132 Series
■TEST CIRCUITS
CIRCUIT①
VIN
VSEN
RESET
RESETB
Cd/MRB
V
HYS
V
VSS
CIRCUIT②
A
VIN
VSEN
RESET
RESETB
Cd/MRB
HYS
VSS
CIRCUIT③
A
VIN
VSEN
RESET
RESETB
Cd/MRB
HYS
VSS
CIRCUIT④
VSEN
A
Cd/MRB
HYS
VIN
RESET
RESETB
VSS
*“RESET” is A/B/C/D/L type, and “RESETB” is E/F/H/K/M type.
12/30
XC6132
Series
■TEST CIRCUITS (Continued)
CIRCUIT⑤
VIN
VSEN
RESET
RESETB
Cd/MRB
Wave Form Measure Point
HYS
VSS
CIRCUIT⑥
VIN
VSEN
RESET
RESETB
Cd/MRB
A
HYS
VSS
CIRCUIT⑦
VIN
VSEN
RESET
RESETB
Cd/MRB
HYS
A
VSS
CIRCUIT⑧
VSEN
A
Cd/MRB
HYS
VIN
RESET
RESETB
VSS
*“RESET” is A/B/C/D/L type, and “RESETB” is E/F/H/K/M type.
13/30
XC6132 Series
■TEST CIRCUITS (Continued)
CIRCUIT⑨
VIN
VSEN
RESET
RESETB
Cd/MRB
V
HYS
V
V
VSS
CIRCUIT⑩
VSEN
VIN
RESET
RESETB
Cd/MRB
V
HYS
V
VSS
CIRCUIT⑪
VSEN
Cd/MRB
HYS
*“RESET” is A/B/C/D/L type, and “RESETB” is E/F/H/K/M type.
14/30
VIN
RESET
RESETB
VSS
Wave Form Measure Point
V
XC6132
Series
■OPERATIONAL DESCRIPTION
Fig. 1 shows a typical block diagram. Fig. 2 shows the timing chart of Fig. 1.
R2
VSEN
HYS
VIN
M3
RSEN=RA+RB+RC
M5
M7
+B
Rp
+
R1
RA
-
SURGE
VOLTAGE
PROTECT
BLOCK
VREF
M1
M4
RB
Rn
DELAY/
MRB
CONTROL
BLOCK
VDD Cd/MRB
RESET
SW
RC
Cd
RESETB
M6
M2
VSS
* The XC6132N series (N-ch open drain output) requires a resistor to pull up the output.
Fig. 1: Typical block diagram (Active Low product)
VSEN pin voltage:VSEN(MIN.:0V,MAX.:6.0V)
Release voltage:VDF+VHYS
Detect voltage:VDF
Cd/MRB pin voltage:VCd/MRB(MIN.:VSS,MAX.:VIN)
Cd pin threshold voltage:VTCd1,VTCd2
Output voltage:VRESETB(MIN.:VSS,MAX.:VIN)
ｔDF
①
②
ｔDR
③
④⑤
⑥
Fig. 2: Timing chart of Fig. 1(VIN=6.0V、Active Low product)
①In the initial state, a voltage that is sufficiently high (MAX.:6.0V) with respect to the release voltage is applied to the VSEN pin,
and the delay capacitance Cd is charged up to the power input pin voltage.
The VSEN pin voltage starts to fall, and during the time until it reaches the detect voltage (VSEN＞VDF),
VRESETB is High level (=VIN).
Note: If the pull-up resistor is connected to a power supply other than the power input pin VIN when using the Nch open drain
output (XC6132N), High level will be the voltage of the power supply to which the pull-up resistor is connected.
15/30
XC6132 Series
■OPERATIONAL DESCRIPTION (Continued)
②The VSEN pin voltage continues to drop, and when it reaches the detect voltage (VSEN=VDF), the Nch transistor for delay
capacitance discharge turns ON, and discharge of the delay capacitance Cd starts through the delay resistor Rn.
The time from VSEN=VDF until VRESETB reaches Low level is the detect delay time tDF (the detect time when the capacitor is not
connected to the Cd/MRB pin is tDF0). The delay capacitance Cd is discharged through the delay resistor Rn when it is above
the threshold voltage of VTCD2. When it is below the threshold voltage of VTCD2, the delay capacitance Cd is discharged faster
through the internal built-in low impedance switch.
③During the time that the VSEN pin voltage is below the detect voltage VDF, the delay capacitance Cd discharges to ground level.
The VSEN pin starts rising again, and during the time until it reaches the release voltage (VSENVDF), VRESETB holds High level.
The above operation description is for an Active Low detection product.
For an Active High product, reverse the logic of the reset pin.
In the factory shipping state, internal hysteresis is not added (VHYS =VDFx0.001V(TYP.)), so please add a hysteresis of 1% or
more with an external resistor. For the calculation method, refer to below. Also
please refer to “Notes on use 5＆6” on page 19.
Hysteresis can be added as desired by inserting a resistor between the node to monitor and VSEN pin, and between the VSEN pin
and HYS pin.
The calculation method for adding hysteresis by increasing only the release voltage and leaving the detect voltage unchanged
is given below.
For the circuit schematic, refer to Fig. 3: Hysteresis Augmentation Circuit 1.
VDR(H)=VDR(T)×{1+(RD/RE)}
Hysteresis width=VDR(H)-VDF(T)
Example 1: RD=200kΩ, RE=200kΩ, VDF(T)=1.000V, VDR(T)=1.001V.
VDR(H)=2.002V
Hysteresis width=2.002-1.000 =1.002V
The calculation method for detecting high voltage and adding hysteresis is shown below.
For the circuit schematic, refer to Fig. 4: Hysteresis Augmentation Circuit 2.
VDF(H)=VDF(T)×{1+(R1/R2)}
VDR(H)=VDR(T)×{1+(R1/R2)+(R1/R3)}
Hysteresis width=VDR(H)-VDF(H)
Example 2: R1=R3=500kΩ, R2=200kΩ, VDF(T)=2.000V, VDR(T)=2.002V.
VDF(H)=7.0V
VDR(H)=9.009V
Hysteresis width=9.009-7.0=2.009V
(Note 1) VDF(H) is the detect voltage after external adjustment.
(Note 2) VDR(H) is the release voltage after external adjustment.
(Note 3) VDR(T) is the release voltage.
(Note 4) VDF(T) is the detect voltage.
(Note 5) The R2 resistance is in parallel with the internal RSEN resistance, and thus to increase the accuracy of the detect
voltage and release voltage after external adjustment, select an R2 resistance that is sufficiently small with respect to the RSEN
resistance. For RSEN resistance values, refer to SPEC TABLE (p.11).
(Note 6) If high voltage is to be detected, divide the voltage with resistors R1 and R2 so that VSEN pin≦6V. The battery voltage
(+B) assumes up to 12V in this case.
VDD
+B
VDD
+B
RE
RD
HYS
R3
R1
VIN
HYS
Rpull(*1)
RESET
RESETB
RESET
SW
Cd
VSS
RESET
RESETB
R2
Cd/MRB
Fig. 3: Hysteresis Augmentation Circuit 1
16/30
Rpull(*1)
VSEN
VSEN
GND
VIN
GND
RESET
SW
Cd
Cd/MRB
VSS
Fig. 4: Hysteresis Augmentation Circuit 2
XC6132
Series
■OPERATIONAL DESCRIPTION (Continued)
The release delay time and detect delay time are determined by the delay resistors (Rp and Rn) and the delay capacitance Cd.
The ratio of the delay resistances (Rp and Rn) is selectable from 5 options. The delay time is adjustable using the combination
of delay resistance and delay capacitance value. (Refer to “Selection Guide”)
The release delay time (tDR) is calculated using Equation (1).
* ln is the natural logarithm.
tDR=Rp×Cd×{-ln(1-VTCd1/VIN)}+tDR0 …(1)
The delay capacitance pin threshold voltage is VTCd1=VIN/2(TYP.), and thus when
tDR0 can be neglected, the release delay time can be calculated simply using Equation (2).
tDR=Rp×Cd×[-ln{1-(VIN/2)/VIN}]=Rp×Cd×0.693 …(2)
The detect delay time (tDF) is calculated using Equation (3).
tDF=Rn×Cd×{-ln(VTCd2/VIN)}+tDF0 …(3)
* ln is the natural logarithm.
The delay capacitance pin threshold voltage is VTCd2=VIN/2 (TYP.), and thus when
tDF0 can be neglected, the detect delay can be calculated simply using Equation (4).
tDF=Rn×Cd×{-ln(VIN/2)/VIN}=Rn×Cd×0.693 …(4)
Example 3: When type A is selected (Rp：Rn=144kΩ：0Ω),the delay times are as follows:
If Cd is set to 0.1uF,
tDR=144×103×0.1×10-6×0.693=10ms
tDF is the detect delay time (tDFO) when the delay capacitance Cd is not connected.
Example 4: When type B is selected (Rp：Rn=144kΩ：18kΩ),the delay times are as follows:
If Cd is set to 0.1uF,
tDR=144×103×0.1×10-6×0.693=10ms
tDF =18×103×0.1×10-6×0.693=1.25ms
(Note 7) The release delay times tDR in Examples 3 and 4 are the values calculated from Equation (2).
(Note 8) The detect delay time tDF in Example 4 is the value calculated from Equation (4).
(Note 9) Note that the delay times will vary depending on the actual capacitance value of the delay capacitance Cd.
The Cd/MRB pin can also be used as a manual reset pin.
When the Cd and RESET switch are connected to the Cd/MRB pin (refer to Fig.1), and under the release condition, if the
RESET switch turns on, then the detect signal is generated at the RESET/RESETB pin forcibly.
For Active Low type (RESETB), under the release condition, if the RESET switch turns on, then the voltage at the RESETB pin
changes from H to L after the detect delay time.
For Active High type (RESET), under the release condition, if the RESET switch turns on, then the voltage at the RESET pin
changes from L to H after the detect delay time.
Under the detect condition, the condition will be kept even if the RESET switch turns on and off.
In the case that either H level or L level is fed to the Cd/MRB pin without the RESET switch, the behavior of the XC6132 follows
the timing chart in Fig. 5.
L level is fed to the MRB pin under the detect condition, the RESET switch will be kept.
H level is fed to the MRB pin under the detect condition, the RESET switch will be undefined.
Even though the voltage at the VSEN pin changes from a higher voltage than the detect voltage to a lower voltage, as long as H
level is fed to the MRB pin, the release condition is kept.
If H level or L level is fed to the Cd/MRB pin forcibly, then even though Cd is connected to the pin, the XC6132 can’t have any
delay time.
Release voltage:VDF+VHYS
Detect voltage:VDF
VSEN pin voltage:VSEN （MIN.:0V,MAX.:6.0V)
MRB High level voltage:VMRH
Cd pin threshold voltage:VTCd
MRB Low level voltage:VMRL
Cd/MRB pin voltage:VCd/MRB (MIN.:VSS ,MAX.:VIN)
Release voltage:VDF+VHYS
Detect voltage:VDF
Undefined
Output voltage:VRESE TB
(MIN.:VSS ,MAX.:VIN(CMOS),Vpu ll(Nch open drain))
Fig. 5: Manual reset operation using the Cd/MRB pin (VIN =6.0V, Active Low product)
17/30
XC6132 Series
■OPERATIONAL DESCRIPTION (Continued)
A surge voltage protection circuit is incorporated into the VSEN pin. A surge current of +2.5mA(≧200ms), -2.5mA(≧20ms) is
possible.
A positive surge current (ISENSURGE(+)) flows when M1 is turned ON by a SURGE VOLTAGE PROTECT BLOCK signal.
A negative surge current (ISENSURGE(-)) is made to flow by the M1 parasitic diode.
When a positive surge current flows and the surge voltage protection circuit activates, the VSEN pin voltage rises in proportion to
the VIN voltage and surge current, so adjust the ISEN current with an external resistor so that the VSEN pin voltage does not
exceed the operating voltage. Refer to Fig. 7.
※The VSEN voltage rise is most pronounced at high temperature.
Example 5： When VIN=3.3V and ISENSURGE(+)=2.5mA (MAX), the VSEN pin voltage from Fig. 7 is 5.6V. If the maximum battery
voltage (+B) pin voltage is 100V, a voltage of (100-5.6)=94.4V will be applied to the R1 resistor. To keep the surge current from
exceeding 2.5mA, use a resistance of R1=V/I=94.4/0.0025=37.8kΩ or above.
Example 6： When VIN = 3.3V and ISENSURGE(-) = -2.5mA(MAX), Vf of the parasitic diode M1 is -0.9V (MAX).
If the battery voltage (+B) maximum is -100V, the voltage applied to the R1 resistor will be {-100 - (-0.9)} = -99.1V.
To limit the surge current to -2.5mA, set the R1 resistance to R1 = V/I= -99.1/-0.0025 = 39.6kΩ or higher.
If the surge voltage on the positive side is different from the negative side, calculate the R1 resistance value using the side
where the voltage difference applied to the R1 resistor is greatest.
+B
Resistance for
hysteresis external
adjustment
R1
R2
HYS
R3
VSEN
RSEN=RA+RB+RC
RA
+
SURGE
VOLTAGE
PROTECT
BLOCK
RB
M1
-
VIN
↓ISENSURGE (+)
VREF
↑ISENSURGE(-) RC
M2
Surge voltage protect circuit
Fig. 6: Surge voltage protect circuit
Fig. 7: Example of VIN-VSEN characteristics
18/30
M3
XC6132
Series
■NOTES ON USE
1) Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is
liable to malfunction should the ratings be exceeded.
2) The power input pin voltage may fall due to the flow through current during IC operation and the resistance component
between the power supply and the power input pin.
In the case of CMOS output, a drop in the power input pin voltage may occur in the same way due to the output current. When
this happens, if the power input pin voltage drops below the minimum operating voltage, a malfunction may occur.
3) Note that large, sharp changes of the power input pin voltage may lead to malfunction.
4) Power supply noise is sometimes a cause of malfunction. Sufficiently test using the actual device, such as inserting a
capacitor between VIN and GND.
5) Internal hysteresis is not initially included with the product. Connect external resistors to the VSEN pin and HYS pin to add a
hysteresis of 1% or more. Note that if hysteresis is not added with external resistors, oscillation will occur when switching takes
place at the detect voltage or the release voltage.
6) There is a possibility that oscillation will occur if the resistances of the VSEN pin and HYS pin are high. Use a resistance of
1MΩ or less between the node to monitor and VSEN pin, and between the VSEN pin and HYS pin.
7) Exercise caution if VIN and VSEN are started in common, as the output will be undefined until VIN reaches the operating
voltage.
8) For a manual reset function, in case when the function is activated by feeding either MRB H level or MRB L level to Cd/MRB
pin instead of using a reset switch, please note these phenomena below;
・The RESET output signal will be undefined when MRB H is fed to Cd/MRB pin under the detect condition.
・The RESET output signal will be undefined based on the voltage relationship between VSEN pin and Cd/MRB pin.
9) When an N-ch open drain output is used, the VRESETB voltage at detection and release is determined by the pull-up resistance
connected to the output pin. Refer to the following when selecting the resistance value.
At detection:
VRESETB=Vpull/(1+Rpull/RON)
Vpull：Voltage after pull-up
RON(*1)：ON resistance of N-ch driver M6 (calculated from VRESETB/IRBOUTN based on electrical characteristics)
Example: When VIN=2.0V(*2), RON=0.3/4.2×10-3=71.4Ω (MAX.).
If it is desired to make VRESETB at detection 0.1V or less when Vpull is 3.0V,
Rpull={(Vpull/VRESETB)-1}×RON={(3/0.1)-1}×71.4≒2.1kΩ
Therefore, to make the output voltage at detection 0.1V or less under the above conditions, the pull-up resistance must be 2.1kΩ or higher.
(*1) Note that R
ON becomes larger as VIN becomes smaller.
(*2) For V in the calculation, use the lowest value of the input voltage range you will use.
IN
At release:
VRESETB=Vpull/(1+Rpull/Roff)
Vpull: Voltage after pull-up
Roff: Resistance when N-ch driver M6 is OFF (calculated from VRESETB/ILEAKN based on electrical characteristics)
Example: When Vpull is 6.0V, Roff=6/(0.1×10-6)=60MΩ (MIN.). If it is desired to make VRESETB 5.99V or higher,
Rpull={(Vpull/VRESETB)-1}×Roff={(6/5.99)-1}×60×106≒100kΩ
Therefore, to make the output voltage at release 5.99V or higher under the above conditions, the pull-up resistance must be
100kΩ or less.
10) If the discharge time of the delay capacitance Cd at detection is short and the delay capacitance Cd cannot be discharged to
ground level, charging will take place at the next release operation with electric charge remaining in the delay capacitance Cd,
and this may cause the release delay time to become noticeably short.
11) If the charging time of the delay capacitance Cd at release is short and the delay capacitance Cd cannot be charged to the
VIN level, the delay capacitance Cd will discharge from less than the VIN level at the next detection operation, and this may
cause the detect delay time to become noticeably short.
12) Torex places an importance on improving our products and their reliability. We request that users incorporate fail-safe designs
and post-aging protection treatment when using Torex products in their systems.
19/30
XC6132 Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(1) Detect, Release Voltage vs. Ambient Temperature
(3) Supply Current vs. Ambient Temperature
(4) Supply Current vs. Input Voltage
20/30
(2) Output Voltage vs Sense Voltage
XC6132
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Sense Resistance vs Ambient Temperature
(6) Delay Resistance vs Ambient Temperature
21/30
XC6132 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(7) Delay Time vs Ambient Temperature
(8) Hysteresis Output Current vs Ambient Temperature
(9) Hysteresis Output Current vs Input Voltage
(10) Hysteresis Output Leakage Current vs Ambient Temperature
(11) RESET Output Current vs Ambient Temperature
22/30
XC6132
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(11) RESET Output Current vs Ambient Temperature (Continued)
(12) RESET Output Current vs Input Voltage
(13) RESET Output Leakage Current vs Ambient Temperature
(14) Cd Pin Sink Current vs Ambient Temperature
(15) Cd Pin Sink Current vs Input Voltage
23/30
XC6132 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(16) Cd Pin Threshold Voltage vs Ambient Temperature
(17) MRB High Level Threshold Voltage vs Ambient Temperature
24/30
(18) MRB Low Level Threshold Voltage vs Ambient Temperature
XC6132
Series
■PACKAGING INFORMATION
●SOT-26 (unit:mm)
2.9±0.2
+0.1
0.4 -0.05
+0.1
0.4 -0.05
6
5
4
2
0.2MIN
3
+0.1
0.15 -0.05
(0.95)
1.1±0.1
(0.95)
1.3MAX
1
1.6
1234
+0.2
-0.1
2.8±0.2
0～0.1
●SOT-26 Reference Pattern Layout (unit:mm)
1.0
2.4
0.7
0.95
0.95
25/30
XC6132 Series
■PACKAGING INFORMATION (Continued)
●USP-6C (unit:mm)
●USP-6C Reference Pattern Layout (unit:mm)
26/30
●USP-6C Reference Metal Mask Design
XC6132
Series
■PACKAGING INFORMATION (Continued)
●SOT-26 Power Dissipation Toprmax+125℃ (40mm x 40mm Standard board)
Power dissipation data for the SOT-26 is shown in this page.
The value of power dissipation varies with the mount board conditions.
Please use this data as the reference data taken in the following condition.
1. Measurement Condition
Condition： Mount on a board
Ambient： Natural convection
Soldering： Lead (Pb) free
Board： Dimensions 40 x 40 mm
Copper (Cu) traces occupy 50% of the board
40.0
28.9
(1600 mm2 in one side)
area In top and back faces
Package heat-sink is tied to the copper traces
Material： Glass Epoxy (FR-4)
Thickness ： 1.6mm
2.5
Through-hole： 4 x 0.8 Diameter
Evaluation Board (Unit：mm)
2.Power Dissipation vs. Ambient Temperature
Board Mount (Tj max = 125℃ )
Ambient Temperature（℃）
Power Dissipation Pd（ mW ）
Thermal Resistance (℃/ W )
25
85
125
600
240
0
166.67
Pd vs. Ta
Power Dissipation Pd (mW)
700
600
500
400
300
200
100
0
25
45
65
85
105
125
Ambient Temperature Ta (℃)
27/30
XC6132 Series
■PACKAGING INFORMATION (Continued)
●USP-6C Power Dissipation (JEDEC board)
Power dissipation data for the USP-6C is shown in this page.
The value of power dissipation varies with the mount board conditions.
Please use this data as one of reference data taken in the described condition.
76.2
1. Measurement Condition (Reference data)
Condition : Mount on a board
Ambient : Natural convection
Soldering : Lead (Pb) free
Board : The board using 4 copper layer.
(76.2mm×114.3mm・・・ Area: about 8700mm2）
1st layer : No copper foil (Signal layer)
3rd layer : 70mm×70mm_Connected to heat-sink.
4th layer : No copper foil (Signal layer)
Material : Glass Epoxy （ FR-4）
114.3
2nd layer : 70mm×70mm_Connected to heat-sink.
Thickness : 1.6mm
8.74
Through-hole : φ0.2mm x 60pcs
Evaluation Board (Unit：mm)
2.Power Dissipation vs. Ambient temperature
Board Mount(Tjmax = 125℃)
AmbientTemperature（℃） PowerDissipation Pd（mW)
25
85
125
1250
500
0
80.00
Pd-Ta
1400
Power DissipationPd（mW）
θja(℃/W)
1200
1000
800
600
400
200
0
25
28/30
45
65
Ta（℃）
85
105
125
XC6132
Series
■MARKING RULE
SOT-26
6
5
2
③
⑤
②
④
①
③
1
⑤
②
4
④
①
USP-6C
3
1
2
5
4
3
① represents products series
MARK
X
6
PRODUCT SERIES
XC6132******-G
②,③ represents internal sequential number
01, …,09, 10, …, 99, A0, …, A9, B0, …, B9, …, Z9… repeated.
(G, I, J, O, Q, W excluded)
④,⑤ represents production lot number
01～09, 0A～0Z, 11～9Z, A1～A9, AA～AZ, B1～ZZ in order.
(G, I, J, O, Q, W excluded)
* No character inversion used.
29/30
XC6132 Series
1.
The product and product specifications contained herein are subject to change without notice to
improve performance characteristics. Consult us, or our representatives before use, to confirm that
the information in this datasheet is up to date.
2.
The information in this datasheet is intended to illustrate the operation and characteristics of our
products. We neither make warranties or representations with respect to the accuracy or
completeness of the information contained in this datasheet nor grant any license to any intellectual
property rights of ours or any third party concerning with the information in this datasheet.
3.
Applicable export control laws and regulations should be complied and the procedures required by
such laws and regulations should also be followed, when the product or any information contained in
this datasheet is exported.
4.
The product is neither intended nor warranted for use in equipment of systems which require
extremely high levels of quality and/or reliability and/or a malfunction or failure which may cause loss
of human life, bodily injury, serious property damage including but not limited to devices or equipment
used in 1) nuclear facilities, 2) aerospace industry, 3) medical facilities, 4) automobile industry and
other transportation industry and 5) safety devices and safety equipment to control combustions and
explosions. Do not use the product for the above use unless agreed by us in writing in advance.
5.
Although we make continuous efforts to improve the quality and reliability of our products;
nevertheless Semiconductors are likely to fail with a certain probability. So in order to prevent
personal injury and/or property damage resulting from such failure, customers are required to
incorporate adequate safety measures in their designs, such as system fail safes, redundancy and
fire prevention features.
6.
Our products are not designed to be Radiation-resistant.
7.
Please use the product listed in this datasheet within the specified ranges.
8.
We assume no responsibility for damage or loss due to abnormal use.
9.
All rights reserved. No part of this datasheet may be copied or reproduced unless agreed by Torex
Semiconductor Ltd in writing in advance.
TOREX SEMICONDUCTOR LTD.
30/30
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湘ICP备2023018690号
