XC61FN2712MR-G

XC61F Series ETR0202-007a Voltage Detectors, Delay Circuit Built-In ■GENERAL DESCRIPTION The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. A delay circuit is built-in to each detector. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N-ch open drain output configurations are available. Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible. ■APPLICATIONS ■FEATURES ●Microprocessor reset circuitry Highly Accurate : ± 2% Low Power Consumption : 1.0μA(TYP.)[ VIN=2.0V ] : 1.6V ~ 6.0V in 0.1V increments Detect Voltage Range Operating Voltage Range : 0.7V ~ 10.0V Detect Voltage Temperature Characteristics :±100ppm/℃(TYP.) Built-In Delay Circuit : ① 1ms ~ 50ms ② 50ms ~ 200ms ③ 80ms ~ 400ms Output Configuration : N-ch open drain output or CMOS Operating Ambient Temperature : -30℃～80℃ Packages : SOT-23 SOT-89 Environmentally Friendly : EU RoHS Compliant, Pb Free ●Memory battery back-up circuits ●Power-on reset circuits ●Power failure detection ●System battery life and charge voltage monitors ●Delay circuitry * No parts are available with an accuracy of ± 1% ■TYPICAL APPLICATION CIRCUITS ■TYPICAL PERFORMANCE CHARACTERISTICS N-ch open drain output Release Delay Time: tDR (ms) ●Release Delay Time vs. Ambient Temperature Ambient Temperature:Ta(℃) 1/14 XC61F Series ■PIN CONFIGURATION 1 ２ 3 VOUT VIN VSS SOT-89 (TOP VIEW) ■PIN ASSIGNMENT PIN NUMBER 2/14 PIN NAME FUNCTIONS VIN Supply Voltage Input 3 VSS Ground 1 VOUT Output SOT-23 SOT-89 3 2 2 1 XC61F Series ■PRODUCT CLASSIFICATION ●Ordering Information XC61F ①②③④⑤⑥⑦-⑧(*1) DESIGNATOR ITEM ① Output Configuration C N DESCRIPTION CMOS output N-ch open drain output e.g. 2.5V → ②2 , ③5 ②③ Detect Voltage 16 ~ 60 1 50ms ~ 200ms ④ Release Output Delay 4 80ms ~ 400ms 5 1ms ~ 50ms 2 Within ± 2.0% Detect Accuracy ⑤ ⑥⑦-⑧ (*1) SYMBOL (*1) Packages (Order Unit) e.g. 3.8V → ②3, ③8 MR SOT-23 (3,000 pcs /Reel) MR-G SOT-23 (3,000 pcs /Reel) PR SOT-89 (1,000 pcs /Reel) PR-G SOT-89 (1,000 pcs /Reel) The “-G” suffix denotes Halogen and Antimony free as well as being fully EU RoHS compliant. ■BLOCK DIAGRAMS (1) CMOS output (2) N-ch open drain output 3/14 XC61F Series ■ABSOLUTE MAXIMUM RATINGS Ta = 25℃ PARAMETER SYMBOL RATINGS UNITS Input Voltage VIN VSS-0.3~12.0 V Output Current IOUT CMOS Output Voltage N-ch open drain output SOT-23 Power Dissipation SOT-89 Operating Ambient Temperature Storage Temperature 50 VSS -0.3 ~ VIN + 0.3 VOUT Pd Topr Tstg mA V VSS -0.3 ~ 9 250 500 -30～+80 -40～+125 mW ℃ ℃ ■ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN. VDF(T) x 0.98 VDF x 0.02 0.7 1.0 3.0 5.0 6.0 7.0 VDF x 0.05 0.9 1.0 1.3 1.6 2.0 2.2 7.7 10.1 11.5 13.0 MAX. VDF(T) x 1.02 VDF x 0.08 2.6 3.0 3.4 3.8 4.2 10.0 - - -10.0 -2.0 VIN=VDF x 0.9V, VOUT=0V - -0.01 - VIN = 10.0V，VOUT=10.0V - 0.01 0.1 ∆VDF/ (∆Topr･VDF) -30℃≦Topr≦80℃ - ±100 VIN changes from 0.6V to 10V 50 80 1 - tDR Detect Voltage VDF Hysteresis Width VHYS Supply Current ISS Operating Voltage VIN Output Current IOUT CMOS Output (P-ch) N-ch Open Drain Output Detect Voltage Temperature Characteristics Leak Current Release Delay Time (VDR → VOUT inversion) CONDITIONS Ta = 25℃ VIN = 1.5V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VDF= 1.6V to 6.0V VIN = 1.0V VIN = 2.0V N-ch VDS =0.5V VIN = 3.0V VIN = 4.0V VIN = 5.0V P-ch VDS=2.1V VIN = 8.0V (CMOS Output) TYP. VDF(T) ILEAK UNITS CIRCUIT V ① V ① μA ② V ① ③ mA ④ μA ③ - ppm/℃ ① 200 400 50 ms ⑤ VDF (T): Setting detect voltage value Release Voltage: VDR = VDF + VHYS * Release Delay Time: 1ms to 50ms & 80ms to 400ms versions are also available. Note: The power consumption during power-start to output being stable (release operation) is 2μA greater than it is after that period (completion of release operation) because of delay circuit through current. 4/14 XC61F Series ■OPERATIONAL EXPLANATION ●CMOS output ① ② ③ ④ ⑤ ⑥ When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN, output (VOUT) will be equal to the input at VIN. Note that high impedance exists at VOUT with the N-ch open drain output configuration. If the pin is pulled up, VOUT will be equal to the pull up voltage. When VIN falls below VDF, VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also applies to N-ch open drain output configurations. When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable. Because the output pin is generally pulled up with configurations, output will be equal to pull up voltage. When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to VSS until VIN reaches the VDR level. Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit. Following transient delay time, VIN will be output at VOUT. Note that high impedance exists with the N-ch open drain output configuration and that voltage will be dependent on pull up. Notes: 1. The difference between VDR and VDF represents the hysteresis range. 2. Release delay time (tDR) represents the time it takes for VIN to appear at VOUT once the said voltage has exceeded the VDR level. ●Timing Chart Release Delay (t Time DLY) (tDR) 5/14 XC61F Series ■DIRECTIONS FOR USE ●Notes on Use 1. Please use this IC within the stated absolute maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is liable to malfunction should the ratings be exceeded. 2. When a resistor is connected between the VIN pin and the power supply with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no resistor be added. (refer to Oscillation Description (1) below) 3. When a resistor is connected between the VIN pin and the power supply with CMOS output configurations, irrespective of N-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (IOUT) does not exist. (refer to Oscillation Description (2) below) 4. If a resistor (RIN) must be used, then please use with as small a level of input impedance as possible in order to control the occurrences of oscillation as described above. Further, please ensure that RIN is less than 10kΩ and that CIN is more than 0.1μF, please test with the actual device. However, N-ch open drain output only. (Figure 1). 5. With a resistor (RIN) connected between the VIN pin and the power supply, the VIN pin voltage will be getting lower than the power supply voltage as a result of the IC's supply current flowing through the VIN pin. 6. Depending on circuit's operation, release delay time of this IC can be widely changed due to upper limits or lower limits of operational ambient temperature. 7. Torex places an importance on improving our products and its reliability. However, by any possibility, we would request user fail-safe design and post-aging treatment on system or equipment. ●Oscillation Description (1) Oscillation as a result of load current with the CMOS output configuration: When the voltage applied at power supply, release operations commence and the detector's output voltage increases. Load current (IOUT) will flow through RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located between the power supply and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Oscillation may occur with this " release - detect - release " repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Oscillation as a result of through current: Since the XC61F series are CMOS ICS, through current will flow when the IC's internal circuit switching operates (during release and detect operations). Consequently, oscillation is liable to occur during release voltage operations as a result of output current which is influenced by this through current (Figure 3). Since hysteresis exists during detect operations, oscillation is unlikely to occur. Power supply Figure 1. When using an input resistor 6/14 Power supply XC61F Series ■DIRECTIONS FOR USE (Continued) ●Oscillation Description (Continued) Power supply Power supply 7/14 XC61F Series ■TEST CIRCUITS 測定回路１ ●Circuit ① 測定回路２ ●Circuit ② 220KΩ* 測定回路３ ●Circuit ③ 測定回路４ ●Circuit ④ 測定回路５ ●Circuit ⑤ 220KΩ * CMOS出力品の場合は不要です。 *Not necessary with CMOS output products. 8/14 XC61F Series ■TYPICAL PERFORMANCE CHARACTERISTICS (4) N-ch Driver Output Current vs. VDS 9/14 XC61F Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (4) N-ch Driver Output Current vs. VDS (Continues) (5) N-ch Driver Output Current vs. Input Voltage (6) P-ch Driver Output Current vs. Input Voltage 10/14 Release Delay Time: tDR (ms) Release Delay Time: tDR (ms) Release Delay Time: tDR (ms) (7) Release Delay Time vs. Ambient Temperature XC61F Series ■TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Release Delay Time: tDR (ms) (8) Release Delay Time vs. Input Voltage 11/14 XC61F Series ■PACKAGING INFORMATION ●SOT-23 12/14 ●SOT-89 XC61F Series ■MARKING RULE ●SOT-23, SOT-89 ① represents integer of detect voltage and output configuration CMOS output (XC61FC series) MARK CONFIGURATION VOLTAGE (V) A CMOS 0.x B CMOS 1.x C CMOS 2.x D CMOS 3.x E CMOS 4.x F CMOS 5.x H CMOS 6.x 3 ① ② ③ ④ 1 ③ ① ④ 2 ② 1 2 3 N-ch open drain output (XC61FN series) MARK CONFIGURATION K N-ch L N-ch M N-ch N N-ch P N-ch R N-ch S N-ch VOLTAGE (V) 0.x 1.x 2.x 3.x 4.x 5.x 6.x ② represents decimal number of detect voltage MARK VOLTAGE (V) MARK 0 x.0 5 1 x.1 6 2 x.2 7 3 x.3 8 4 x.4 9 ③ represents delay time VOLTAGE (V) 5 6 7 VOLTAGE (V) x.5 x.6 x.7 x.8 x.9 DELAY TIME 50 ~ 200ms 80 ~ 400ms 1 ~ 50ms ④ represents assembly lot number (Based on internal standards) 13/14 XC61F Series 1. The product and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. The information in this datasheet is intended to illustrate the operation and characteristics of our products. We neither make warranties or representations with respect to the accuracy or completeness of the information contained in this datasheet nor grant any license to any intellectual property rights of ours or any third party concerning with the information in this datasheet. 3. Applicable export control laws and regulations should be complied and the procedures required by such laws and regulations should also be followed, when the product or any information contained in this datasheet is exported. 4. The product is neither intended nor warranted for use in equipment of systems which require extremely high levels of quality and/or reliability and/or a malfunction or failure which may cause loss of human life, bodily injury, serious property damage including but not limited to devices or equipment used in 1) nuclear facilities, 2) aerospace industry, 3) medical facilities, 4) automobile industry and other transportation industry and 5) safety devices and safety equipment to control combustions and explosions. Do not use the product for the above use unless agreed by us in writing in advance. 5. Although we make continuous efforts to improve the quality and reliability of our products; nevertheless Semiconductors are likely to fail with a certain probability. So in order to prevent personal injury and/or property damage resulting from such failure, customers are required to incorporate adequate safety measures in their designs, such as system fail safes, redundancy and fire prevention features. 6. Our products are not designed to be Radiation-resistant. 7. Please use the product listed in this datasheet within the specified ranges. 8. We assume no responsibility for damage or loss due to abnormal use. 9. All rights reserved. No part of this datasheet may be copied or reproduced unless agreed by Torex Semiconductor Ltd in writing in advance. TOREX SEMICONDUCTOR LTD. 14/14