6N138F

6N138,6N139 TOSHIBA Photocoupler IRED & Photo IC 6N138, 6N139 Current Loop Driver Low Input Current Line Receiver CMOS Logic Interface Unit: mm The TOSHIBA 6N138 and 6N139 consists of an infrared emitting diode coupled with a split-Darlington output configuration. A high speed Ired manufactured with an unique LPE junction, has the virtue of fast rise and fall time at low drive current. • Isolation voltage: 2500 Vrms (min) • Current transfer ratio : 6N138 − 300% (min) (IF=1.6mA) : 6N139 − 400% (min) (IF=0.5mA) • Switching time: 6N138 − tPHL = 10μs (max) − tPLH = 35μs (max) 6N139 − tPHL = 1μs (max) − tPLH = 7μs (max) • UL-recognized: UL 1577, File No.E67349 TOSHIBA Pin Configuration (top view) 1 8 2 7 11−10C4S Weight: 0.54 g (typ.) 1 : N.C. 2 : Anode 3 : Cathode 4 : N.C. 5 : Gnd 6 3 6 : Output 7 : Output Base 8 : VCC 5 4 Schematic VCC 8 2 IF ICC + IO VF 6 VO - 3 7 IB 5 GND VB Start of commercial production © 2019 Toshiba Electronic Devices & Storage Corporation 1 1988-02 2019-06-10 6N138,6N139 Absolute Maximum Ratings (*) (Ta = 0°C to + 70°C) Characteristics Forward current (Note 1) LED Pulse forward current Total pulse forward current Detector Reverse voltage Symbol Rating Unit IF 20 mA IFP (*1) 40 mA IFP (*2) 1 A VR 5 V Diode power dissipation (Note 2) PD 35 mW Output current (Note 3) IO 60 mA Emitter−base reverse voltage VEB 0.5 V Supply voltage VCC(*3) −0.5 to 18 V Output voltage VO(*3) −0.5 to 18 V PO 100 mW Topr 0 to 70 °C Tstg −55 to 125 °C Tsol 260 °C 2500 Vrms 3540 Vdc (Note 4) Output power dissipation Operating temperature range Storage temperature range Lead solder temperature (10s) (*4) Isolation voltage (60s, R.H.≤ 60%) BVS(**) Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc.). (*) JEDEC registered data (**) Not registered JEDEC (*1) 50 % duty cycle, 1 ms pulse width (*2) Pulse width 1 μs, 300 pps (*3) 6N138… −0.5 to 7 V (*4) 1.6 mm below seating plane © 2019 Toshiba Electronic Devices & Storage Corporation 2 2019-06-10 6N138,6N139 Electrical Characteristics Over Recommended Temperature (Ta = 0°C to 70°C, unless otherwise noted) Characteristics Current transfer ratio 6N139 CTR(*) (Note 5, 6) 6N138 6N139 Logic low output voltage VOL (Note 6) 6N138 Logic high output current 6N139 (Note 6) Test Condition Min (*5)Typ. Max IF = 0.5 mA, VO = 0.4 V VCC = 4.5 V 400 800  500 900  Symbol IOH(*) 6N138 Logic low supply current IF = 1.6 mA, VO = 0.4 V VCC = 4.5V 300 600  IF = 1.6 mA, IO = 6.4 mA VCC = 4.5 V  0.1 0.4 IF = 5 mA, IO = 15 mA VCC = 4.5 V  0.1 0.4 IF = 12 mA, IO = 24 mA VCC = 4.5 V  0.2 0.4 IF = 1.6 mA, IO = 4.8 mA VCC = 4.5 V  0.1 0.4 IF = 0 mA, VO = VCC = 18 V  0.05 100 IF = 0 mA, VO = VCC = 7 V  0.05 250 Unit % V μA (Note 6) ICCL IF = 1.6 mA, VO = Open VCC = 5 V  0.2  mA (Note 6) ICCH IF = 0 mA, VO = Open, VCC = 5 V  10  nA VF(*) IF = 1.6 mA, Ta = 25 °C  1.65 1.7 V BVR(*) IR = 10 μA, Ta = 25 °C 5   V  −1.9  mV / °C  60  pF Logic high supply current Input forward voltage Input reverse breakdown voltage Temperature coefficient of forward voltage ΔVF / ΔTa IF = 1.6 mA Input capacitance CIN f = 1 MHz, V F= 0 V Resistance (input−output) RI−O VI−O = 500 V R.H.≤ 60 % (Note 7),  1012  Ω Capacitance (input−output) CI−O f = 1 MHz, V = 0 V (Note 7)  0.6  pF (**) JEDEC registered data. (*5) All typical values are at Ta = 25 °C and VCC = 5 V, unless otherwise noted. © 2019 Toshiba Electronic Devices & Storage Corporation 3 2019-06-10 6N138,6N139 Switching Specifications (Ta=25°C, VCC=5V, unless otherwise specified) Characteristics Symbol Propagation delay time to logic low at output (Note 6, 8) 6N139 Propagation delay time to logic high at output (Note 6, 8) 6N139 Common mode transient immunity at logic high level output Common mode transient immunity at logic low level output tpHL(*) Test Circuit 1 6N138 tpLH(*) 1 6N138 Min Typ. Max IF = 0.5 mA, RL = 4.7 kΩ  5 25 IF = 12 mA, RL = 270 Ω  0.2 1 IF = 1.6 mA, RL = 2.2 kΩ  1 10 IF = 0.5 mA, RL = 4.7 kΩ  5 60 IF = 12 mA, RL = 270 Ω  1 7 IF = 1.6 mA, RL = 2.2 kΩ  4 35 Test Condition Unit µs µs CMH 2 IF = 0 mA, RL = 2.2 kΩ VCM = 400 Vp−p  500  V / µs CML 2 IF =1.6 mA RL = 2.2 kΩ VCM = 400 Vp−p  −500  V / µs (Note 9) (Note 9) (*)JEDEC registered data. (Note 1): Derate linearly above 50 °C free−air temperature at a rate of 0.4 mA / °C (Note 2): Derate linearly above 50 °C free−air temperature at a rate of 0.7 mW / °C (Note 3): Derate linearly above 25 °C free−air temperature at a rate of 0.7 mA / °C (Note 4): Derate linearly above 25 °C free−air temperature at a rate of 2.0 mW / °C (Note 5): DC CURRENT TRANSFER RATIO is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100 %. (Note 6): Pin 7 open. (Note 7): Device considered a two−terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7 and 8 shorted together. (Note 8): Use of a resistor between pin 5 and 7 will decrease gain and delay time. (Note 9): Common mode transient immunity in logic high level is the maximum tolerable (positive) dVCM / dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a logic high state (i.e. VO > 2.0 V). Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dVCM / dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e. VO < 0.8 V). © 2019 Toshiba Electronic Devices & Storage Corporation 4 2019-06-10 6N138,6N139 Test Circuit 1. IF Pulse gen. Zo = 50Ω tf = 5ns 0 IF 5V VO (Saturated Response) 1.5V 10% Duty cycle 1 / f < 100μs 1.5V VOL 10% 90% tr VO (NonSaturated Response) tpLH IF MonitorF 100Ω tpHL 1 8 2 7 3 6 VO 4 5 CL (*) +5V RL 5V 90% 10% tf (*)CL is approximately 15pF which includes probe and stray wiring capacitance. Test Circuit 2. VCM 10% 90% tr tf 0V A B 5V VO VFF Switch at A: IF = 0mA VOL 1 8 2 7 3 6 4 5 + VCM RCC +5V RL 400V IF tr, tf = 0.64μs VO － VO Pulse gen Switch at B: IF = 1.6mA © 2019 Toshiba Electronic Devices & Storage Corporation 5 2019-06-10 6N138,6N139 RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. Hardware, software and systems described in this document are collectively referred to as “Product”. • TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. • Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. 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