74HC4066D(BJ)

74HC4066D CMOS Digital Integrated Circuits Silicon Monolithic 74HC4066D 1. Functional Description • Quad Bilateral Switch 2. General The 74HC4066D is high-speed CMOS QUAD BILATERAL SWITCH fabricated with silicon gate C2MOS technology. It consists of four independent high speed switches capable of controlling either digital or analog signals while maintaining the CMOS low power dissipation. Control input(C) is provided to control the switch. The switch turns ON while the C input is High, and the switch turns OFF while low. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. Features (1) Low power dissipation: ICC = 1.0 µA (max) at VCC = 6.0 V, Ta = 25  (2) High noise immunity: VNIH = VNIL = 28 % VCC (min) (3) Low ON resistance: RON = 50 Ω (typ.) at VCC = 9.0 V, VI/O = VCC or GND (4) High degree of linearity: THD = 0.05 % (typ.) at VCC = 4.5 V 4. Packaging SOIC14 Start of commercial production ©2016 Toshiba Corporation 1 2016-10 2016-10-26 Rev.1.0 74HC4066D 5. Pin Assignment 6. Marking 7. Truth Table Control Switch Function H On L Off 8. System Diagram (per circuit) ©2016 Toshiba Corporation 2 2016-10-26 Rev.1.0 74HC4066D 9. Absolute Maximum Ratings (Note) Characteristics Symbol Note Rating Unit Supply voltage VCC -0.5 to 13 V Input voltage VIN -0.5 to VCC + 0.5 V Switch I/O voltage VI/O -0.5 to VCC + 0.5 V Input diode current IIK ±20 mA II/OK ±20 mA IT ±25 mA I/O diode current Switch through current VCC/ground current ICC ±50 mA Power dissipation PD 500 mW Storage temperature Tstg -65 to 150  Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 10. Operating Ranges (Note) Characteristics Rating Unit VCC 2.0 to 12 V Input voltage VIN 0 to VCC V Switch I/O voltage VI/O 0 to VCC V Operating temperature Topr -40 to 85  Input rise and fall times tr,tf 0 to 50 µs Supply voltage Note: Symbol Test Condition The operating ranges must be maintained to ensure the normal operation of the device. Unused control inputs must be tied to either VCC or GND. ©2016 Toshiba Corporation 3 2016-10-26 Rev.1.0 74HC4066D 11. Electrical Characteristics 11.1. DC Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics Symbol Test Condition VCC (V) Min Typ. Max Unit VIH  2.0 1.50   V 4.5 3.15   9.0 6.30   12.0 8.40   2.0   0.50 4.5   1.35 9.0   2.70 12.0   3.60 4.5  96 170 High-level input voltage Low-level input voltage VIL ON-resistance RON  VIN = VIH VI/O = VCC to GND II/O ≤ 1 mA VIN = VIH VI/O = VCC or GND II/O ≤ 1 mA  55 85  45 80 2.0  160  4.5  70 100 9.0  50 75 12.0  45 70 4.5  10  9.0  5  Ω Difference of ON-resistance between switches ∆RON 12.0  5  Input/Output leakage current (Switch OFF) IOFF VOS = VCC or GND VIS = GND to VCC VIN = VIL 12.0   ±0.1 µA Input/Output leakage current (Switch ON, output open) II/O VOS = VCC or GND VIN = VIH 12.0   ±0.1 µA Control input leakage current IIN VIN = VCC or GND 12.0   ±0.1 µA Quiescent supply current ICC VIN = VCC or GND 6.0   1.0 µA 9.0   4.0 12.0   8.0 ©2016 Toshiba Corporation VIN = VIH VI/O = VCC to GND II/O ≤ 1 mA 9.0 12.0 V 4 Ω 2016-10-26 Rev.1.0 74HC4066D 11.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 ) Characteristics Symbol Test Condition VCC (V) Min Max Unit VIH  2.0 1.50  V 4.5 3.15  High-level input voltage Low-level input voltage ON-resistance VIL RON  VIN = VIH VI/O = VCC to GND II/O ≤ 1 mA VIN = VIH VI/O = VCC or GND II/O ≤ 1 mA 9.0 6.30  12.0 8.40  2.0  0.50 4.5  1.35 9.0  2.70 12.0  3.60 4.5  200 9.0  100 12.0  90 2.0   4.5  130 9.0  95 V Ω 12.0  90 Input/Output leakage current (Switch OFF) IOFF VOS = VCC or GND VIS = GND to VCC VIN = VIL 12.0  ±1.0 µA Input/Output leakage current (Switch ON, output open) II/O VOS = VCC or GND VIN = VIH 12.0  ±1.0 µA Control input leakage current IIN VIN = VCC or GND 12.0  ±1.0 µA Quiescent supply current ICC VIN = VCC or GND 6.0  10.0 µA ©2016 Toshiba Corporation ICC 9.0 40.0 ICC 12.0 80.0 5 2016-10-26 Rev.1.0 74HC4066D 11.3. AC Characteristics (Unless otherwise specified, CL = 50 pF, Ta = 25 , Input: tr = tf = 6 ns) Characteristics Symbol Phase difference between input to output Output enable time Output disable time Note Test Condition ϕI/O tPZL, tPZH RL = 1 kΩ See 12. AC Test Circuit, Figure 1 tPLZ, tPHZ RL = 1 kΩ See 12. AC Test Circuit, Figure 1 VCC (V) Min Typ. Max Unit 2.0  10 50 ns 4.5  4 10 9.0  3 8 12.0  3 7 2.0  18 100 4.5  8 20 9.0  6 12 12.0  6 12 2.0  20 115 4.5  10 23 9.0  8 20 12.0  8 12 ns ns Control input capacitance CIN  3  pF Switch terminal capacitance COS See 12. AC Test Circuit, Figure 2  6  pF Feedthrough capacitance CIOS See 12. AC Test Circuit, Figure 2  0.5  pF Power dissipation capacitance CPD (Note 1) See 12. AC Test Circuit, Figure 2  5  pF Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation. ICC(opr) = CPD × VCC × fIN + ICC/4 (per bit) 11.4. AC Characteristics (Unless otherwise specified, CL = 50 pF, Ta = -40 to 85 , Input: tr = tf = 6 ns) Characteristics Phase difference between input to output Output enable time Output disable time ©2016 Toshiba Corporation Symbol Test Condition ϕI/O tPZL,tPZH RL = 1 kΩ See 12. AC Test Circuit, Figure 1 tPLZ,tPHZ RL = 1 kΩ See 12. AC Test Circuit, Figure 1 6 VCC (V) Min Max Unit 2.0  65 ns 4.5  13 9.0  10 12.0  9 2.0  125 4.5  25 9.0  22 12.0  18 2.0  145 4.5  29 9.0  25 12.0  22 ns ns 2016-10-26 Rev.1.0 74HC4066D 11.5. Analog Switch Characteristics (Ta = 25 ) (Note) Characteristics Sine Wave Distortion Maximum frequency response (switch ON) Feed through attenuation (switch OFF) Crosstalk (control input to signal output) Crosstalk (between any switches) Note: Symbol THD Test Condition VCC (V) Typ. Unit VIN = 4.5 Vp-p 4.5 0.05 % VIN = 9.0 Vp-p 9.0 0.04 4.5 200 9.0 200 VIN is centered at (VCC/2). Adjust input for 0dBm. RL = 600 Ω, CL = 50 pF, fIN = 1 MHz, sine wave See 12. AC Test Circuit, Figure 4 4.5 -60 9.0 -60 RL = 600 Ω, CL = 50 pF, fIN = 1 MHz, square wave (tr = tf = 6 ns) See 12. AC Test Circuit, Figure 5 4.5 60 9.0 100 VIN is centered at (VCC/2). Adjust input for 0dBm. RL = 600 Ω, CL = 50 pF, fIN = 1 MHz, sine wave See 12. AC Test Circuit, Figure 6 4.5 -60 9.0 -60 RL = 10 kΩ, CL = 50 pF, fIN = 1 kHz fMAX(I/O) VIN is centered at (VCC/2). Adjust input for 0dBm. Increase fIN frequency until dB meter reads -3dB. RL = 50 Ω, CL = 10 pF, fIN = 1 MHz, sine wave See 12. AC Test Circuit, Figure 3 FTH Xtalk Xtalk MHz dB mV dB These characteristics are determined by design of devices. ©2016 Toshiba Corporation 7 2016-10-26 Rev.1.0 74HC4066D 12. AC Test Circuit Figure 1 tPLZ, tPHZ, tPZL, tPZH Figure 2 CIOS, COS Figure 3 Frequency Response (switch on) ©2016 Toshiba Corporation 8 2016-10-26 Rev.1.0 74HC4066D Figure 4 Feedthrough Figure 5 Cross Talk (control input to output signal) Figure 6 Cross Talk (between any two switches) ©2016 Toshiba Corporation 9 2016-10-26 Rev.1.0 74HC4066D Package Dimensions Unit: mm Weight: 0.13 g (typ.) Package Name(s) Nickname: SOIC14 ©2016 Toshiba Corporation 10 2016-10-26 Rev.1.0 74HC4066D RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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