74HC573D(BJ,K)

74HC573D CMOS Digital Integrated Circuits Silicon Monolithic 74HC573D 1. Functional Description • Octal D-Type Latch with 3-State Outputs 2. General The 74HC573D is a high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. These 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE). When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. Features (1) High speed: tpd = 13 ns (typ.) at VCC = 6.0 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V 4. Packaging SOIC20 Start of commercial production ©2016 Toshiba Corporation 1 2016-03 2016-05-24 Rev.2.0 74HC573D 5. Pin Assignment 6. Marking 7. IEC Logic Symbol ©2016 Toshiba Corporation 2 2016-05-24 Rev.2.0 74HC573D 8. Truth Table INPUT OE INPUT LE INPUT D OUTPUT Q H X X Z L L X Qn L H L L L H H H X: Z: Qn: Don't Care High Impedance Q outputs are latched at the time when the LE input is taken to low logic level. 9. System Diagram ©2016 Toshiba Corporation 3 2016-05-24 Rev.2.0 74HC573D 10. Absolute Maximum Ratings (Note) Characteristics Symbol Note Rating Unit Supply voltage VCC -0.5 to 7.0 V Input voltage VIN -0.5 to VCC + 0.5 V VOUT -0.5 to VCC + 0.5 V IIK ±20 mA Output diode current IOK ±20 mA Output current IOUT ±35 mA VCC/ground current ICC Power dissipation PD Storage temperature Tstg Output voltage Input diode current (Note 1) ±75 mA 500 mW -65 to 150  Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: PD derates linearly with -8 mW/ above 85 11. Operating Ranges (Note) Characteristics Supply voltage Input voltage Symbol Test Condition Rating Unit VCC 2.0 to 6.0 V VIN 0 to VCC V Output voltage VOUT 0 to VCC V Operating temperature Topr Input rise and fall times tr,tf Note: -40 to 85  VCC = 2.0 V 0 to 1000 ns VCC = 4.5 V 0 to 500 VCC = 6.0 V 0 to 400 The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. ©2016 Toshiba Corporation 4 2016-05-24 Rev.2.0 74HC573D 12. Electrical Characteristics 12.1. DC Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Symbol Test Condition VIH  VIL VOH VOL  VIN = VIH or VIL Min Typ. Max Unit 2.0 1.50   V 4.5 3.15   V 6.0 4.20   V 2.0   0.50 V 4.5   1.35 V 6.0   1.80 V 2.0 1.9 2.0  V 4.5 4.4 4.5  6.0 5.9 6.0  IOH = -6 mA 4.5 4.18 4.31  IOH = -7.8 mA 6.0 5.68 5.80  IOL = 20 µA 2.0  0.0 0.1 4.5  0.0 0.1 IOH = -20 µA VIN = VIH or VIL VCC (V) 6.0  0.0 0.1 IOL = 6 mA 4.5  0.17 0.26 IOL = 7.8 mA V 6.0  0.18 0.26 V IOZ VIN = VIH or VIL VOUT = VCC or GND 6.0   ±0.5 µA Input leakage current IIN VIN = VCC or GND 6.0   ±0.1 µA Quiescent supply current ICC VIN = VCC or GND IO = 0 A 6.0   4.0 µA 3-state output OFF-state leakage current 12.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Symbol VIH VIL VOH VOL Test Condition VCC (V) Min Max Unit 2.0 1.50  V 4.5 3.15  6.0 4.20  V 2.0  0.50 V 4.5  1.35 6.0  1.80 V 2.0 1.9  V 4.5 4.4  6.0 5.9  IOH = -6 mA 4.5 4.13  IOH = -7.8 mA 6.0 5.63  IOL = 20 µA 2.0  0.1 4.5  0.1   VIN = VIH or VIL VIN = VIH or VIL IOH = -20 µA 6.0  0.1 IOL = 6 mA 4.5  0.33 IOL = 7.8 mA V 6.0  0.33 V IOZ VIN = VIH or VIL VOUT = VCC or GND 6.0  ±5.0 µA Input leakage current IIN VIN = VCC or GND 6.0  ±1.0 µA Quiescent supply current ICC VIN = VCC or GND IO = 0 A 6.0  40.0 µA 3-state output OFF-state leakage current ©2016 Toshiba Corporation 5 2016-05-24 Rev.2.0 74HC573D 12.3. Timing Requirements (Unless otherwise specified, Ta = 25 , Input: tr = tf = 6 ns) Characteristics Symbol Test Condition VCC (V) Limit Unit Minimum pulse width (LE) tw(H)  2.0 75 ns 4.5 15 6.0 13 Minimum setup time tS 2.0 50 4.5 10 6.0 9 2.0 5 4.5 5 6.0 5 Minimum hold time  th  ns ns 12.4. Timing Requirements (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 6 ns) Characteristics Minimum pulse width (LE) Minimum setup time Minimum hold time ©2016 Toshiba Corporation Symbol Test Condition VCC (V) Limit Unit tw(H)  2.0 95 ns 4.5 19 6.0 16 2.0 65 4.5 13 6.0 11 2.0 5 4.5 5 6.0 5 tS  th  6 ns ns 2016-05-24 Rev.2.0 74HC573D 12.5. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 6 ns) Characteristics Output transition time Symbol Note Test Condition VCC (V) CL (pF) Min Typ. Max Unit  2.0 50  20 60 ns  6 12 tTLH,tTHL 4.5 6.0 Propagation delay time (LE-Q) tPLH,tPHL   5 10  50 115 4.5  15 23 6.0  13 20  60 155  20 31  17 26  42 110 4.5  14 22 6.0  12 19  57 150  19 30  16 26  55 140 4.5  17 28 6.0  14 24  66 180  22 36  19 31  40 125 4.5  17 25 6.0  15 21 2.0 2.0 50 150 4.5 6.0 Propagation delay time (D-Q) tPLH,tPHL  2.0 2.0 50 150 4.5 6.0 Output enable time tPZL,tPZH RL = 1 kΩ 2.0 2.0 50 150 4.5 6.0 Output disable time Input capacitance tPLZ,tPHZ RL = 1 kΩ 2.0 50 ns ns ns ns ns ns ns CIN   5 10 pF Output capacitance COUT   10  pF Power dissipation capacitance CPD   51  pF (Note 1) Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation. ICC(opr) = CPD × VCC × fIN + ICC/8 (per latch) And the total CPD when n pcs. of latch operate can be gained by the following equation: CPD (total) = 33 + 18 × n ©2016 Toshiba Corporation 7 2016-05-24 Rev.2.0 74HC573D 12.6. AC Characteristics (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 6 ns) Characteristics Output transition time Symbol Note Test Condition VCC (V) CL (pF) Min Max Unit  2.0 50  75 ns  15 tTLH,tTHL 4.5 6.0 Propagation delay time (LE-Q) tPLH,tPHL   13  145 4.5  29 6.0  25  195  39 2.0 2.0 50 150 4.5 6.0 Propagation delay time (D-Q) tPLH,tPHL   33  140 4.5  28 6.0  24  190  38 2.0 2.0 50 150 4.5 6.0 Output enable time tPZL,tPZH RL = 1 kΩ  32  175 4.5  35 6.0  30  225  45 2.0 2.0 50 150 4.5 6.0 Output disable time Input capacitance ©2016 Toshiba Corporation tPLZ,tPHZ RL = 1 kΩ CIN  8  38  155 4.5  31 6.0  26  10 2.0 50 ns ns ns ns ns ns ns pF 2016-05-24 Rev.2.0 74HC573D Package Dimensions Unit: mm Weight: 0.51 g (typ.) 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