74VHC163FT(BJ)

74VHC161FT,74VHC163FT CMOS Digital Integrated Circuits Silicon Monolithic 74VHC161FT,74VHC163FT 1. Functional Description • Synchronous Presettable 4-Bit Counter 74VHC161FT: Binary , Asynchronous Clear 74VHC163FT: Binary , Synchronous Clear 2. General The 74VHC161FT and 74VHC163FT are advanced high speed CMOS SYNCHRONOUS PRESETTABLE 4 BIT BINARY COUNTERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The CK input is active on the rising edge. Both LOAD and CLR inputs are active on low logic level. Presetting of each IC's is synchronous to the rising edge of CK. The clear function of the 74VHC163FT is synchronous to CK, while the 74VHC161FT are cleared asynchronously. Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages 3. Features (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: Topr = -40 to 125  (3) High speed: fMAX = 185 MHz (typ.) at VCC = 5 V (4) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (5) High noise immunity: VNIH = VNIL = 28 % VCC (min) (6) Power-down protection is provided on all inputs. (7) Balanced propagation delays: tPLH ≈ tPHL (8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V (9) Low noise: VOLP=0.8 V (max) (10) Pin and function compatible with 74 series (AC/HC/AHC/LV etc.) 161 or 163 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. Start of commercial production ©2016 Toshiba Corporation 1 2014-12 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 4. Packaging TSSOP16B 5. Pin Assignment 6. Marking 74VHC161FT ©2016 Toshiba Corporation 74VHC163FT 2 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 7. IEC Logic Symbol 74VHC161FT 74VHC163FT 8. Truth Table X: Don't care A, B, C, D: Logic level of data inputs Carry: Carry = ENTQAQBQCQD ©2016 Toshiba Corporation 3 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 9. Timing Diagrams ©2016 Toshiba Corporation 4 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 10. System Diagram ©2016 Toshiba Corporation 5 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 11. Absolute Maximum Ratings (Note) Characteristics Symbol Note Rating Unit Supply voltage VCC -0.5 to 7.0 V Input voltage VIN -0.5 to 7.0 V VOUT -0.5 to VCC + 0.5 V IIK -20 mA Output diode current IOK ±20 mA Output current IOUT ±25 mA VCC/ground current ICC Power dissipation PD Storage temperature Tstg Output voltage Input diode current (Note 1) ±50 mA 180 mW -65 to 150  Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: 180 mW in the range of Ta = -40 to 85 . From Ta = 85 to 125  a derating factor of -3.25 mW/ shall be applied until 50 mW. 12. Operating Ranges (Note) Characteristics Supply voltage Input voltage Output voltage Symbol Rating Unit 2.0 to 5.5 V VIN 0 to 5.5 V VOUT 0 to VCC V VCC Operating temperature Topr Input rise and fall times dt/dv Note: Test Condition -40 to 125  VCC = 3.3 ± 0.3 V 0 to 100 ns/V VCC = 5 ± 0.5 V 0 to 20 The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. ©2016 Toshiba Corporation 6 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 13. Electrical Characteristics 13.1. DC Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics Symbol Test Condition High-level input voltage VIH  Low-level input voltage VIL  High-level output voltage VOH Low-level output voltage VOL VIN = VIH or VIL Min Typ. Max Unit 2.0 1.50   V 3.0 to 5.5 VCC × 0.7   2.0   0.50 3.0 to 5.5   VCC × 0.3 2.0 1.9 2.0  3.0 2.9 3.0  4.5 4.4 4.5  IOH = -4 mA 3.0 2.58   IOH = -8 mA 4.5 3.94   IOL = 50 µA 2.0  0.0 0.1 3.0  0.0 0.1 4.5  0.0 0.1 3.0   0.36 IOH = -50 µA VIN = VIH or VIL VCC (V) IOL = 4 mA IOL = 8 mA V V V 4.5   0.36 Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5   ±0.1 µA Quiescent supply current ICC VIN = VCC or GND 5.5   4.0 µA Min Max Unit V 13.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Symbol VIH VIL VOH VOL Test Condition VCC (V)   VIN = VIH or VIL IOH = -50 µA VIN = VIH or VIL 2.0 1.50  3.0 to 5.5 VCC × 0.7  2.0  0.50 3.0 to 5.5  VCC × 0.3 2.0 1.9  3.0 2.9  4.5 4.4  IOH = -4 mA 3.0 2.48  IOH = -8 mA 4.5 3.80  IOL = 50 µA 2.0  0.1 3.0  0.1 4.5  0.1 IOL = 4 mA 3.0  0.44 IOL = 8 mA 4.5  0.44 V V V Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5  ±1.0 µA Quiescent supply current ICC VIN = VCC or GND 5.5  40.0 µA ©2016 Toshiba Corporation 7 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 13.3. DC Characteristics (Unless otherwise specified, Ta = -40 to 125 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Symbol Test Condition VIH  VIL VOH VOL VCC (V) Unit V 2.0 1.50  VCC × 0.7  2.0  0.50 3.0 to 5.5  VCC × 0.3 2.0 1.9  3.0 2.9  IOH = -50 µA VIN = VIH or VIL Max 3.0 to 5.5  VIN = VIH or VIL Min 4.5 4.4  IOH = -4 mA 3.0 2.40  IOH = -8 mA 4.5 3.70  IOL = 50 µA 2.0  0.1 3.0  0.1 4.5  0.1 IOL = 4 mA 3.0  0.55 IOL = 8 mA 4.5  0.55 V V V Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5  ±2.0 µA Quiescent supply current ICC VIN = VCC or GND 5.5  80.0 µA 13.4. Timing Requirements (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Symbol Minimum pulse width (CK) tw(L),tw(H) Minimum pulse width (CLR) tw(L) Minimum setup time (A,B,C,D) tS Minimum setup time (LOAD) tS Minimum setup time (ENT,ENP) tS Minimum setup time (CLR) tS Minimum hold time th Minimum hold time (CLR) Minimum removal time (CLR) th trem Note (Note 1) Test Condition VCC (V) Limit Unit Figure 1 3.3 ± 0.3 5.0 ns 5.0 ± 0.5 5.0 3.3 ± 0.3 5.0 5.0 ± 0.5 5.0 3.3 ± 0.3 5.5 5.0 ± 0.5 4.5 3.3 ± 0.3 8.0 5.0 ± 0.5 5.0 3.3 ± 0.3 7.5 5.0 ± 0.5 5.0 3.3 ± 0.3 4.0 5.0 ± 0.5 3.5 3.3 ± 0.3 1.0 5.0 ± 0.5 1.0 3.3 ± 0.3 1.0 5.0 ± 0.5 1.5 3.3 ± 0.3 2.5 5.0 ± 0.5 1.5 Figure 4 Figure 2 Figure 2 Figure 3 (Note 2) Figure 5 Figure 2, Figure 3 (Note 2) Figure 5 (Note 1) Figure 4 ns ns ns ns ns ns ns ns Note 1: For 74VHC161FT only Note 2: For 74VHC163FT only ©2016 Toshiba Corporation 8 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 13.5. Timing Requirements (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) Characteristics Symbol Minimum pulse width (CK) tw(L),tw(H) Minimum pulse width (CLR) tw(L) Minimum setup time (A,B,C,D) tS Minimum setup time (LOAD) tS Minimum setup time (ENT,ENP) tS Minimum setup time (CLR) tS Minimum hold time th Minimum hold time (CLR) Minimum removal time (CLR) th trem Note (Note 1) Test Condition VCC (V) Limit Unit Figure 1 3.3 ± 0.3 5.0 ns 5.0 ± 0.5 5.0 3.3 ± 0.3 5.0 5.0 ± 0.5 5.0 3.3 ± 0.3 6.5 5.0 ± 0.5 4.5 3.3 ± 0.3 9.5 5.0 ± 0.5 6.0 3.3 ± 0.3 9.0 5.0 ± 0.5 6.0 3.3 ± 0.3 4.0 5.0 ± 0.5 3.5 3.3 ± 0.3 1.0 5.0 ± 0.5 1.0 3.3 ± 0.3 1.0 5.0 ± 0.5 1.5 3.3 ± 0.3 2.5 5.0 ± 0.5 1.5 Figure 4 Figure 2 Figure 2 Figure 3 (Note 2) Figure 5 Figure 2, Figure 3 (Note 2) Figure 5 (Note 1) Figure 4 ns ns ns ns ns ns ns ns Note 1: For 74VHC161FT only Note 2: For 74VHC163FT only 13.6. Timing Requirements (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns) Characteristics Symbol Minimum pulse width (CK) tw(L),tw(H) Minimum pulse width (CLR) tw(L) Minimum setup time (A,B,C,D) tS Minimum setup time (LOAD) tS Minimum setup time (ENT,ENP) tS Minimum setup time (CLR) tS Minimum hold time th Minimum hold time (CLR) Minimum removal time (CLR) th trem Note (Note 1) Test Condition VCC (V) Limit Unit Figure 1 3.3 ± 0.3 5.0 ns 5.0 ± 0.5 5.0 3.3 ± 0.3 5.0 5.0 ± 0.5 5.0 3.3 ± 0.3 6.5 5.0 ± 0.5 4.5 3.3 ± 0.3 9.5 5.0 ± 0.5 6.0 3.3 ± 0.3 9.0 5.0 ± 0.5 6.0 3.3 ± 0.3 4.0 5.0 ± 0.5 3.5 3.3 ± 0.3 1.0 5.0 ± 0.5 1.0 3.3 ± 0.3 1.0 5.0 ± 0.5 1.5 3.3 ± 0.3 3.5 5.0 ± 0.5 2.0 Figure 4 Figure 2 Figure 2 Figure 3 (Note 2) Figure 5 Figure 2, Figure 3 (Note 2) Figure 5 (Note 1) Figure 4 ns ns ns ns ns ns ns ns Note 1: For 74VHC161FT only Note 2: For 74VHC163FT only ©2016 Toshiba Corporation 9 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 13.7. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (CK - Q) Symbol Note tPLH,tPHL Test Condition VCC (V) CL (pF) Min Figure 1, Figure 2 3.3 ± 0.3 15 50 5.0 ± 0.5 Propagation delay time (CK - CARRY , count-mode) tPLH,tPHL Figure 1 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK - CARRY , preset-mode) tPLH,tPHL Figure 2 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (ENT - CARRY) tPLH,tPHL Figure 6 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR - Q) tPHL (Note 1) Figure 4 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR - CARRY) tPHL (Note 1) Figure 4 3.3 ± 0.3 5.0 ± 0.5 Maximum clock frequency fMAX  3.3 ± 0.3 5.0 ± 0.5 Input capacitance CIN Power dissipation capacitance CPD (Note 2) Typ. Max Unit  8.3 12.8 ns  10.8 16.3 15  4.9 8.1 50  6.4 10.1 15  8.7 13.6 50  11.2 17.1 15  4.9 8.1 50  6.4 10.1 15  11.0 17.2 50  13.5 20.7 15  6.2 10.3 50  7.7 12.3 15  7.5 12.3 50  10.5 15.8 15  4.9 8.1 50  6.4 10.1 15  8.9 13.6 50  11.2 17.1 15  5.5 9.0 50  7.0 11.0 15  8.4 13.2 50  10.9 16.7 15  5.0 8.6 50  6.5 10.6 15 80 130  50 55 85  15 135 185  50 95 125  ns ns ns ns ns MHz   4 10 pF   23  pF Note 1: For 74VHC161FT only Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(opr) = CPD × VCC × fIN + ICC When the outputs drive a capacitive load, total current consumption is the sum of ICC(opr) and ∆ICC which is obtained from the following formula: ∆ICC = fCK × VCC × (CQA/2 + CQB/4 + CQC/8 + CQD/16 + CCO/16) CQA to CQD and CCO are the capacitances at QA to QD and Carry out, respectively. fCK is the input frequency of the CK. ©2016 Toshiba Corporation 10 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 13.8. AC Characteristics (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (CK - Q) Symbol Note tPLH,tPHL Test Condition VCC (V) CL (pF) Min Max Unit Figure 1, Figure 2 3.3 ± 0.3 15 1.0 15.0 ns 50 1.0 18.5 15 1.0 9.5 50 1.0 11.5 15 1.0 16.0 50 1.0 19.5 15 1.0 9.5 50 1.0 11.5 15 1.0 20.0 50 1.0 23.5 15 1.0 12.0 50 1.0 14.0 15 1.0 14.5 50 1.0 18.0 15 1.0 9.5 50 1.0 11.5 15 1.0 16.0 50 1.0 19.5 15 1.0 10.5 50 1.0 12.5 15 1.0 15.5 50 1.0 19.0 15 1.0 10.0 50 1.0 12.0 15 70  50 50  15 115  50 85   10 5.0 ± 0.5 Propagation delay time (CK - CARRY , count-mode) tPLH,tPHL Figure 1 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK - CARRY , preset-mode) tPLH,tPHL Figure 2 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (ENT - CARRY) tPLH,tPHL Figure 6 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR - Q) tPHL (Note 1) Figure 4 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR - CARRY) tPHL (Note 1) Figure 4 3.3 ± 0.3 5.0 ± 0.5 Maximum clock frequency fMAX  3.3 ± 0.3 5.0 ± 0.5 Input capacitance CIN  ns ns ns ns ns MHz pF Note 1: For 74VHC161FT only ©2016 Toshiba Corporation 11 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 13.9. AC Characteristics (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (CK - Q) Symbol Note tPLH,tPHL Test Condition VCC (V) CL (pF) Min Max Unit Figure 1, Figure 2 3.3 ± 0.3 15 1.0 17.0 ns 50 1.0 20.5 15 1.0 11.0 50 1.0 13.0 15 1.0 18.0 50 1.0 21.5 15 1.0 11.0 50 1.0 13.0 15 1.0 22.5 50 1.0 26.0 15 1.0 13.5 50 1.0 15.5 15 1.0 16.5 50 1.0 20.0 15 1.0 11.0 50 1.0 13.0 15 1.0 18.0 50 1.0 21.5 15 1.0 12.0 50 1.0 14.0 15 1.0 17.5 50 1.0 21.0 15 1.0 11.5 50 1.0 13.5 15 60  50 40  15 105  50 75   10 5.0 ± 0.5 Propagation delay time (CK - CARRY , count-mode) tPLH,tPHL Figure 1 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK - CARRY , preset-mode) tPLH,tPHL Figure 2 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (ENT - CARRY) tPLH,tPHL Figure 6 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR - Q) tPHL (Note 1) Figure 4 3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR - CARRY) tPHL (Note 1) Figure 4 3.3 ± 0.3 5.0 ± 0.5 Maximum clock frequency fMAX  3.3 ± 0.3 5.0 ± 0.5 Input capacitance CIN  ns ns ns ns ns MHz pF Note 1: For 74VHC161FT only ©2016 Toshiba Corporation 12 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 14. Noise Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) Typ. Limit Unit Quiet output maximum dynamic VOL VOLP CL = 50 pF 5.0 0.4 0.8 V Quiet output minimum dynamic VOL VOLV CL = 50 pF 5.0 -0.4 -0.8 V Minimum high-level dynamic input voltage VIHD CL = 50 pF 5.0  3.5 V Maximum low-level dynamic input voltage VILD CL = 50 pF 5.0  1.5 V 15. Internal Equivalent Circuit ©2016 Toshiba Corporation 13 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 16. AC Characteristics Test Waveform Figure 1 Count Mode Figure 4 Clear Mode (74VHC161FT) Figure 2 Preset Mode Figure 5 Clear Mode (74VHC163FT) Figure 3 Count Enable Mode Figure 6 Cascade Mode (fix maximum count) ©2016 Toshiba Corporation 14 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT 17. Typical Application Parallel Carry N-Bit Counter ©2016 Toshiba Corporation 15 2016-08-18 Rev.3.0 74VHC161FT,74VHC163FT Package Dimensions Unit: mm Weight: 0.055 g (typ.) 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