74VHC393FT(BJ)

74VHC393FT CMOS Digital Integrated Circuits Silicon Monolithic 74VHC393FT 1. Functional Description • Dual Binary Counter 2. General The 74VHC393FT is an advanced high speed CMOS 4-BIT BINARY COUNTER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It contains two independent counter circuits in one package, so that counting or frequency division of eight binary bits can be achieved with one IC. This device changes state on the negative going transition of the CK pulse. The counter can be reset to "0" (QA to QD = "L") by a high at the CLR input regardless of other inputs. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. 3. Features (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: Topr = -40 to 125  (3) High speed: fMAX = 170 MHz (typ.) at VCC = 5.0 V (4) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (5) High noise immunity: VNIH = VNIL = 28 % VCC (min) (6) Power-down protection is provided on all inputs. (7) Balanced propagation delays: tPLH ≈ tPHL (8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V (9) Low noise: VOLP = 0.8 V (max) (10) Pin and function compatible with the 74 series (74AC/HC/AHC etc.) 393 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. Packaging TSSOP14B Start of commercial production ©2015 Toshiba Corporation 1 2014-12 2017-02-22 Rev.3.0 74VHC393FT 5. Pin Assignment 6. Marking 7. IEC Logic Symbol ©2015 Toshiba Corporation 2 2017-02-22 Rev.3.0 74VHC393FT 8. Truth Table X: Don't care 9. Timing Diagrams 10. System Diagram ©2015 Toshiba Corporation 3 2017-02-22 Rev.3.0 74VHC393FT 11. Absolute Maximum Ratings (Note) Characteristics Symbol Note Rating Unit Supply voltage VCC -0.5 to 7.0 V Input voltage VIN -0.5 to 7.0 V VOUT -0.5 to VCC + 0.5 V IIK -20 mA Output diode current IOK ±20 mA Output current IOUT ±25 mA VCC/ground current ICC Power dissipation PD Storage temperature Tstg Output voltage Input diode current (Note 1) ±75 mA 180 mW -65 to 150  Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: 180 mW in the range of Ta = -40 to 85 . From Ta = 85 to 125  a derating factor of -3.25 mW/ shall be applied until 50 mW. 12. Operating Ranges (Note) Characteristics Supply voltage Input voltage Output voltage Symbol Test Condition Rating Unit VCC  2.0 to 5.5 V VIN  0 to 5.5 V VOUT  0 to VCC V  Operating temperature Topr Input rise and fall times dt/dv Note: -40 to 125  VCC = 3.3 ± 0.3 V 0 to 100 ns/V VCC = 5.0 ± 0.5 V 0 to 20 The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. ©2015 Toshiba Corporation 4 2017-02-22 Rev.3.0 74VHC393FT 13. Electrical Characteristics 13.1. DC Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics Symbol Test Condition High-level input voltage VIH  Low-level input voltage VIL  High-level output voltage VOH Low-level output voltage VOL VIN = VIH or VIL Min Typ. Max Unit 2.0 1.50   V 3.0 to 5.5 VCC × 0.7   2.0   0.50 3.0 to 5.5   VCC × 0.3 2.0 1.9 2.0  3.0 2.9 3.0  4.5 4.4 4.5  IOH = -4 mA 3.0 2.58   IOH = -8 mA 4.5 3.94   IOL = 50 µA 2.0  0.0 0.1 3.0  0.0 0.1 4.5  0.0 0.1 3.0   0.36 IOH = -50 µA VIN = VIH or VIL VCC (V) IOL = 4 mA IOL = 8 mA V V V 4.5   0.36 Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5   ±0.1 µA Quiescent supply current ICC VIN = VCC or GND 5.5   4.0 µA Min Max Unit V 13.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Symbol VIH VIL VOH VOL Test Condition VCC (V)   VIN = VIH or VIL IOH = -50 µA VIN = VIH or VIL 2.0 1.50  3.0 to 5.5 VCC × 0.7  2.0  0.50 3.0 to 5.5  VCC × 0.3 2.0 1.9  3.0 2.9  4.5 4.4  IOH = -4 mA 3.0 2.48  IOH = -8 mA 4.5 3.80  IOL = 50 µA 2.0  0.1 3.0  0.1 4.5  0.1 IOL = 4 mA 3.0  0.44 IOL = 8 mA 4.5  0.44 V V V Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5  ±1.0 µA Quiescent supply current ICC VIN = VCC or GND 5.5  40.0 µA ©2015 Toshiba Corporation 5 2017-02-22 Rev.3.0 74VHC393FT 13.3. DC Characteristics (Unless otherwise specified, Ta = -40 to 125 ) Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Symbol VIH VIL VOH VOL Test Condition VCC (V)   VIN = VIH or VIL IOH = -50 µA VIN = VIH or VIL Min Max Unit V 2.0 1.50  3.0 to 5.5 VCC × 0.7  2.0  0.50 3.0 to 5.5  VCC × 0.3 2.0 1.9  3.0 2.9  4.5 4.4  IOH = -4 mA 3.0 2.40  IOH = -8 mA 4.5 3.70  IOL = 50 µA 2.0  0.1 3.0  0.1 4.5  0.1 IOL = 4 mA 3.0  0.55 IOL = 8 mA 4.5  0.55 V V V Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5  ±2.0 µA Quiescent supply current ICC VIN = VCC or GND 5.5  80.0 µA ©2015 Toshiba Corporation 6 2017-02-22 Rev.3.0 74VHC393FT 13.4. Timing Requirements (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Minimum pulse width (CK) Minimum pulse width (CLR) Minimum removal time Symbol Test Condition VCC (V) Typ. Limit Unit tw(L),tw(H)  3.3 ± 0.3  5.0 ns 5.0 ± 0.5  5.0 3.3 ± 0.3  5.0 5.0 ± 0.5  5.0 3.3 ± 0.3  5.0 5.0 ± 0.5  4.0 tw(H)  trem  ns ns 13.5. Timing Requirements (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) Characteristics Minimum pulse width (CK) Minimum pulse width (CLR) Minimum removal time Symbol Test Condition VCC (V) Limit Unit tw(L),tw(H)  3.3 ± 0.3 5.0 ns 5.0 ± 0.5 5.0 3.3 ± 0.3 5.0 5.0 ± 0.5 5.0 3.3 ± 0.3 5.0 5.0 ± 0.5 4.0 tw(H)  trem  ns ns 13.6. Timing Requirements (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) Limit Unit tw(L),tw(H)  3.3 ± 0.3 5.0 ns 5.0 ± 0.5 5.0 Minimum pulse width (CLR) tw(H)  3.3 ± 0.3 5.0 5.0 ± 0.5 5.0 Minimum removal time trem  3.3 ± 0.3 5.0 5.0 ± 0.5 4.0 Minimum pulse width (CK) ©2015 Toshiba Corporation 7 ns ns 2017-02-22 Rev.3.0 74VHC393FT 13.7. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (CK-QA) Symbol Note Test Condition VCC (V) CL (pF) Min  3.3 ± 0.3 15 50 tPLH,tPHL 5.0 ± 0.5 Propagation delay time (CK-QB) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK-QC) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK-QD) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR-Qn) tPHL  3.3 ± 0.3 5.0 ± 0.5 Maximum clock frequency fMAX  3.3 ± 0.3 5.0 ± 0.5 Input capacitance CIN Power dissipation capacitance CPD (Note 1) Typ. Max Unit  8.6 13.2 ns  11.1 16.7 15  5.8 8.5 50  7.3 10.5 15  10.2 15.8 50  12.7 19.3 15  6.8 9.8 50  8.3 11.8 15  11.7 18.0 50  14.2 21.5 15  7.7 11.2 50  9.2 13.2 15  13.0 19.7 50  15.5 23.2 15  8.5 12.5 50  10.0 14.5 15  7.9 12.3 50  10.4 15.8 15  5.4 8.1 50  6.9 10.1 15 75 120  50 45 65  15 125 170  50 85 115  ns ns ns ns MHz   4 10 pF   23  pF Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation. ICC(opr) = CPD × VCC × fIN + ICC/2 (per circuit) ©2015 Toshiba Corporation 8 2017-02-22 Rev.3.0 74VHC393FT 13.8. AC Characteristics (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (CK-QA) Symbol Test Condition VCC (V) CL (pF) Min Max Unit tPLH,tPHL  3.3 ± 0.3 15 1.0 15.5 ns 50 1.0 19.0 15 1.0 10.0 50 1.0 12.0 15 1.0 18.5 50 1.0 22.0 15 1.0 11.5 50 1.0 13.5 15 1.0 21.0 50 1.0 24.5 15 1.0 13.0 50 1.0 15.0 15 1.0 23.0 50 1.0 26.5 15 1.0 14.5 50 1.0 16.5 15 1.0 14.5 50 1.0 18.0 15 1.0 9.5 50 1.0 11.5 15 65  50 35  15 105  50 75   10 5.0 ± 0.5 Propagation delay time (CK-QB) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK-QC) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK-QD) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR-Qn) tPHL  3.3 ± 0.3 5.0 ± 0.5 Maximum clock frequency fMAX  3.3 ± 0.3 5.0 ± 0.5 Input capacitance ©2015 Toshiba Corporation CIN  9 ns ns ns ns MHz pF 2017-02-22 Rev.3.0 74VHC393FT 13.9. AC Characteristics (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns) Characteristics Propagation delay time (CK-QA) Symbol Test Condition VCC (V) CL (pF) Min Max Unit tPLH,tPHL  3.3 ± 0.3 15 1.0 17.5 ns 50 1.0 21.0 15 1.0 11.5 50 1.0 13.5 15 1.0 21.0 50 1.0 24.5 15 1.0 13.0 50 1.0 15.0 15 1.0 23.5 50 1.0 27.0 15 1.0 14.5 50 1.0 16.5 15 1.0 25.5 50 1.0 29.0 15 1.0 16.5 50 1.0 18.5 15 1.0 16.5 50 1.0 20.0 15 1.0 11.0 50 1.0 13.0 15 60  50 35  15 100  50 65   10 5.0 ± 0.5 Propagation delay time (CK-QB) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK-QC) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CK-QD) tPLH,tPHL  3.3 ± 0.3 5.0 ± 0.5 Propagation delay time (CLR-Qn) tPHL  3.3 ± 0.3 5.0 ± 0.5 Maximum clock frequency fMAX  3.3 ± 0.3 5.0 ± 0.5 Input capacitance CIN  ns ns ns ns MHz pF 13.10. Noise Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) Typ. Limit Unit Quiet output maximum dynamic VOL VOLP CL = 50 pF 5.0 0.5 0.8 V Quiet output minimum dynamic VOL VOLV CL = 50 pF 5.0 -0.5 -0.8 V Minimum high-level dynamic input voltage VIHD CL = 50 pF 5.0  3.5 V Maximum low-level dynamic input voltage VILD CL = 50 pF 5.0  1.5 V ©2015 Toshiba Corporation 10 2017-02-22 Rev.3.0 74VHC393FT 14. Internal Equivalent Circuit Package Dimensions Unit: mm Weight: 0.054 g (typ.) Package Name(s) Nickname: TSSOP14B ©2015 Toshiba Corporation 11 2017-02-22 Rev.3.0 74VHC393FT RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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