74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
CMOS Digital Integrated Circuits
Silicon Monolithic
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
1. Functional Description
74VHC4051AFT:8-Channel Analog Multiplexer/Demultiplexer
74VHC4052AFT:Dual 4-Channel Analog Multiplexer/Demultiplexer
74VHC4053AFT:Triple 2-Channel Analog Multiplexer/Demultiplexer
2. General
The 74VHC4051AFT, 74VHC4052AFT and 74VHC4053AFT are high-speed, low-voltage drive analog
multiplexer/demultiplexers using silicon gate CMOS technology. In 3 V and 5 V systems these can achieve highspeed operation with the low power dissipation that is a feature of CMOS.
The 74VHC4051AFT, 74VHC4052AFT and 74VHC4053AFT offer analog/digital signal selection as well as mixed
signals. The 74VHC4051AFT has an 8-channel configuration, the 74VHC4052AFT has an 4-channel ×2
configuration, and the 74VHC4053AFT has a 2-channel ×3 configuration.
The switches for each channel are turned ON by the control pin digital signals.
All control inputs are equipped with a newly developed input protection circuit that avoids the need for a diode
on the plus side (forward side from the input to the VCC). As a result, for example, 5.5 V signals can be permitted
on the inputs even when the power supply voltage to the circuits is off. As a result of this input power protection,
the 74VHC4051AFT, 74VHC4052AFT and 74VHC4053AFT can be used in a variety of applications, including
in the system which has two power supplies, and in battery backup circuits.
3. Features
(1)
AEC-Q100 (Rev. H) (Note 1)
(2)
Wide operating temperature range: Topr = -40 to 125
(3)
Low ON-resistance: RON = 45 Ω (typ.) (VCC = 3.0 V)
(4)
Low power dissipation: ICC = 2.0 µA (max) (Ta = 25°C)
(5)
High noise immunity: VIL = 0.8 V (max) VCC =3.0 V
RON = 24 Ω (typ.) (VCC = 4.5 V)
VIH = 2.0 V (min) VCC =3.0 V
(6) Power down protection is provided on all control inputs.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
4. Packaging
TSSOP16B
Start of commercial production
©2015-2018
Toshiba Electronic Devices & Storage Corporation
1
2013-06
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
5. Pin Assignment
74VHC4051AFT
74VHC4052AFT
74VHC4053AFT
©2015-2018
Toshiba Electronic Devices & Storage Corporation
2
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
6. Marking
74VHC4051AFT
74VHC4052AFT
74VHC4053AFT
©2015-2018
Toshiba Electronic Devices & Storage Corporation
3
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
7. System Diagram
74VHC4051AFT
74VHC4052AFT
74VHC4053AFT
©2015-2018
Toshiba Electronic Devices & Storage Corporation
4
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
8. Truth Table
Input
Inhibit
Input
C*
Input
B
L
L
L
L
0
0X, 0Y
0X, 0Y, 0Z
L
L
L
H
1
1X, 1Y
1X, 0Y, 0Z
L
L
H
L
2
2X, 2Y
0X, 1Y, 0Z
L
L
H
H
3
3X, 3Y
1X, 1Y, 0Z
L
H
L
L
4
0X, 0Y, 1Z
L
H
L
H
5
1X, 0Y, 1Z
L
H
H
L
6
0X, 1Y, 1Z
L
H
H
H
7
1X, 1Y, 1Z
H
X
X
X
None
None
None
X:
*:
Input
A
ON Channel
ON Channel
ON Channel
74VHC4051AFT 74VHC4052AFT 74VHC4053AFT
Don't care
Except 74VHC4052AFT
9. Absolute Maximum Ratings (Note)
Characteristics
Symbol
Note
Rating
Unit
Supply voltage
VCC
-0.5 to 7.0
V
Input voltage
VIN
-0.5 to 7.0
V
Switch I/O voltage
VI/O
-0.5 to VCC + 0.5
V
Input diode current
IIK
-20
mA
II/OK
±25
mA
IT
±25
mA
I/O diode current
Switch through current
VCC/ground current
ICC
Power dissipation
PD
Storage temperature
Tstg
(Note 1)
±50
mA
180
mW
-65 to 150
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 1: 180 mW in the range of Ta = -40 to 85 . From Ta = 85 to 125 a derating factor of -3.25 mW/ shall be
applied until 50 mW.
10. Operating Ranges (Note)
Characteristics
Symbol
Test Condition
Rating
Unit
2.0 to 5.5
V
Supply voltage
VCC
Input voltage
VIN
0 to 5.5
V
Switch I/O voltage
VS
0 to VCC
V
Operating temperature
Topr
Input rise and fall times
dt/dv
Note:
-40 to 125
VCC = 2.5 ± 0.2 V
0 to 200
ns/V
VCC = 3.3 ± 0.3 V
0 to 100
VCC = 5 ± 0.5 V
0 to 20
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
©2015-2018
Toshiba Electronic Devices & Storage Corporation
5
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
11. Electrical Characteristics
11.1. DC Characteristics (Unless otherwise specified, Ta = 25 )
Characteristics
High-level input voltage
Low-level input voltage
ON-resistance
Difference of ON-resistance
between switches
Symbol
Test Condition
VCC (V)
Min
Typ.
Max
Unit
VIH
2.0
1.5
V
3.0
2.0
4.5
3.15
5.5
3.85
2.0
0.5
3.0
0.8
4.5
1.35
VIL
RON
∆RON
5.5
1.65
VIN = VIH or VIL
VI/O = VCC to GND
II/O = 2 mA
2.3
200
3.0
45
86
4.5
24
37
VIN = VIH or VIL
VI/O = VCC or GND
II/O = 2 mA
2.3
28
73
3.0
22
38
4.5
17
27
VIN = VIH or VIL
VI/O = VCC to GND
II/O = 2 mA
2.3
10
25
3.0
5
15
4.5
5
13
V
Ω
Ω
Input/Output leakage current
(Switch OFF)
IOFF
VOS = VCC or GND
VIS = GND to VCC
VIN = VIH or VIL
5.5
±0.1
µA
Input/Output leakage current
(Switch ON, Output OPEN)
II/O
VOS = VCC or GND
VIN = VIH or VIL
5.5
±0.1
µA
Control input leakage current
IIN
VIN = VCC or GND
5.5
±0.1
µA
Quiescent supply current
ICC
VIN = VCC or GND
5.5
2.0
µA
©2015-2018
Toshiba Electronic Devices & Storage Corporation
6
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
11.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 )
Characteristics
High-level input voltage
Low-level input voltage
ON-resistance
Symbol
Test Condition
VCC (V)
Min
Max
Unit
VIH
2.0
1.5
V
3.0
2.0
4.5
3.15
5.5
3.85
2.0
0.50
3.0
0.8
4.5
1.35
5.5
1.65
VIN = VIH or VIL
VI/O = VCC to GND
II/O = 2 mA
2.3
3.0
108
4.5
46
VIN = VIH or VIL
VI/O = VCC or GND
II/O = 2 mA
2.3
84
3.0
44
4.5
31
VIN = VIH or VIL
VI/O = VCC to GND
II/O = 2 mA
2.3
35
3.0
20
VIL
RON
V
Ω
Difference of ON-resistance
between switches
∆RON
4.5
18
Input/Output leakage current
(Switch OFF)
IOFF
VOS = VCC or GND
VIS = GND to VCC
VIN = VIH or VIL
5.5
±1.0
µA
Input/Output leakage current
(Switch ON, Output OPEN)
II/O
VOS = VCC or GND
VIN = VIH or VIL
5.5
±1.0
µA
Control input leakage current
IIN
VIN = VCC or GND
5.5
±1.0
µA
Quiescent supply current
ICC
VIN = VCC or GND
5.5
20.0
µA
©2015-2018
Toshiba Electronic Devices & Storage Corporation
7
Ω
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
11.3. DC Characteristics (Unless otherwise specified, Ta = -40 to 125 )
Characteristics
High-level input voltage
Low-level input voltage
ON-resistance
Symbol
Test Condition
VCC (V)
Min
Max
Unit
2.0
1.5
V
3.0
2.0
4.5
3.15
5.5
3.85
2.0
0.5
3.0
0.8
4.5
1.35
5.5
1.65
VIN = VIH or VIL
VI/O = VCC to GND
II/O = 2 mA
2.3
3.0
125
4.5
54
VIN = VIH or VIL
VI/O = VCC or GND
II/O = 2 mA
2.3
105
3.0
55
4.5
39
VIN = VIH or VIL
VI/O = VCC to GND
II/O = 2 mA
2.3
45
3.0
25
VIH
VIL
RON
V
Ω
Difference of ON-resistance
between switches
∆RON
4.5
23
Input/Output leakage current
(Switch OFF)
IOFF
VOS = VCC or GND
VIS = GND to VCC
VIN = VIH or VIL
5.5
±4.0
µA
Input/Output leakage current
(Switch ON, Output OPEN)
II/O
VOS = VCC or GND
VIN = VIH or VIL
5.5
±4.0
µA
Control input leakage current
IIN
VIN = VCC or GND
5.5
±2.0
µA
Quiescent supply current
ICC
VIN = VCC or GND
5.5
40.0
µA
©2015-2018
Toshiba Electronic Devices & Storage Corporation
8
Ω
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
11.4. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns)
Characteristics
Part Number
Phase difference between
input to output
Symbol
Test
Condition
ϕI/O
VCC (V)
CL (pF)
Min
Typ.
Max
Unit
2.5 ± 0.2
15
1.2
10
ns
50
2.6
12
15
0.8
6
50
1.5
9
15
0.3
4
50
0.6
6
15
3.3
15
50
4.2
25
15
2.3
11
50
3.0
18
15
1.6
7
50
2.1
12
15
6
15
50
9.6
25
15
4.5
11
50
7.2
18
15
3.2
7
50
5.1
12
3.3 ± 0.3
5.0 ± 0.5
Output enable time
tPZL,tPZH RL = 1 kΩ
Figure 1
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
Output disable time
tPLZ,tPHZ RL = 1 kΩ
Figure 1
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
Control input capacitance
Common terminal capacitance
Switch terminal capacitance
All types
2
pF
CIS
Figure 2
23.4
pF
74VHC4052AFT
13.1
74VHC4053AFT
8.2
5.7
5.6
5.6
0.5
74VHC4052AFT
0.5
74VHC4053AFT
0.5
15
24
12
74VHC4051AFT
COS
Figure 2
74VHC4053AFT
Power dissipation capacitance
ns
CIN
74VHC4051AFT
74VHC4052AFT
Feedthrough capacitance
ns
74VHC4051AFT
74VHC4051AFT
CIOS
Figure 2
CPD
Figure 2
(Note 1)
74VHC4052AFT
74VHC4053AFT
pF
pF
pF
Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load. Average operating current can be obtained by the equation.
ICC(opr) = CPD × VCC × fIN + ICC
©2015-2018
Toshiba Electronic Devices & Storage Corporation
9
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
11.5. AC Characteristics
(Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns)
Characteristics
Phase difference between input to output
Symbol
Test
Condition
ϕI/O
VCC (V)
CL (pF)
Min
Max
Unit
2.5 ± 0.2
15
16
ns
50
18
15
10
50
12
15
7
50
8
15
20
50
32
15
15
50
22
15
10
50
16
15
23
50
32
15
15
50
22
15
10
50
16
10
pF
3.3 ± 0.3
5.0 ± 0.5
Output enable time
tPZL,tPZH RL = 1 kΩ
Figure 1
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
Output disable time
tPLZ,tPHZ RL = 1 kΩ
Figure 1
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
Control input capacitance
CIN
ns
ns
11.6. AC Characteristics
(Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns)
Characteristics
Phase difference between input to output
Symbol
Test
Condition
ϕI/O
VCC (V)
CL (pF)
Min
Max
Unit
2.5 ± 0.2
15
20
ns
50
22
15
13
50
14
15
9
50
9.5
15
23.5
50
37
15
18
50
25
15
12
50
19
15
28.5
50
37
15
18
50
25
15
12
50
19
10
3.3 ± 0.3
5.0 ± 0.5
Output enable time
tPZL,tPZH RL = 1 kΩ
Figure 1
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
Output disable time
tPLZ,tPHZ RL = 1 kΩ
Figure 1
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
Control input capacitance
©2015-2018
Toshiba Electronic Devices & Storage Corporation
CIN
10
ns
ns
pF
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
11.7. Analog Switch Characteristics (Ta = 25 ) (Note)
Characteristics
Part Number
Sine Wave Distortion
Maximum frequency
response
THD
Test Condition
RL = 10 kΩ, CL = 50 pF
fIN = 1 kHz
74VHC4051AFT fMAX(I/O) VIN is centered at (VCC/2).
Adjust input for 0 dBm.
74VHC4052AFT
Increase fIN frequency until dB
74VHC4053AFT
meter reads -3 dB.
RL = 50 Ω, CL = 10 pF, sine
74VHC4051AFT
wave
74VHC4052AFT
Figure 3
74VHC4053AFT
Feed through
attenuation (switch OFF)
Crosstalk (control input
to signal output)
Crosstalk (between any
switches)
Note:
Symbol
FTH
Xtalk
Xtalk
VCC (V)
Typ.
Unit
%
VIN = 2.0 Vp-p
3.0
0.1
VIN = 4.0 Vp-p
4.5
0.03
3.0
150
MHz
200
240
4.5
180
230
280
VIN is centered at (VCC/2).
Adjust input for 0 dBm.
RL = 600 Ω, CL = 50 pF,
fIN = 1 MHz, sine wave
Figure 4
3.0
-45
4.5
-45
VIN is centered at (VCC/2).
Adjust input for 0 dBm.
RL = 50 Ω, CL = 10 pF,
fIN = 1 MHz, sine wave
Figure 4
3.0
-65
4.5
-65
RL = 600 Ω, CL = 50 pF,
fIN = 1 MHz,
square wave (tr = tf = 6 ns)
Figure 5
3.0
60
4.5
100
VIN is centered at (VCC/2).
Adjust input for 0 dBm.
RL = 600 Ω, CL = 50 pF,
fIN = 1 MHz, sine wave
Figure 6
3.0
-45
4.5
-45
dB
mV
dB
These characteristics are determined by design of devices.
©2015-2018
Toshiba Electronic Devices & Storage Corporation
11
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
12. AC Test Circuit
Figure 1 tPLZ, tPHZ, tPZL, tPZH
Figure 2 CIOS, CIS, COS
Figure 3 Frequency Response
Figure 4 Feedthrough Attenuation
©2015-2018
Toshiba Electronic Devices & Storage Corporation
12
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
Figure 5 Cross Talk (control input to output signal)
Figure 6 Cross Talk (between any two switches)
©2015-2018
Toshiba Electronic Devices & Storage Corporation
13
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
Package Dimensions
Unit: mm
Weight: 0.055 g (typ.)
Package Name(s)
Nickname: TSSOP16B
©2015-2018
Toshiba Electronic Devices & Storage Corporation
14
2018-10-30
Rev.5.0
74VHC4051AFT,74VHC4052AFT,74VHC4053AFT
RESTRICTIONS ON PRODUCT USE
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Hardware, software and systems described in this document are collectively referred to as "Product".
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minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage
to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate
the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA
information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the
precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application
with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications,
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AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
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