74VHC4066AFT(BJ)

74VHC4066AFT CMOS Digital Integrated Circuits Silicon Monolithic 74VHC4066AFT 1. Functional Description • Quad Bilateral Switch 2. General The 74VHC4066AFT is high-speed, low-voltage drive QUAD BILATERAL SWITCH fabricated with silicon gate C2MOS technology. In 3 V and 5 V systems these can achieve high-speed operation with the low power dissipation that is a feature of CMOS. It consists of four independent high speed switches capable of controlling either digital or analog signals while maintaining the CMOS low power dissipation. The switches for each channel are turned ON by the control pin digital signals. Control pin is equipped with a newly developed input protection circuit that avoids the need for a diode on the plus side (forward side from the input to the VCC). As a result, for example, 5.5 V signals can be permitted on the inputs even when the power supply voltage to the circuits is off. As a result of this input power protection, the 74VHC4066AFT can be used in a variety of applications, including in the system which has two power supplies, and in battery backup circuits. 3. Features (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: Topr = -40 to 125  (3) Low ON resistance: RON = 45 Ω (typ.) at VCC = 3.0 V (4) Low power dissipation: ICC = 2.0 µA (max) at Ta = 25  (5) Input level: VIL = 0.8 V (max) at VCC = 3.0 V : RON = 24 Ω (typ.) at VCC = 4.5 V : VIH = 2.0 V (min) at VCC = 3.0 V (6) Power-down protection is provided on all control inputs. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. Packaging TSSOP14B Start of commercial production ©2016 Toshiba Corporation 1 2014-10 2017-02-22 Rev.3.0 74VHC4066AFT 5. Pin Assignment 6. Marking 7. Truth Table Control Switch Function H On L Off 8. System Diagram (per circuit) ©2016 Toshiba Corporation 2 2017-02-22 Rev.3.0 74VHC4066AFT 9. Absolute Maximum Ratings (Note) Characteristics Symbol Note Rating Unit Supply voltage VCC -0.5 to 7.0 V Input voltage VIN -0.5 to 7.0 V Switch I/O voltage VI/O -0.5 to VCC + 0.5 V Input diode current IIK -20 mA II/OK ±25 mA IT ±25 mA I/O diode current Switch through current VCC/ground current ICC Power dissipation PD Storage temperature Tstg (Note 1) ±50 mA 180 mW -65 to 150  Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: 180 mW in the range of Ta = -40 to 85 . From Ta = 85 to 125  a derating factor of -3.25 mW/ shall be applied until 50 mW. 10. Operating Ranges (Note) Characteristics Supply voltage Symbol Test Condition VCC Rating Unit 2.0 to 5.5 V Input voltage VIN 0 to 5.5 V Switch I/O voltage VI/O 0 to VCC V Operating temperature Topr Input rise and fall times dt/dv Note: -40 to 125  VCC = 2.5 ± 0.2 V 0 to 200 ns/V VCC = 3.3 ± 0.3 V 0 to 100 VCC = 5.0 ± 0.5 V 0 to 20 The operating ranges must be maintained to ensure the normal operation of the device. Unused control inputs must be tied to either VCC or GND. ©2016 Toshiba Corporation 3 2017-02-22 Rev.3.0 74VHC4066AFT 11. Electrical Characteristics 11.1. DC Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics Symbol Test Condition VCC (V) Min Typ. Max Unit VIH  2.0 1.5   V 3.0 2.0   4.5 3.15   5.5 3.85   2.0   0.5 3.0   0.8 4.5   1.35 High-level input voltage Low-level input voltage VIL ON-resistance Difference of ON-resistance between switches RON ∆RON  5.5   1.65 VIN = VIH VI/O = VCC to GND II/O = 2 mA 2.3  200  3.0  45 86 4.5  24 37 VIN = VIH VI/O = VCC or GND II/O = 2 mA 2.3  28 73 3.0  22 38 4.5  17 27 VIN = VIH VI/O = VCC to GND II/O = 2 mA 2.3  10 25 3.0  5 15 4.5  5 13 V Ω Ω Input/Output leakage current (Switch OFF) IOFF VOS = VCC or GND VIS = GND to VCC VIN = VIL 5.5   ±0.1 µA Input/Output leakage current (Switch ON, output open) II/O VOS = VCC or GND VIN = VIH 5.5   ±0.1 µA Control input leakage current IIN VIN = VCC or GND 5.5   ±0.1 µA Quiescent supply current ICC VIN = VCC or GND 5.5   2.0 µA ©2016 Toshiba Corporation 4 2017-02-22 Rev.3.0 74VHC4066AFT 11.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 ) Characteristics Symbol Test Condition VCC (V) Min Max Unit VIH  2.0 1.5  V 3.0 2.0  4.5 3.15  5.5 3.85  2.0  0.5 3.0  0.8 4.5  1.35 5.5  1.65 VIN = VIH VI/O = VCC to GND II/O = 2 mA 2.3   3.0  108 4.5  46 VIN = VIH VI/O = VCC or GND II/O = 2 mA 2.3  84 3.0  44 4.5  31 VIN = VIH VI/O = VCC to GND II/O = 2 mA 2.3  35 3.0  20 High-level input voltage Low-level input voltage VIL ON-resistance RON  V Ω Difference of ON-resistance between switches ∆RON 4.5  18 Input/Output leakage current (Switch OFF) IOFF VOS = VCC or GND VIS = GND to VCC VIN = VIL 5.5  ±1.0 µA Input/Output leakage current (Switch ON, output open) II/O VOS = VCC or GND VIN = VIH 5.5  ±1.0 µA Control input leakage current IIN VIN = VCC or GND 5.5  ±1.0 µA Quiescent supply current ICC VIN = VCC or GND 5.5  20.0 µA ©2016 Toshiba Corporation 5 Ω 2017-02-22 Rev.3.0 74VHC4066AFT 11.3. DC Characteristics (Unless otherwise specified, Ta = -40 to 125 ) Characteristics Symbol High-level input voltage VIH Low-level input voltage VIL ON-resistance RON Test Condition VCC (V) Min Max Unit 2.0 1.5  V 3.0 2.0  4.5 3.15  5.5 3.85  2.0  0.5 3.0  0.8 4.5  1.35 5.5  1.65 VIN = VIH VI/O = VCC to GND II/O = 2 mA 2.3   3.0  125 4.5  54 VIN = VIH VI/O = VCC or GND II/O = 2 mA 2.3  105 3.0  55 4.5  39 VIN = VIH VI/O = VCC to GND II/O = 2 mA 2.3  45 3.0  25   V Ω Ω Difference of ON-resistance between switches ∆RON 4.5  23 Input/Output leakage current (Switch OFF) IOFF VOS = VCC or GND VIS = GND to VCC VIN = VIL 5.5  ±4.0 µA Input/Output leakage current (Switch ON, output open) II/O VOS = VCC or GND VIN = VIH 5.5  ±4.0 µA Control input leakage current IIN VIN = VCC or GND 5.5  ±2.0 µA Quiescent supply current ICC VIN = VCC or GND 5.5  40.0 µA ©2016 Toshiba Corporation 6 Ω 2017-02-22 Rev.3.0 74VHC4066AFT 11.4. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns) Characteristics Phase difference between input to output Symbol ϕI/O Note Test Condition VCC (V) Min Typ. Max Unit 2.5 ± 0.2  1.2 10 ns 3.3 ± 0.3  0.8 6 5.0 ± 0.5  0.3 4 2.5 ± 0.2  2.6 12 3.3 ± 0.3  1.5 9 5.0 ± 0.5  0.6 6 CL = 15 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  3.3 15 3.3 ± 0.3  2.3 11 5.0 ± 0.5  1.6 7 CL = 50 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  4.2 25 3.3 ± 0.3  3.0 18 5.0 ± 0.5  2.1 12 CL = 15 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  6 15 3.3 ± 0.3  4.5 11 5.0 ± 0.5  3.2 7 CL = 50 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  9.6 25 3.3 ± 0.3  7.2 18 5.0 ± 0.5  5.1 12 CL = 15 pF RL = 1 kΩ CL = 50 pF RL = 1 kΩ Output enable time Output disable time tPZL, tPZH tPLZ, tPHZ ns ns Control input capacitance CIN All types  3  pF Switch terminal capacitance COS See 12. AC Test Circuit, Figure 2  5.5  pF Feedthrough capacitance CIOS See 12. AC Test Circuit, Figure 2  0.5  pF Power dissipation capacitance CPD (Note 1) See 12. AC Test Circuit, Figure 2  4.5  pF Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation. ICC(opr) = CPD × VCC × fIN + ICC ©2016 Toshiba Corporation 7 2017-02-22 Rev.3.0 74VHC4066AFT 11.5. AC Characteristics (Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns) Characteristics Phase difference between input to output Symbol VCC (V) Min Max Unit 2.5 ± 0.2  16 ns 3.3 ± 0.3  10 5.0 ± 0.5  7 2.5 ± 0.2  18 3.3 ± 0.3  12 5.0 ± 0.5  8 tPZL,tPZH CL = 15 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  20 3.3 ± 0.3  15 5.0 ± 0.5  10 CL = 50 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  32 3.3 ± 0.3  22 5.0 ± 0.5  16 tPLZ,tPHZ CL = 15 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  23 3.3 ± 0.3  15 5.0 ± 0.5  10 CL = 50 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  32 3.3 ± 0.3  22 5.0 ± 0.5  16 ϕI/O Test Condition CL = 15 pF RL = 1 kΩ CL = 50 pF RL = 1 kΩ Output enable time Output disable time ns ns 11.6. AC Characteristics (Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns) Characteristics Phase difference between input to output Symbol VCC (V) Min Max Unit 2.5 ± 0.2  20 ns 3.3 ± 0.3  13 5.0 ± 0.5  9 2.5 ± 0.2  22 3.3 ± 0.3  14 5.0 ± 0.5  9.5 tPZL,tPZH CL = 15 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  23.5 3.3 ± 0.3  18 5.0 ± 0.5  12 CL = 50 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  37 3.3 ± 0.3  25 5.0 ± 0.5  19 tPLZ,tPHZ CL = 15 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  28.5 3.3 ± 0.3  18 5.0 ± 0.5  12 CL = 50 pF RL = 1 kΩ See 12. AC Test Circuit, Figure 1 2.5 ± 0.2  37 3.3 ± 0.3  25 5.0 ± 0.5  19 ϕI/O Test Condition CL = 15 pF RL = 1 kΩ CL = 50 pF RL = 1 kΩ Output enable time Output disable time ©2016 Toshiba Corporation 8 ns ns 2017-02-22 Rev.3.0 74VHC4066AFT 11.7. Analog Switch Characteristics (Ta = 25 ) (Note) Characteristics Sine Wave Distortion Maximum frequency response (switch ON) Feed through attenuation (switch OFF) Crosstalk (control input to signal output) Crosstalk (between any switches) Note: Symbol THD Test Condition RL = 10 kΩ, CL = 50 pF, fIN = 1 kHz Xtalk Xtalk Typ. Unit % VIN = 2.0 Vp-p 3.0 0.1 VIN = 4.0 Vp-p 4.5 0.03 3.0 250 4.5 290 VIN is centered at (VCC/2). Adjust input for 0dBm. RL = 600 Ω, CL = 50 pF, fIN = 1 MHz, sine wave See 12. AC Test Circuit, Figure 4 3.0 -45 4.5 -45 RL = 50 Ω, CL = 10 pF, fIN = 1 MHz, sine wave 3.0 -65 4.5 -65 RL = 600 Ω, CL = 50 pF, fIN = 1 MHz, square wave (tr = tf = 6 ns) See 12. AC Test Circuit, Figure 5 3.0 60 4.5 100 VIN is centered at (VCC/2). Adjust input for 0dBm. RL = 600 Ω, CL = 50 pF, fIN = 1 MHz, sine wave See 12. AC Test Circuit, Figure 6 3.0 -45 4.5 -45 fMAX(I/O) VIN is centered at (VCC/2). Adjust input for 0dBm. Increase fIN frequency until dB meter reads -3dB. RL = 50 Ω, CL = 10 pF, sine wave See 12. AC Test Circuit, Figure 3 FTH VCC (V) MHz dB mV dB These characteristics are determined by design of devices. ©2016 Toshiba Corporation 9 2017-02-22 Rev.3.0 74VHC4066AFT 12. AC Test Circuit Figure 1 tPLZ, tPHZ, tPZL, tPZH Figure 2 CIOS, COS Figure 3 Frequency Response (switch on) ©2016 Toshiba Corporation 10 2017-02-22 Rev.3.0 74VHC4066AFT Figure 4 Feedthrough Figure 5 Cross Talk (control input to output signal) Figure 6 Cross Talk (between any two switches) ©2016 Toshiba Corporation 11 2017-02-22 Rev.3.0 74VHC4066AFT Package Dimensions Unit: mm Weight: 0.054 g (typ.) Package Name(s) Nickname: TSSOP14B ©2016 Toshiba Corporation 12 2017-02-22 Rev.3.0 74VHC4066AFT RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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