74VHCV574FT
CMOS Digital Integrated Circuits
Silicon Monolithic
74VHCV574FT
1. Functional Description
•
Octal Schmitt D-Type Flip-Flop with 3-State Outputs
2. General
The 74VHCV574FT is advanced high speed CMOS OCTAL FLIP-FLOP with 3-STATE OUTPUT fabricated with
silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS
low power dissipation.
This 8-bit D-type flip-flop is controlled by a clock input (CK) and an output enable input (OE).
When the OE input is high, the eight outputs are in a high impedance state.
Input pin have hysteresis between the positive-going and negative-going thresholds. Thus the 74VHCV574FT is
capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins
without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and
input/output voltages such as battery back up, etc.
Note: Output in off-state.
3. Features
(1)
AEC-Q100 (Rev. H) (Note 1)
(2)
Wide operating temperature range: Topr = -40 to 125
(3)
High speed: fMAX = 180 MHz (typ.) at VCC = 5.0 V
(4)
Low power dissipation: ICC = 2.0 µA (max) at Ta = 25
(5)
Wide operating voltage range: VCC(opr) = 1.8 V to 5.5 V
(6)
Output current: |IOH|/IOL = 16 mA (min)(VCC = 4.5 V)
(7)
Power-down protection is provided on all inputs and outputs.
(8) Pin and function compatible with the 74 series (74AC/HC/AHC/LV etc.) 574 type.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
4. Packaging
TSSOP20B
Start of commercial production
©2016 Toshiba Corporation
1
2014-07
2016-08-05
Rev.2.0
74VHCV574FT
5. Pin Assignment
6. Marking
7. Truth Table
X:
Z:
Qn:
Don't care
High impedance
No change
©2016 Toshiba Corporation
2
2016-08-05
Rev.2.0
74VHCV574FT
8. System Diagram
©2016 Toshiba Corporation
3
2016-08-05
Rev.2.0
74VHCV574FT
9. Absolute Maximum Ratings (Note)
Characteristics
Symbol
Note
Rating
Unit
Supply voltage
VCC
-0.5 to 7.0
V
Input voltage
VIN
-0.5 to 7.0
V
(Note 1)
-0.5 to 7.0
V
(Note 2)
-0.5 to VCC + 0.5
-50
mA
(Note 3)
±50
mA
±50
mA
(Note 4)
180
mW
ICC/IGND
±100
mA
Tstg
-65 to 150
Output voltage
VOUT
Input diode current
IIK
Output diode current
IOK
Output current
IOUT
Power dissipation
PD
VCC/ground current
Storage temperature
Note:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 1: Output in OFF state.
Note 2: High (H) or Low (L) state. IOUT absolute maximum rating must be observed.
Note 3: VOUT < GND, VOUT > VCC
Note 4: 180 mW in the range of Ta = -40 to 85 . From Ta = 85 to 125 a derating factor of -3.25 mW/ shall be
applied until 50 mW.
10. Operating Ranges (Note)
Characteristics
Symbol
Test Condition
Supply voltage
VCC
Input voltage
VIN
VOUT
Output voltage
Operating temperature
Topr
Input rise and fall times
dt/dv
Rating
Unit
1.8 to 5.5
V
0 to 5.5
V
(Note 1)
0 to 5.5
V
(Note 2)
0 to VCC
Note
-40 to 125
VCC = 3.3 ± 0.3 V
0 to 20
ms/V
VCC = 5 ± 0.5 V
0 to 1
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Note 1: Output in OFF state.
Note 2: High (H) or Low (L) state.
©2016 Toshiba Corporation
4
2016-08-05
Rev.2.0
74VHCV574FT
11. Electrical Characteristics
11.1. DC Characteristics (Unless otherwise specified, Ta = 25 )
Characteristics
Positive threshold voltage
Negative threshold voltage
Hysteresis voltage
High-level output voltage
Low-level output voltage
Symbol
VP
VN
VH
VOH
VOL
Test Condition
VIN = VIH or VIL
VIN = VIH or VIL
IOH = -50 µA
VCC (V)
Min
Typ.
Max
Unit
1.8
1.65
V
2.3
1.85
3.0
2.20
4.5
3.15
5.5
3.85
1.8
0.15
2.3
0.45
3.0
0.90
4.5
1.35
5.5
1.65
1.8
0.15
1.05
2.3
0.20
1.10
3.0
0.30
1.20
4.5
0.40
1.40
5.5
0.50
1.60
1.8
1.7
1.8
3.0
2.9
3.0
4.5
4.4
4.5
IOH = -8 mA
3.0
2.58
IOH = -16 mA
4.5
3.94
IOL = 50 µA
1.8
0.0
0.1
3.0
0.0
0.1
4.5
0.0
0.1
IOL = 8 mA
3.0
0.36
IOL = 16 mA
4.5
0.44
V
V
V
V
3-state output OFF-state
leakage current
IOZ
VIN = VIH or VIL
VOUT = 0 to 5.5 V
1.8 to 5.5
±0.5
µA
Power-OFF leakage current
IOFF
VIN/VOUT = 5.5 V
0
0.5
µA
Input leakage current
IIN
VIN = 5.5 V or GND
0 to 5.5
±0.1
µA
Quiescent supply current
ICC
VIN = VCC or GND
5.5
2.0
µA
©2016 Toshiba Corporation
5
2016-08-05
Rev.2.0
74VHCV574FT
11.2. DC Characteristics (Unless otherwise specified, Ta = -40 to 85 )
Characteristics
Positive threshold voltage
Negative threshold voltage
Hysteresis voltage
High-level output voltage
Low-level output voltage
Symbol
VP
VN
VH
VOH
VOL
Test Condition
VCC (V)
Min
Max
Unit
1.8
1.65
V
2.3
1.85
3.0
2.20
4.5
3.15
5.5
3.85
1.8
0.15
2.3
0.45
3.0
0.90
4.5
1.35
5.5
1.65
1.8
0.15
1.05
2.3
0.20
1.10
3.0
0.30
1.20
4.5
0.40
1.40
5.5
0.50
1.60
1.8
1.7
3.0
2.9
4.5
4.4
IOH = -8 mA
3.0
2.48
IOH = -16 mA
4.5
3.80
IOL = 50 µA
1.8
0.1
3.0
0.1
4.5
0.1
3.0
0.44
VIN = VIH or VIL
VIN = VIH or VIL
IOH = -50 µA
IOL = 8 mA
IOL = 16 mA
V
V
V
V
4.5
0.55
3-state output OFF-state leakage
current
IOZ
VIN = VIH or VIL
VOUT = 0 to 5.5 V
1.8 to 5.5
±5.0
µA
Power-OFF leakage current
IOFF
VIN/VOUT = 5.5 V
0
5.0
µA
Input leakage current
IIN
VIN = 5.5 V or GND
0 to 5.5
±1.0
µA
Quiescent supply current
ICC
VIN = VCC or GND
5.5
20.0
µA
©2016 Toshiba Corporation
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2016-08-05
Rev.2.0
74VHCV574FT
11.3. DC Characteristics (Unless otherwise specified, Ta = -40 to 125 )
Characteristics
Positive threshold voltage
Negative threshold voltage
Hysteresis voltage
High-level output voltage
Low-level output voltage
Symbol
VP
VN
VH
VOH
VOL
Test Condition
VCC (V)
Min
Max
Unit
1.8
1.65
V
2.3
1.85
3.0
2.20
4.5
3.15
5.5
3.85
1.8
0.15
2.3
0.45
3.0
0.90
4.5
1.35
5.5
1.65
1.8
0.15
1.05
2.3
0.20
1.10
3.0
0.30
1.20
4.5
0.40
1.40
5.5
0.50
1.60
1.8
1.7
3.0
2.9
4.5
4.4
IOH = -8 mA
3.0
2.40
IOH = -16 mA
4.5
3.70
IOL = 50 µA
1.8
0.1
3.0
0.1
4.5
0.1
3.0
0.55
VIN = VIH or VIL
VIN = VIH or VIL
IOH = -50 µA
IOL = 8 mA
IOL = 16 mA
V
V
V
V
4.5
0.65
3-state output OFF-state leakage
current
IOZ
VIN = VIH or VIL
VOUT = 0 to 5.5 V
1.8 to 5.5
±20.0
µA
Power-OFF leakage current
IOFF
VIN/VOUT = 5.5 V
0
20.0
µA
Input leakage current
IIN
VIN = 5.5 V or GND
0 to 5.5
±2.0
µA
Quiescent supply current
ICC
VIN = VCC or GND
5.5
40.0
µA
©2016 Toshiba Corporation
7
2016-08-05
Rev.2.0
74VHCV574FT
, Input: tr = tf = 3 ns)
11.4. Timing Requirements (Unless otherwise specified, Ta = 25
25
Characteristics
Minimum pulse width (CK)
Minimum setup time
Minimum hold time
Symbol
VCC (V)
Limit
Unit
tw(L),tw(H)
2.5 ± 0.2
7.0
ns
3.3 ± 0.3
5.0
5.0 ± 0.5
5.0
2.5 ± 0.2
5.5
3.3 ± 0.3
3.5
5.0 ± 0.5
3.5
2.5 ± 0.2
2.0
3.3 ± 0.3
1.5
5.0 ± 0.5
1.5
tS
th
ns
ns
11.5. Timing Requirements
(Unless otherwise specified, Ta = -40 to 85
, Input: tr = tf = 3 ns)
85
Characteristics
Minimum pulse width (CK)
Minimum setup time
Minimum hold time
Symbol
VCC (V)
Limit
Unit
tw(L),tw(H)
2.5 ± 0.2
7.0
ns
3.3 ± 0.3
5.0
5.0 ± 0.5
5.0
2.5 ± 0.2
5.5
3.3 ± 0.3
3.5
5.0 ± 0.5
3.5
2.5 ± 0.2
2.0
3.3 ± 0.3
1.5
5.0 ± 0.5
1.5
tS
th
ns
ns
11.6. Timing Requirements
(Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns)
Characteristics
Minimum pulse width (CK)
Minimum setup time
Minimum hold time
©2016 Toshiba Corporation
Symbol
VCC (V)
Limit
Unit
tw(L),tw(H)
2.5 ± 0.2
7.0
ns
3.3 ± 0.3
5.0
5.0 ± 0.5
5.0
2.5 ± 0.2
7.0
3.3 ± 0.3
4.5
5.0 ± 0.5
4.0
2.5 ± 0.2
2.0
3.3 ± 0.3
1.5
5.0 ± 0.5
1.5
tS
th
8
ns
ns
2016-08-05
Rev.2.0
74VHCV574FT
11.7. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns)
Characteristics
Propagation delay time
(CK-Q)
Symbol
Note
Test
Condition
VCC (V)
CL (pF)
Min
2.5 ± 0.2
15
50
tPLH,tPHL
Typ.
Max
Unit
9.1
16.6
ns
11.9
19.6
15
6.7
13.2
50
8.9
16.7
15
5.0
8.6
50
6.7
10.6
15
7.6
16.1
50
10.7
19.0
15
5.7
12.8
50
8.1
16.3
15
4.2
9.0
50
6.1
11.0
2.5 ± 0.2
50
13.6
17.5
3.3 ± 0.3
50
10.5
15.0
5.0 ± 0.5
50
8.2
10.1
2.5 ± 0.2
15
60
95
50
50
75
15
80
135
50
55
100
15
130
180
3.3 ± 0.3
5.0 ± 0.5
3-state output enable time
tPZL,tPZH
RL = 1 kΩ
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
3-state output disable time
Maximum clock frequency
tPLZ,tPHZ
RL = 1 kΩ
fMAX
3.3 ± 0.3
5.0 ± 0.5
Output skew
Input capacitance
tosLH,tosHL
(Note 1)
ns
ns
MHz
50
85
135
2.5 ± 0.2
50
2.0
3.3 ± 0.3
50
1.5
5.0 ± 0.5
50
1.0
ns
ns
CIN
4
10
pF
Output capacitance
COUT
6
pF
Power dissipation capacitance
CPD
26
pF
(Note 2)
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load. Average operating current can be obtained by the equation.
ICC(opr) = CPD × VCC × fIN + ICC/8 (per latch)
And the total CPD when n pcs. of latch operate can be gained by the following equation.
CPD (total) = 14 + 12 × n
©2016 Toshiba Corporation
9
2016-08-05
Rev.2.0
74VHCV574FT
11.8. AC Characteristics
(Unless otherwise specified, Ta = -40 to 85 , Input: tr = tf = 3 ns)
Characteristics
Propagation delay time
(CK-Q)
Symbol
Note
Test Condition
VCC (V)
CL (pF)
Min
Max
Unit
2.5 ± 0.2
15
1.0
20.0
ns
50
1.0
23.0
15
1.0
15.5
50
1.0
19.0
15
1.0
10.0
50
1.0
12.0
15
1.0
19.0
50
1.0
22.0
15
1.0
15.0
50
1.0
18.5
15
1.0
10.5
50
1.0
12.5
2.5 ± 0.2
50
1.0
20.0
3.3 ± 0.3
50
1.0
17.0
5.0 ± 0.5
50
1.0
11.5
2.5 ± 0.2
15
50
50
40
15
65
50
45
15
110
tPLH,tPHL
3.3 ± 0.3
5.0 ± 0.5
3-state output enable time
tPZL,tPZH
RL = 1 kΩ
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
3-state output disable time
Maximum clock frequency
tPLZ,tPHZ
RL = 1 kΩ
fMAX
3.3 ± 0.3
5.0 ± 0.5
Output skew
Input capacitance
tosLH,tosHL
(Note 1)
CIN
ns
ns
MHz
50
75
2.5 ± 0.2
50
2.0
3.3 ± 0.3
50
1.5
5.0 ± 0.5
50
1.0
ns
10
pF
ns
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
©2016 Toshiba Corporation
10
2016-08-05
Rev.2.0
74VHCV574FT
11.9. AC Characteristics
(Unless otherwise specified, Ta = -40 to 125 , Input: tr = tf = 3 ns)
Characteristics
Symbol
Propagation delay time
(CK-Q)
Note
Test Condition
VCC (V)
CL (pF)
Min
Max
Unit
2.5 ± 0.2
15
1.0
22.5
ns
50
1.0
25.5
15
1.0
17.5
50
1.0
21.0
15
1.0
11.5
50
1.0
13.5
15
1.0
21.0
50
1.0
24.0
15
1.0
17.0
50
1.0
20.5
15
1.0
12.0
50
1.0
14.0
2.5 ± 0.2
50
1.0
22.0
3.3 ± 0.3
50
1.0
19.0
5.0 ± 0.5
50
1.0
13.0
2.5 ± 0.2
15
40
50
30
15
60
50
40
15
100
tPLH,tPHL
3.3 ± 0.3
5.0 ± 0.5
3-state output enable time
tPZL,tPZH
RL = 1 kΩ
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
3-state output disable time
tPLZ,tPHZ
Maximum clock frequency
RL = 1 kΩ
fMAX
3.3 ± 0.3
5.0 ± 0.5
Output skew
tosLH,tosHL (Note 1)
Input capacitance
CIN
50
65
2.5 ± 0.2
50
2.0
3.3 ± 0.3
50
1.5
5.0 ± 0.5
50
1.0
10
ns
ns
MHz
ns
pF
Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)
, Input: tr = tf = 3 ns)
25
11.10. Noise Characteristics (Unless otherwise specified, Ta = 25
Characteristics
Symbol
Test Condition
VCC (V)
Typ.
Max
Unit
3.3
0.4
V
5.0
0.8
3.3
-0.1
Quiet output maximum dynamic VOL
VOLP
CL = 50 pF
Quiet output minimum dynamic VOL
VOLV
CL = 50 pF
5.0
-0.4
Minimum high-level dynamic input voltage
VIHD
CL = 50 pF
5.0
3.5
V
Maximum low-level dynamic input voltage
VILD
CL = 50 pF
5.0
1.5
V
©2016 Toshiba Corporation
11
V
2016-08-05
Rev.2.0
74VHCV574FT
Package Dimensions
Unit: mm
Weight: 0.071 g (typ.)
Package Name(s)
Nickname: TSSOP20B
©2016 Toshiba Corporation
12
2016-08-05
Rev.2.0
74VHCV574FT
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• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
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written permission, reproduction is permissible only if reproduction is without alteration/omission.
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for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which
minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage
to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate
the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA
information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the
precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application
with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications,
including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating
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©2016 Toshiba Corporation
13
2016-08-05
Rev.2.0