SSM3K310T(TE85L,F)

SSM3K310T TOSHIBA Field Effect Transistor Silicon N-Channel MOS Type SSM3K310T High-Speed Switching Applications Unit: mm Ron = 66 mΩ (max) (@VGS = 1.5 V) Ron = 43 mΩ (max) (@VGS = 1.8 V) Ron = 32 mΩ (max) (@VGS = 2.5 V) Ron = 28 mΩ (max) (@VGS = 4.0 V) +0.2 2.8-0.3 Drain-Source voltage VDS 20 V Gate-Source voltage VGSS ± 10 V Drain current DC ID 5.0 Pulse IDP 10.0 Drain power dissipation A PD (Note 1) 700 mW Channel temperature Tch 150 °C Storage temperature range Tstg −55~150 °C Note: ２ ３ 0.16±0.05 Unit 0.15 Rating 0～0.1 Symbol １ 0.7±0.05 Characteristics 2.9±0.2 Absolute Maximum Ratings (Ta = 25°C) 0.4±0.1 +0.2 1.6-0.1 1.9±0.2 1.5 V drive Low ON-resistance: 0.95 0.95 • • Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/ voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 1.GATE 2.SOURCE 3.DRAIN TSM JEDEC ― JEITA ― TOSHIBA 2-3S1A Weight: 10 mg (typ.) Note 1: Mounted on an FR4 board. 2 (25.4 mm × 25.4 mm × 1.6 t, Cu Pad: 645 mm ) Electrical Characteristics (Ta = 25°C) Characteristics Drain-Source breakdown voltage Symbol Test Condition Min Typ. Max V (BR) DSS ID = 1 mA, VGS = 0 20 ⎯ ⎯ V (BR) DSX ID = 1 mA, VGS = −10 V 12 ⎯ ⎯ Unit V Drain cutoff current IDSS VDS = 20 V, VGS = 0 ⎯ ⎯ 1 μA Gate leakage current IGSS VGS = ±10 V, VDS = 0 ⎯ ⎯ ±1 μA Vth VDS = 3 V, ID = 1 mA 0.35 ⎯ 1.0 V ⏐Yfs⏐ VDS = 3 V, ID = 4.0 A (Note 2) 14 28 ⎯ S ID = 4.0 A, VGS = 4.0 V (Note 2) ⎯ 19 28 ID = 3.0 A, VGS = 2.5 V (Note 2) ⎯ 23 32 ID = 1.0 A, VGS = 1.8 V (Note 2) ⎯ 28 43 ID = 0.5 A, VGS = 1.5 V (Note 2) Gate threshold voltage Forward transfer admittance Drain-Source ON-resistance Input capacitance RDS (ON) Ciss VDS = 10 V, VGS = 0, f = 1 MHz ⎯ 33 66 ⎯ 1120 ⎯ ⎯ 180 ⎯ Output capacitance Coss Reverse transfer capacitance Crss ⎯ 160 ⎯ Qg ⎯ 14.8 ⎯ Total Gate Charge Gate-Source Charge Qgs Gate-Drain Charge Qgd Switching time Turn-on time ton Turn-off time toff Drain-Source forward voltage VDSF VDS = 10 V, IDS= 5.0 A, VGS = 4 V VDD = 10 V, ID = 2.0 A, VGS = 0 to 2.5 V, RG = 4.7 Ω ID = −5.0 A, VGS = 0 V Note 2: Pulse test (Note 2) ⎯ 11.4 ⎯ ⎯ 3.4 ⎯ ⎯ 21 ⎯ ⎯ 36 ⎯ ⎯ -0.85 -1.2 mΩ pF nC ns V Start of commercial production 2006-12 1 2014-03-01 SSM3K310T Switching Time Test Circuit (a) Test Circuit (b) VIN 2.5 V OUT 2.5 V 90% IN 0V RG 0 10 μs (c) VOUT VDD VDD = 10 V RG = 4.7 Ω Duty ≤ 1% VIN: tr, tf < 5 ns Common Source Ta = 25°C Marking 10% VDD VDS (ON) 10% 90% tr ton tf toff Equivalent Circuit (top view) 3 3 KDQ 1 2 1 2 Notice on Usage Vth can be expressed as the voltage between gate and source when the low operating current value is ID = 1 mA for this product. For normal switching operation, VGS (on) requires a higher voltage than Vth, and VGS (off) requires a lower voltage than Vth. (The relationship can be established as follows: VGS (off) < Vth < VGS (on).) Take this into consideration when using the device. Handling Precaution When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that come into direct contact with devices should be made of antistatic materials. 2 2014-03-01 SSM3K310T ID – VDS 10 ID – VGS 10 2.5 V 1.5 V (A) 1 ID VGS = 1.2 V 6 Drain current (A) 8 ID Drain current Common Source VDS = 3 V 1.8 V 4.0 V 4 2 0.1 Ta = 100 °C 25 °C 0.01 0.001 − 25 °C Common Source Ta = 25 °C 0 0 0.4 0.2 0.6 0.8 Drain - Source voltage VDS 0.0001 0 1.0 0.5 (V) RDS (ON) – VGS 100 Common Source Common Source Drain – Source on-resistance RDS (ON) (mΩ) Drain – Source on-resistance RDS (ON) (mΩ) ID =4.0A 50 25 °C Ta = 100 °C − 25 °C 0 2 6 4 Gate - Source voltage 8 1.5 V 1.8 V VGS = 4.0 V 0 2 2.5 V 6 4 Drain current ID 8 10 (A) Vth – Ta 1.0 Gate threshold voltage Vth (V) Common Source 1.0 A / 1.8 V 0.5 A / 1.5 V ID = 4.0 A / VGS = 4.0 V 3.0 A / 2.5 V 0 −50 50 VGS (V) RDS (ON) – Ta 50 Ta = 25°C 0 10 100 Drain – Source on-resistance RDS (ON) (mΩ) 1.5 VGS (V) RDS (ON) – ID 100 0 1.0 Gate - Source voltage Common Source VDS = 3 V 0.8 ID = 1 mA 0.6 0.4 0.2 0 0 50 Ambient temperature 100 Ta −50 150 (°C) 0 50 Ambient temperature 3 100 Ta 150 (°C) 2014-03-01 SSM3K310T IDR – VDS (S) 10 VDS = 3 V 10 Common Source VGS = 0 V D (A) Common Source IDR Ta = 25 °C 3 Drain reverse current Forward transfer admittance ⎪Yfs⎪ |Yfs| – ID 30 1 0.3 0.1 0.03 IDR 1 G 0.1 0.01 0.001 Ta=100 °C 25 °C 0.01 0.001 0.1 0.01 1 Drain current ID 0.0001 0 10 -0.2 (A) -0.4 −25 °C -0.6 -0.8 -1.0 Drain-Source voltage VDS -1.2 (V) t – ID C – VDS 5000 1000 3000 Common Source VDD = 10 V VGS = 0 ∼ 2.5 V Ta = 25 °C RG = 4.7 Ω toff (ns) Ciss 1000 tf 100 300 Switching time Capacitance C t (pF) S Coss 100 Crss Common Source 30 ton 10 tr Ta = 25 °C f = 1 MHz VGS = 0 V 10 0.1 1 10 Drain – Source voltage 1 0.01 100 VDS 0.1 Drain current (V) 1 ID 10 (A) Dynamic Input Characteristic 10 ID = 5.0 A 8 Ta = 25°C Gate-Source voltage VGS (V) Common Source VDD = 10V 6 VDD = 16V 4 2 0 0 10 20 30 Total Gate Charge 40 Qg 50 (nC) 4 2014-03-01 SSM3K310T rth – tw PD – Ta Drain power dissipation PD (mW) Transient thermal impedance Rth (°C/W) 1000 b 100 a Single Pulse 10 a: Mounted on FR4 board (25.4mm × 25.4mm × 1.6t , Cu Pad : 645 mm2) b: Mounted on FR4 board (25.4mm × 25.4mm × 1.6t , Cu Pad : 0.8 mm2×3) 1 0.001 0.01 0.1 1 Pulse width 10 tw 100 1000 800 a 600 400 b 200 0 -40 1000 a: Mounted on FR4 board (25.4mm × 25.4mm × 1.6t , Cu Pad : 645 mm2) b: Mounted on FR4 board (25.4mm × 25.4mm × 1.6t , 2 Cu Pad : 0.8 mm ×3) -20 0 20 40 60 80 Ambient temperature (s) 5 100 120 140 160 Ta (°C) 2014-03-01 SSM3K310T RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. • PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). 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