TA1360ANG

TA1360ANG TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA1360ANG YCbCr/YPbPr Signal and Sync Processor for Digital TV, Progressive Scan TV and Double Scan TV The TA1360ANG integrates an analog component signal (YCbCr/YPbPr) processor and sync processor in a 56-pin shrink DIP plastic package. The IC is ideal for digital TVs, progressive TVs, and double scan TVs. The luminance block and the color difference block incorporate the high performance signal processing circuits. The sync processor block supports 525I/60, 625I/50, 525P/60, 625P/50, 1125I/50, 1125I/60, 750P/60, (750P/50), PAL100 Hz, NTSC120 Hz, and SVGA/60(VESA). The TA1360ANG incorporates the I2C bus. The device can control various functions via the bus line. Weight: 5.55 g (typ.) Features Luminance Block • • • • • • • • • • • • • • • • • • • • • • • Black stretch circuit and DC restoration rate correction circuit Dynamic γ correction circuit (gray scale correction) SRT (LTI) Y group delay correction (shoot balance correction) High-bright color circuit Color detail enhancer (CDE) White pulse limiter (WPL) VSM output Flesh color correction Dynamic Y/C correction circuit Color SRT (CTI) Color γ circuit Green stretch Blue stretch OSD blending SW ACB (only black level) Two analog RGB inputs Horizontal sync (15.75 k, 28.125 k, 31.5 k, 33.75 k, 37.9 k, 45 kHz) Vertical sync (525I/P, 625I/P, 750P, 1125I/P, PAL 100 Hz/NTSC 120 Hz 2- and 3-level sync separator circuit HD/VD input (positive and negative polarities) Copy guard Vertical blanking Color difference Block Text Block Synchronization Block 1 2005-08-18 TA1360ANG Block Diagram DEF/DAC GND DEF/DAC VCC Cb1/Pb1 IN Cr1/Pr1 IN Cb2/Pb2 IN 9 19 Y/C VCC 55 Y/C GND 6 RGB VCC 40 RGB GND 44 SCL 30 SDA 31 DAC2 36 (ACB PLUSE) DAC1 (SYNC OUT) 28 CP OUT 18 SCP IN 17 H-OUT 26 H-FREQ SW1 13 H-FREQ SW2 22 HVCO 21 AFC FILTER 20 25 29 32 3 4 CLAMP 5 CP1 SW 8 10 CLAMP I CBUS DECODER SW DAC2 SW DAC1 SYNC OUT 2 YHDPbPr/YCbCr→ YUV CONVERT U V Y BLACK STRETCH UV→ IQ CONVERTER BLACK LEVEL FLESH CORECTION COLOR IQ→ UV CONVERTER SW Y/C LEVEL COMP CP/BPP H DUTY EXT BPP BPP SW GREEN STRETCH TINT DL/ COLOR SRT CP SW CP1 COLOR + H-BPP V-BPP UNI-COLOR CP2 RELATIVE PHASE/ AMPLITUDE G-Y MATRIX B-Y R-Y G-Y COLOR γ V-BLK HALF TONE /C MUTE HI-BRIGHT COLOR Yout-γ HALF TONE /Y MUTE COLOR PEAK DETECT CLAMP WPL V FREQUENCY SW ACB PULSE EXT V-BLK H-BLK + WPS DYNAMIC γ Cr2/Pr2 IN I2L VDD I L GND Y1 IN Y2 IN 2 BLACK PEAK DETECT 2 BPH FILTER DARK DET LIGHT DET 1 DARK AREA DET FILTER LIGHT AREA 7 DET FILTER 56 APL FILTER DC REST SHARPNESS DELAY LINE SRT GROUP DELAY + CORRECTION SHARPNESS CONTROL APL DETECT H FREQUENCY SW HORIZONTAL PHASE H CURVE CORRECTION EXT CP H C/D HVCO H-AFC CP2 CLAMP PULSE + SUBCONTRAST UNICOLOR Y DETAIL CONTROL CDE H CURVE 23 CORRECTION FBP IN 24 VP OUT 27 VP OUT CLAMP PULSE HD POLARITY FBP/BLK H-RAMP 2 × fH BRIGHTNESS ABCL AMP 53 ABCL IN V C/D SYNC IN 14 HD IN 16 SYNC SEPA HD IN SW 11 COLOR LIMITER HPF VSM AMP VSM MUTE 12 VSM FILTER 54 VSM OUT 39 ANALOG OSD R IN 38 ANALOG OSD G IN 37 ANALOG OSD B IN 51 YS1 (ANALOG OSD) V INTEGRAL V-CLP WP BLUE CP2 CLAMP Y VD IN 15 R OUT 43 G OUT 42 B OUT 41 VD IN SW CP2 RGB OUT BLK CLAMP DRIVE RGB MATRIX MIXER SW/ BLUE BACK OSD AMP CP2 OSD ACL SW SW S/H CUT OFF BLUE STRETCH CP2 RGB BRIGHTNESS CLAMP OR CLAMP YM SW 50 YS2 (ANALOG OSD) IK RGB CONTRAST 48 R S/H 47 G S/H 46 B S/H 35 ANALOG R IN 34 ANALOG G IN 33 ANALOG B IN 49 YS3 (ANALOG RGB) 52 YM/PMUTE/BLK 45 IK IN 2 2005-08-18 TA1360ANG Pin Assignment DARK AREA DET FILTER BPH FILTER Y1 IN Cb1/Pb1 IN Cr1/Pr1 IN Y/C GND LIGHT AREA DET FILTER Y2 IN Cb2/Pb2 IN 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 TA1360ANG 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 APL FILTER Y/C VCC VSM OUT ABCL IN YM/P-MUTE/BLK YS 1 (analog OSD) YS 2 (analog OSD) YS 3 (analog RGB) R S/H G S/H B S/H IK IN RGB GND R OUT G OUT B OUT RGB VCC ANALOG OSD R IN ANALOG OSD G IN ANALOG OSD B IN DAC2 (ACB pluse) ANALOG R IN ANALOG G IN ANALOG B IN I2L GND SDA SCL I2L VDD Cr2/Pr2 IN 10 COLOR LIMITER 11 VSM FILTER 12 H-FREQ SW1 13 SYNC IN 14 VD IN 15 HD IN 16 SCP IN 17 CP OUT 18 DEF/DAC VCC 19 AFC FILTER 20 HVCO 21 H-FREQ SW2 22 H CURVE CORRECTION 23 FBP IN 24 DEF/DAC GND 25 H-OUT 26 VP OUT 27 DAC1 (SYNC OUT) 28 3 2005-08-18 TA1360ANG Pin Functions Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 55 1 100 kΩ Connects filter for detecting dark area. DARK AREA DET Voltage of this pin controls FILTER dynamic γ circuit gain for dark area. 1 1 kΩ 5 kΩ DC 1 kΩ 6 55 Connects filter for detecting black peak. 2 BPH FILTER Voltage of this pin controls black stretch gain. Leaving Y open and setting the test circuit SW 2 = C enable to monitor H/V-BPP (black-stretch-stop pulse) width. 4 kΩ 2 200 Ω 1 kΩ 1 kΩ DC 1 kΩ 5V 6 1 Vp-p (including sync) at 100% color bar 40 3 4 5 1 kΩ 1 kΩ or 5 kΩ 3 Y1 IN Inputs Y1 signal via clamp capacitor. 6 4 5 6 Cb1/Pb1 IN Cr1/Pr1 IN Y/C GND Inputs Cb1/Pb1 signal via clamp capacitor. Inputs Cr1/Pr1 signal via clamp capacitor. GND pin for Y/C block ⎯ 700 mVp-p at 100% color bar for Cb1/Pb1 700 mVp-p700 mVp-p at 100% color bar for Cr1/Pr1 ⎯ 55 7 LIGHT AREA DET FILTER Connects filter for detecting light area. Voltage of this pin controls dynamic γ circuit gain for light area. 7 1 kΩ 100 kΩ 5 kΩ DC 1 kΩ 6 4 2005-08-18 TA1360ANG Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 1 Vp-p (including sync) at 100% color bar 40 Inputs Y2 signal via clamp capacitor. 8 9 10 1 kΩ 1 kΩ 5 kΩ or 8 Y2 IN 6 9 10 Cb2/Pb2 IN Cr2/Pr2 IN Inputs Cb2/Pb2 signal via clamp capacitor. Inputs Cr2/Pr2 signal via clamp capacitor. 700 mVp-p at 100% color bar for Cb1/Pb1 700 mVp-p700 mVp-p at 100% color bar for Cr1/Pr1 40 7 µA 11 COLOR LIMITER Connects filter for detecting color limit. 11 5 kΩ DC 6 12 Connects VSM output filter. 12 VSM FILTER Connect 0.01-µF capacitor between this pin and GND. 200 Ω 200 Ω 1 kΩ 40 DC 1 kΩ 54 1.6 mA 6 19 Switches horizontal frequency (Switch 1). Leave this pin open when horizontal frequency is switched by Bus controlling. Controlling this pin prevails over Bus control. (Refer to Table 1: Bus control function.) When this IC is used for CRT, connect this pin to DEF VCC (pin 19) or DEF GND (pin 25). If it is not necessary to control this pin on CRT, connect this pin directly to DEF VCC or DEF GND on the PCB. 50 µA 13 1 kΩ 50 kΩ 13 H-FREQ SW1 DEF VCC or DEF GND 30 kΩ 25 White 100%: 1 Vp-p 19 1 kΩ 14 SYNC IN Inputs Y signal with sync signal via clamp capacitor. 14 1 kΩ or 1 kΩ 60 kΩ 25 5 2005-08-18 TA1360ANG Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 19 Threshold : 0.75 V 0V 15 VD IN Inputs vertical sync VD signal. Inputs positive- or negative-polarity signals. 15 1 kΩ or 45 kΩ 25 Threshold : 0.75 V 0V 19 Threshold : 0.75 V 0V 16 HD IN 50 kΩ Inputs horizontal sync HD signal. Inputs positive- or negative-polarity signals. 16 1 kΩ or 25 Threshold : 0.75 V 0V 19 Inputs SCP from up converter. Input signals are clamp pulse (CP) and black peak detection stop pulse (BPP). 5 kΩ 50 kΩ 17 SCP IN 17 2.2 V to 2.8 V : BPP 4.2 V to 9 V : CP 25 19 5V 2.5 kΩ 18 CP OUT Outputs internal clamp pulse (CP). 18 200 Ω 0V 25 VCC pin for DEF/DAC block. 19 DEF/DAC VCC See “Maximum Ratings” about the voltage. ⎯ ⎯ 19 20 AFC FILTER Connects filter for detecting AFC. 7.5 kΩ 20 300 Ω 30 kΩ VCO DC 6.3 V 25 19 2 kΩ 21 HVCO Connects ceramic oscillator for horizontal oscillation. Use Murata “CSBLA503KECZF30”. 21 1 kΩ ⎯ 1 kΩ 10 kΩ 25 6 2005-08-18 TA1360ANG Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 19 Switches horizontal frequency (Switch 2). Leave this pin open when horizontal frequency is switched by Bus controlling. Controlling this pin prevails over Bus control. (Refer to Table 1: Bus control function.) When this IC is used for CRT, frequency of horizontal output (pin 26) is controlled according to voltage of this pin. DC voltage that is generated by dividing resistor of DEF VCC (pin 19) should be used to control this pin. 60 kΩ 1 kΩ 60 kΩ 60 kΩ 15 kΩ 22 H-FREQ SW2 22 1 kΩ 30 kΩ 7.5 V 4.5 V 1.5 V At BUS control (horizontal frequency) : output voltage value 28 k/15 kHz : DC 9 V 31 kHz : DC 6 V 33 kHz : DC 3 V 37 k/45 kHz : DC 0 V At pin 22 control, horizontal frequency and input voltage value 0 to 1.0 V : 37 k/45 kHz 2.0 V to 4.0 V : 33 kHz 5.0 V to 7.0 V : 31 kHz 8.0 V to 9.0 V : 28 k/15 kHz 20 pF 16 kΩ 25 19 Adjusts screen curve at high voltage fluctuation. Input AC component of high voltage fluctuation. When not used, connect 0.01-µF capacitor between this pin and GND. 65 kΩ 50 kΩ 23 H CURVE CORRECTION 23 1 kΩ DC 25 kΩ 6.5 V 130 kΩ 25 19 2.25 V max: 9 V 20 kΩ H-AFC threshold : 5.3 V BLK threshold : 2.3 V 24 FBP IN Inputs FBP for horizontal AFC. Sets H-BLK width. 24 500 Ω 30 kΩ 5V 25 ⎯ 25 DEF/DAC GND GND pin for DEF/DAC block ⎯ 19 26 H-OUT Horizontal output pin. Open-collector output. 26 5 kΩ 25 19 200 µA Outputs vertical pulse. Applying current to this pin, performs external blanking by OR-ing with internal blanking. Note: Changing H-position varies VP output width. Use the start phase only for VP output. 200 Ω VP output: 5V 27 VP OUT 27 0V 32 25 Start phase V-BLK input current: 780 µA to 1 mA 7 2005-08-18 TA1360ANG Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 19 Outputs 1-bit DAC or separated SYNC. Open-collector output. 500 Ω DC or SYNC OUT 28 DAC1 (SYNC OUT) 28 32 25 VDD pin for I2L block. Connects 2 V (typ.). 29 I2L VDD Supply power via zener diode through resistor from pin 19. (See “Application Circuit”.) ⎯ ⎯ 19 2.25 V 30 SCL SCL pin for I2C BUS 30 5 kΩ SCL ⎯ 25 32 19 ACK 2.25 V 31 SDA SDA pin for I2C BUS 31 50 Ω 5 kΩ SDA ⎯ 25 32 32 I2L GND GND pin for I2L block ⎯ ⎯ 40 33 ANALOG B IN Inputs analog R/G/B signal via clamp capacitor. 33 34 35 1 kΩ 1 kΩ 1 kΩ 44 100 IRE: 0.7 Vp-p (not including sync) 34 ANALOG G IN 35 ANALOG R IN 40 DC or ACB PULSE DAC2 (ACB pulse) Outputs 1-bit DAC or pulse over ACB period. Open-collector output. 36 500 Ω 36 44 8 2005-08-18 TA1360ANG Pin No. Pin Name Function Interface Circuit Input Signal/Output Signal 40 37 ANALOG OSD B IN 37 38 39 1 kΩ 1 kΩ 1 kΩ 44 100 IRE: 0.7 Vp-p (not including sync) 38 ANALOG OSD G IN Inputs analog OSD signal via clamp capacitor. 39 ANALOG OSD R IN VCC pin for text/RGB block. 40 RGB VCC See “Maximum Ratings” about the supply voltage. ⎯ ⎯ 40 100 Ω 41 B OUT Outputs R/G/B signal. 42 G OUT Recommended output amplitude: 100 IRE = 2.3 Vp-p 41 42 43 200 Ω 100 IRE: 2.3 Vp-p Conditions: UNI-COLOR = max SUB-CONT = Cent 2.5 mA Y IN = 0.7 Vp-p 44 44 RGB GND GND pin for text/RGB block。 ⎯ ⎯ 43 R OUT 40 Inputs feedback signal from CRT. (BLK level should be 0 to 3 V.) When ACB function is not used, connect this pin to RGB VCC pin. 45 1 Vp-p (typ.) R 1 kΩ 0 to 3 V or RGB VCC 44 G B 45 IK IN 40 46 B S/H S/H (sample-and-hold) pin. In ACB Mode, connect 2.2-µF capacitor. In CUT-OFF Mode, connect 0.01-µF capacitor. 46 47 48 500 Ω 1 kΩ 5 kΩ DC 3 pF 3V 44 40 47 G S/H 48 R S/H 49 YS3 (analog RGB) Switches internal RGB and external analog RGB input. VSM output is muted when analog RGB is selected. 49 300 Ω 50 kΩ 300 Ω 0 to 0.5 V : Internal 1.5 V to 9 V : Analog RGB, VSM Mute 44 9 2005-08-18 TA1360ANG Pin No. Pin Name Function Switches internal RGB and OSD input signals. The blend ratio of internal RGB and OSD signals can be adjusted according to applying voltage to pins YS1 and YS2. VSM output is muted when YS1 or YS2 pin is set to High. YS2 YS1 51 YS1 (analog OSD) L H L H L L H H Blend ratio Int RGB: OSD RGB 10:0 7:3 5:5 0:10 50 51 300 Ω 40 Interface Circuit Input Signal/Output Signal 50 YS2 (analog OSD) 0 to 0.5 V 50 kΩ : Internal 1.1 V to 1.7 V : VSM Mute 2.9 V to 9 V 44 : OSD, VSM Mute 40 300 Ω 80 kΩ 0 to 0.5 V : Internal 52 YM/P-MUTE/BLK High-speed halftone switch for internal RGB signal. Enables picture mute and blanking. 52 1.2 V to 1.8 V : Half Tone 2 V.7 to 4.0 V : P-Mute 7 V to 9 V : Blanking 10 kΩ 44 40 7.05 V Inputs ABL and ACL signals. 53 ABCL IN Sets gain and start point of ABL and dynamic ABL signal according to bus controlling. 53 30 kΩ 5 kΩ DC 44 Outputs Y signal for VSM that passed through HPF circuit (first differential circuit). Output signals are muted according to pins 49, 50, and 51. VCC pin for Y/C block. 55 Y/C VCC See “Maximum Ratings” about the supply voltage. ⎯ ⎯ 54 VSM OUT See pin 12. ⎯ 55 40 kΩ Connects filter for correcting DC restoration rate. 56 APL FILTER Leaving this pin open enables to monitor Y signal after black stretch and dynamic γ. 56 1 kΩ ⎯ 1 kΩ 6 10 2005-08-18 TA1360ANG Bus Control Map Write Data Slave Address: 88H Sub-Add 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F D-ABL POINT ABL POINT DYNC γ GAIN OSD BRIGHT BS-CHAR1 OSD CONTRAST R-Y/B-Y GAIN G-Y/B-Y GAIN COLOR SRT TRAN C.D.E. VSM PHASE DC REST POINT BLACK STRETCH POINT SRT-GAIN D-ABL GAIN BL STRETCH POINT ABL GAIN STATIC γ GAIN-1 Y/C-DL1 BS-CHAR2 Y/C-DL2 C FREQ GREEN STRETCH HI BRT SUB CONTRAST DRIVE GAIN1 DRIVE GAIN2 R CUT OFF G CUT OFF B CUT OFF R-Y/B-Y PHASE G-Y/B-Y PHASE COLOR γ FLESH CLT H-SHIFT OSD-ACL TINT PICTURE SHARPNESS RGB BRIGHTNESS RGB CONTRAST WPS YUV MODE Y-OUT γ DR-R DR-B/G ACB-MODE D7 H-FREQ1 D6 D5 H-DUTY D4 YUV-SW D3 DAC1 D2 DAC2 D1 SYNC-SW D0 H-FREQ2 CLP-PHS TEST Preset 1000 1000 1000 1000 1000 1000 1000 1000 HBP-PHS2 BLS γ DCRR-SW 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 HORIZONTAL POSITION SCP-SW HBP-PHS1 SYNC SEP-LEVEL V-BLK PHASE COMPRESSION-BLK PHASE-1 P-MODE1 VERTICAL FREQUENCY COMPRESSION-BLK PHASE-2 UNI-COLOR BRIGHTNESS COLOR Y/C GAIN COMP BL STRETCH GAIN VSM GAIN DC REST RATE APACON PEAK FREQ DC REST LIMIT B.L.C. B.D.L WPL-LEVEL P-MODE2 RGB OUT MODE STATIC γ GAIN-2 DYNC γ AREA WP BLUE POINT WP BLUE GAIN BS-AREA APL VS BSP Y DETAIL CONTROL Y GROUP DELAY CORRECTION Read Data Slave Address: 89H D7 0 POR D6 IK-IN D5 RGB-OUT D4 YUV-IN D3 H-OUT D2 VP-OUT D1 RGB-IN D0 SYNC-IN 11 2005-08-18 TA1360ANG Bus Control Features Write Mode Resister Name H-FREQ1/2 H-DUTY Description Switches horizontal oscillation frequency. (See the appendix 1) Switches horizontal output duty. 0: 41% 1: 47% Preset Value 33.75 kHz 41% YUV-SW Switches YUV input. 0: INPUT-1 (Y1/Cb1/Cr1) 1: INPUT-2 (Y2/Cb2/Cr2) INPUT-1 Switches DAC controlling output. DAC 1 0: OPEN (high) 1: ON (low) OPEN Controls 1-bit DAC of open-collector when TEST is 00. Outputs H/C-SYNC from pin 28 when TEST is 01. Switches DAC controlling output. DAC 2 0: ON (low), 1: OPEN (high) Controls 1-bit DAC of open-collector when TEST is 00. Outputs ACB reference pulse from pin 36 when TEST is 01. ON SYNC-SW Switches sync input. 0: Selects HD/VD input. 1: Selects SYNC input. HD/VD Adjusts horizontal picture position (phase). HORIZONTAL POSITION 0000000: −12.5% 1111111: +12.5% CENTER Note: VP output width (pin 27) varies with a change of horizontal position. Switches clamp pulse phase. 0: 0.7-µs (2.5%) width, 1.1-µs (3.8%) delay from HD stop phase. CLP-PHS 1: 0.7-µs (2.4%) width, 0.2-µs (0.7%) delay from HD stop phase when no signal, 0.8-µs (2.7%) width that is 1.2-µs (4.2%) delay from FBP start phase. Also switches CP phase of CP-OUT (pin 18). Sets ACB mode; Sets converged reference level. ACB MODE 00: ACB OFF (cutoff BUS control), 01: ACB ON (5 IRE), ACB ON (10 IRE) 1.1-µs delay 10: ACB ON (10 IRE) 11: ACB ON (20 IRE) SCP-SW SCP (sand castle pulse) Switches modes. 0: Internal Mode 1: External input Mode Switches phase of black-stretch-detection stop pulse. HBP-PHS1 = 0 and HBP-PHS2 = 0: FBP ± 3% HBP-PHS1 = 0 and HBP-PHS2 = 1: FBP ± 8% HBP-PHS1/2 HBP-PHS1 = 1 and HBP-PHS2 = 0: FBP ± 13% HBP-PHS1 = 1 and HBP-PHS2 = 1: FBP ± 18% Leaving Y open and setting the test circuit SW 2 to C enable to monitor H/V-BPP (black-stretch-detection stop pulse) width through pin 2. SYNC SEP-LEVEL Switches Sync SEP-level. 00: 16% Test Mode: Controls 1-bit DAC of open-collector when TEST is 00. TEST 01: 24% 10: 32% 11: 40% (At 1125I/60) Internal Mode ±3% 16% Outputs H/C-SYNC from pin 28, and ACB reference pulse from pin 36 when TEST 00 is 01. Do not set TEST to 10/11 for that is shipment TEST Mode. 12 2005-08-18 TA1360ANG Resister Name Switches vertical BLK stop phase. V-BLK PHASE 00000: 16 H~ 11110: 46 H (1 H/STEP) 32 H Description Preset Value 11111: Internal H/V-BLK OFF Please set ACB Mode to OFF when internal H/V-BLK is OFF (11111). V-FREQUENCY COMPRESSION-BLK PHASE-1/2 P-MODE1/2 UNI-COLOR Vertical free-run frequency: Sets V pull-in range. (See Appendix 2.) Compression BLK phase: Sets BLK for upper and lower parts of screen. (See Appendix 3.) Picture Mode: Sets picture mute, halftone, blue background, and Y mute. (See Appendix 4.) Unicolor adjustment: 0000000: −16dB~ 1111111: 0dB 1281 H CENTER, OFF P-MUTE 1 min BRIGHTNESS Brightness adjustment: 00000000: −40 IRE OSD-ACL; 0: OFF 1: ON 11111111: +40 IRE CENTER OSD-ACL ON Color adjustment: COLOR 0000000: COLOR MUTE, 0000001: −20dB or more TINT Tint adjustment: 0000000: −32 deg~ Sharpness adjustment: PICTURE-SHARPNESS 0000000: −10dB or more 1000000: +10dB CENTER 1111111: +32 deg 1111111: +4dB ±0 deg C-MUTE 1111111: +17.5dB (at peak FREQ) BLSγ Blue stretch γ correction: B-axis correction 0: OFF 1: ON OFF RGB-BRIGHTNESS RGB brightness: 0000000; −20 IRE~ 1111111; +20 IRE CENTER DCRR-SW Switches DC restoration rate. 0: 100% or higher High-bright color: 0: OFF 1: ON 1: 100%or lower 100% or higher HI BRT ON RGB-CONTRAST RGB contrast: 0000000: −16.5dB Sub-contrast: 00000: −3.3dB WPS level: 0: 110 IRE 1: 130 IRE 11111: +2.5dB 1111111: 0dB min SUB-CONTRAST CENTER WPS 110 IRE Y/color-difference input Mode: YUV MODE 0: Y/Cb/Cr, 1: Y/Pb/Pr (Remarks) Y/Cb/Cr: ITU-R BT 601 Y/Pb/Pr: ITU-R BT 709 (1125/60/2:1) Y-outγ Ｙ-out gamma control: 0: OFF 1: ON OFF Y/Cb/Cr DRIVE GAIN1/2 DR-R DR-B/G Drive gain 1/2; 0000000: −5dB 1111111: +3dB Switches RGB drive gain base. (See Appendix 5.) CENTER R 13 2005-08-18 TA1360ANG Resister Name R/G/B cutoff: 1) At ACB-OFF RGB-OUT R/G/B CUT OFF 00000000: 1.9 V 11111111: 2.9 V CENTER Description Preset Value 2) At ACB-ON SENS-IN 00000000: 0.5 Vp-p 11111111: 1.5 Vp-p R-Y/B-Y GAIN Switches R-Y/B-Y relative amplitude: 0000: min (0.45) 1111: max (0.9) CENTER R-Y/B-Y PHASE Switches R-Y/B-Y relative phase: 0000: min (90 deg) 1111: max (111.5 deg) min G-Y/B-Y GAIN Switches G-Y/B-Y relative amplitude: 0000: min (0.25) 1111: max (0.48) CENTER G-Y/B-Y PHASE Switches G-Y/B-Y relative phase: 0000: min (232 deg) 1111: max (254 deg) min COLOR SRT TRAN Color SRT transient: Color-difference transient improvement 00: C-SRT OFF~ 11: max CENTER C FREQ Color SRT peak frequency: 0: 4.5 MHz Green stretch: 00: OFF~ 11: max (+3dB) Color γ correction point 00: OFF, 01: 0.23 Vp-p, 10: 0.40 Vp-p, Color limiter level: 0: 1.65 Vp-p, 1: 2 Vp-p Color detail enhancer: 00: min 11: max Dynamic Y/C compensation: Operated when luminance level is made up according to dynamic Yγ. 00: OFF~ 11: max 11: 0.58 Vp-p 1: 5.8 MHz 4.5 MHz GREEN STRETCH OFF COLOR γ OFF CLT 1.65 Vp-p CDE CENTER Y/C GAIN COMP OFF BL STRETCH GAIN Blue stretch gain: B-axis correction 00: OFF 11: max (+6.4dB) Flesh color: Skin tone correction 0: OFF 1: ON (Lead-in angle: ±33.7 deg) OFF FLESH OFF H-SHIFT Shifts a center of horizontal picture position (phase): 0: OFF 1: ON（FBP shifts 6.7% against HD） OFF VSM-PHASE VSM phase: 000: −37.5 ns VSM gain: 000: OFF 001: 0 dB~ APACON peak frequency: 00: 13.5 MHz 01: 9.5 MHz 10: 7.2 MHz 11: 4.5 MHz 111: +16dB (VSM gain is limitted 1.4 Vp-p) 101: normal 111: +15 ns CENTER VSM GAIN OFF APACON PEAK f0 13.5 MHz DC REST POINT DC restoration rate correction point: 000: 0% 111: 49% CENTER DC REST RATE DC restoration correction rate: 000: 100% 111: 135% (70%) DC restoration rate correction limit point: 00: 67% 01: 77％ 10: 80% 11: 80% min DC REST LIMIT min 14 2005-08-18 TA1360ANG Resister Name BLACK STRETCH POINT Black stretch start point 1: 000: OFF 001: 25 IRE~ Black stretch start point 2: 00: 0 IRE 11: 46 IRE up (at APL 100%) 111: 55 IRE Description Preset Value CENTER APL VS BSP 0 IRE B.L.C Black level automatic correction: Up to 6.5 IRE. (Black stretch takes priority.) 0: OFF 1: ON OFF B.D.L. Switches black detection level: 0: 3 IRE 1: 0 IRE 3 IRE BS-AREA Black stretch area reinforcement: 0: ON 1: OFF ON SRT-GAIN SRT gain; Y transient improvement (LTI) 00000: min 11111: max White letters improvement amplitude; 000: min (21 IRE) ~ 110: max (102 IRE) 111: OFF CENTER WPL-LEVEL min D-ABL POINT Dynamic ABL detection voltage 00: min 11: max Dynamic ABL sensitivity 00: min 11: max Blue stretch point; B-axis correction 00: min (28 IRE) 11: max (60 IRE) CENTER D-ABL GAIN min BL STRETCH POINT min ABL POINT ABL detection voltage 000: min 111: max ABL sensitivity 000: min 111: max RGB output mode; RGB output mode SW for test and adjustment 00: Normal 01: R only 10: G only 11: B only CENTER ABL GAIN min RGB-OUT MODE Normal Dynamic Yγ gain vs dark area; dynamic γ-correction according to dark area. DYNCγ GAIN 00:min~ 11: max (Maximum gain is +6dB included Static Yγ gain for dark area.) Black stretch characteristic swich BS-CHAR1/2 BS-CHAR1 = 0 and BS-CHAR2 = 0: OFF BS-CHAR1 = 0 and BS-CHAR2 = 1: min BS-CHAR1 = 1 and BS-CHAR2 = 0: mid BS-CHAR1 = 1 and BS-CHAR2 = 1: max Static Yγ dark area gain; γ correction for dark area STATICγ GAIN-1 000: OFF 001: min (−5dB) ~ 11: max (+2.4dB) OFF OFF CENTER Note: When STATIC γ GAIN-1 is 000(OFF), set DYNC γ GAIN to min (00), STATIC γ GAIN-2 to OFF (11), and DYNC γ AREA to min (000). Static Yγ light area gain; γ correction for light area STATICγ GAIN-2 00: max (−8.8dB)~ 11: OFF max When 00~10 is set, light area static Yγ and light dynamic Yγ according to light area is operated. OSD BRIGHT OSD brightness: 00: 5 IRE 01: 0 IRE 10: −5 IRE 11: −10 IRE −5 IRE OSD-CONTRAST OSD contrast: 00: min (1.7dB) 11: max (0dB) min 15 2005-08-18 TA1360ANG Resister Name Description Adjusts Y/C phase; adjusts the phase Y before passing through matrix circuit. Y/C DL1/2 Y/C DL2 = 0 and Y/C DL1 = 0: −10 ns, Y/C DL2 = 0 and Y/C DL1 = 1: −5 ns Y/C DL2 = 1 and Y/C DL1 = 0: 0 ns, Y/C DL2 = 1 and Y/C DL1 = 1: +5 ns DYNCγAREA Dynamic γ dark area detection sensitivity; switches detection sensitivity of dynamic Yγ of dark area. min 000: min~ 111: max Controls Y detail; corrects sharpness of 5.0-MHz peak frequency. 0000:min (trap) 1111: max（+6dB） CENTER −10 ns Preset Value Y DETAIL CONTROL WP BLUE POINT White peak blue point; 000: OFF 001: min (42 IRE) ~ 111: max (106 IRE) Y group delay correction; shoot balance correction. OFF Y-GROUP DELAY CORRECTION 0000: Pre-shoot gain is lowered. (Overshoot gain is raised.) 1111: Overshoot gain is lowered. (Pre-shoot gain is raised.) CENTER WP BLUE GAIN White peak blue gain. 000: min (+3dB) 111: max (+10dB) min 16 2005-08-18 TA1360ANG Appendix 1: Horizontal Frequency Pin Voltages (V) Pin 13 Pin 22 DEF VCC (8.0~9.0) DEF GND (0~1.0) 6.0 (5.0~7.0) 3.0 (2.0~4.0) DEF GND (0~1.0) DEF VCC (8.0~9.0) DEF VCC (8.0~9.0) 6.0 (5.0~7.0) 3.0 (2.0~4.0) DEF GND (0~1.0) 00-D0 0 0 0 0 1 1 1 1 Bus Data 00-D7 0 0 1 1 0 0 1 1 00-D6 0 1 0 1 0 1 0 1 H-Frequency (kHz) 28.125 31.5 33.75 37.9 15.75 31.5 33.75 45 Note 1: Controlling pins prevails over BUS control. When the TA1360N is used for CRT, control horizontal oscillation frequency by pins 13 and 22. (See the pin descriptions for details.) Note 2: Horizontal output frequency may not be switched at once but may takes two steps if switching pins 13 and 22 is controlled at the same time. Switching horizontal output frequency may cause deterioration of the horizontal transistor. Thus, be sure to take account of applications, included software. Appendix 2; Vertical Frequency Data 000 001 010 011 100 101 110 111 V Pull-in Range 48~1281 H 48~849 H 48~725 H 48~660 H 48~613 H 48~363 H 48~307 H VP-OUT HI V-BPP Start Phase 1100 H 730 H 600 H 545 H 500 H 290 H 240 H ⎯ ⎯ V-BLK P. (C.BLK P.) +20 H Stop Phase Example of Format/V (H)-Frequency 1125P/30 Hz (33.75 kHz) 750P/60 Hz (45 kHz) (750P/50Hz(37.5 kHz)) 625P/50 Hz (31.5 kHz) SVGA/60 Hz(37.9 kHz) 1125I/50 Hz (28.125 kHz) 1125I/60 Hz (33.75 kHz) 525P/60 Hz (31.5 kHz) PAL/SECAM/50 Hz (15.625 kHz), 100 Hz (31.5 kHz) NTSC/60 Hz (15.734 kHz), 120 Hz (31.5 kHz) ⎯ 17 2005-08-18 TA1360ANG Appendix 3; Compression-BLK Phase V-Frequency 000 001 010 011 100 101 110 111 Phase-1 (start phase) * 1088 H~1116 H 720 H~748 H 592 H~620 H 528 H~556 H 488 H~516 H 280 H~308 H 224 H~252 H C-BLK OFF 50~78 H (0000: C-BLK2 OFF) Phase-2 (stop phase) *: C-BLK1 = 1111: C-BLK1 OFF Appendix 4; P-Mode 05-D7 1A-D1 1A-D0 MODE Description P-Mute and halftone the main signal by pin YM. 0 0 0 NORMAL 1 Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-mute process is executed on Y of main signal by BUS. 0 0 1 Y-MUTE Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-halftone process is executed on main signal by BUS. 0 1 0 YM 1 Insert P-Mute by pin YM, and analog RGB-IN by Ys3. Ys1/Ys2 blends OSD-IN and main halftone signal. Analog RGB-IN > P-Mute Blue background process is executed on main signal by BUS. 0 1 1 BB Insert P-Mute by pin YM, analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2 Analog RGB-IN > P-Mute Full-screen-mute process is executed on main signal by BUS. 1 0 0 P-MUTE 1 Insert analog RGB-IN by Ys3, and OSD-IN by Ys1/Ys2. Analog RGB-IN > P-Mute Full-screen-halftone process is executed on main signal by BUS. 1 0 1 YM 2 Insert P-Mute by pin YM, and analog RGB-IN by Ys3. Ys1/Ys2 blends OSD-IN and main halftone signal P-Mute > Analog RGB-IN Full-screen-mute process is executed on main signal and analog RGB-IN by BUS. 1 1 0 P-MUTE 2 Insert OSD-IN by Ys1/Ys2. P-Mute > Analog RGB-IN P-Mute and halftone process is executed on the main signal by pin YM. 1 1 1 NORMAL 2 Analog RGB-IN is inserted by Ys3, and OSD-IN by Ys1/Ys2. P-Mute > Analog RGB-IN Output priority; (000)~(100): Main signal < BB < P-MUTE < RGB-IN < OSD-IN (101)~(111): Main signal < BB < RGB-IN < P-MUTE < OSD-IN 18 2005-08-18 TA1360ANG Appendix 5; DR-R, DR-B/G DR-R 0 0 1 1 DR-B/G 0 1 0 1 Reference Axis R R G B Drive Gain1 G G R G Drive Gain2 B B B R Read Function Signal Power-on reset: POR 0: RESISTER PRESET 1: Normal Function After power on, 0 is returned at first read; 1, at second and subsequent reads. IK-IN Detects IK input; detects input through pin 45. 0: NG (no signal) 1: OK (signal detected) Detects RGB-OUT self-check; detects output of pins 41, 42, 43. RGB-OUT 0: NG (no signal) 1: OK (signal detected) Detects signal when all three outputs hsve signals. Small signals are not detected. Detects YUV-IN self-check; detects input of pins 3, 4, 5 or pins 8, 9, 10. YUV-IN 0: NG (no signal) 1: OK (signal detected) Detects signal when all three inputs are AC signals. Small signals or signals like DC voltage are not detected. H-OUT Detects H-OUT self-check; detects output of pin 26. 0: NG (no signal) 1: OK (signal detected) VP-OUT Detects VP-OUT self-check; detects output of pin 27. 0: NG (no signal) 1: OK (signal detected) Detects RGB-IN self-check; detects input of pins 33, 34, 35. RGB-IN 0: NG (no signal) 1: OK (signal detected) Detects signal when all three inputs are AC signals. Small signals or signals like DC voltage are not detected. SYNC-IN Detects SYNC-IN self-check; detects input of pin 14. 0: NG (no signal), 1: OK (signal detected) 19 2005-08-18 TA1360ANG How to Transmit/Receive Via I2C Bus Slave Address: 88H A6 1 A5 0 A4 0 A3 0 A2 1 A1 0 A0 0 W/R 0/1 Start and Stop Conditions SDA SCL S Start condition P Stop condition Bit Transfer SDA SCL SDA must not be changed SDA may be changed Acknowledgement SDA from transmitter SDA from receiver High impedance at bit 9 Low impedance only at bit 9 1 S Clock pulse for acknowledgement 8 9 SCL from master 20 2005-08-18 TA1360ANG Data Transmit Format 1 S Slave address 7 bit 0A Sub address 8 bit A Transmit data 9 bit MSB P: Stop condition AP MSB S: Start condition MSB A: Acknowledgement Data Transmit Format 2 S Slave address 0A Sub address ･･････ A Transmit data 1 A A ･･････ AP Sub address Transmit data n Data Receive Format S Slave address 7 bit MSB 1A Receive data 8 bit MSB ΑP To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. The slave receiver changes to a transmitter. The stop condition is always created by the master. Optional Data Transmit Format S Slave address 7 bit MSB 0A1 MSB Sub address 7 bit A Transmit data 1 8 bit MSB ････ Transmit data n 8 bit MSB AP In this way, sub addresses are automatically incremented from the specified sub address and data are set. I2C BUS Conditions Characteristics Low level input voltage High level input voltage Low level output voltage at 3 mA sink current Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Capacitance for each I/O pin SCL clock frequency Hold time START condition Low period of SCL clock High period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition Symbol VIL VIH VOL1 Ii Ci fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Min 0 1.8 0 −10 ⎯ 0 4.0 4.7 4.0 4.7 350 250 4.0 4.7 Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 1.0 Vcc 0.4 10 10 100 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit V V V µA pF kHz µs µs µs µs ns ns µs µs 21 2005-08-18 TA1360ANG Maximum Ratings (Ta = 25°C) Characteristics Power supply voltage (pins 19, 40, 55) Power supply voltage (pin 29) Input pin voltage Power dissipation Power dissipation reduction rate depending on temperature Operating temperature Storage temperature Symbol VCCmax9 VCCmax2 Vin PD (Note 3) 1/θja Topr Tstg min Supply voltage (pins 19, 40, 55) typ. max 2551 20.4 −20 to 65 −55 to 150 8.5 8.8 9.1 PCB A Rating PCB B 12 2.5 GND – 0.3 to VCC + 0.3 2717 21.7 −20 to 65 −55 to 150 8.7 9.0 9.3 3378 27.0 −20 to 65 −55 to 150 8.7 9.0 9.3 V PCB C Unit V V V mW mW/°C °C °C Note 3: See the following Figure A. Note, however, that the conditions apply only to the case where the device is mounted on board A (180 mm × 125 mm × 1.6 mm, one-sided); board B (329 mm × 249 mm × 1.6 mm, two-sided); or board C (276 mm × 192 mm × 1.6 mm, six-layered). When mounting the IC, select boards no smaller than these. When using under the conditions of board A, set the IC’s power supply voltage (pins 19, 40, 55) to 8.8 V (±0.3 V). Because the IC’s thermal capacity margin is narrow, when designing a set, incorporate heat discharge features into the design. Note that the power dissipation varies widely depending on the board mounting conditions. 3378 Printed Circuit Board B 2717 Printed Circuit Board C PD (mW) Power dissipation 2551 2297 1848 1735 Printed Circuit Board A 0 0 25 65 150 Ambient temperature Ta (°C) Figure A Power Dissipation Reduction Curve 22 2005-08-18 TA1360ANG Note 4: Power supply sequence At power-on, power should be supplied to the power supply pins according to the following sequence: 1. Pin 29 (I L VDD) 2. Pin 19 (DEF/DAC VCC) 3. Pins 40 and 55 (RGB VCC/YC VCC) Supply power to pin 29 via zener diode through resistor from pin 19. (See “Application Circuit”.) BUS preset value is become undefined and caused malfunction of the IC unless supplying power to all supply pins or follow the power supply sequence described above. When the frequency of horizontal output (pin 26) became undefined, horizontal transistor may be damaged. When the TA1360N is used for CRT, control horizontal oscillation frequency by pins 13 and 22. V DEF/DAC VCC 2 Horizontal output 6.0 V (typ.) POR release voltage (BUS operation) 4.6 V (typ.) Logic operation 1.3 V (typ.) t I2L VDD Figure B Timing chart that indicates the timing from power-on till horizontal output. (At Ta = 25 C°) 23 2005-08-18 TA1360ANG Operating Conditions Characteristics Pins 19, 40, 55 Pin 29 Y input level Color-difference input level Y input frequency Color-difference input frequency HD/VD input level SYNC input level SCP input level Pins 3, 8: 100% color bar, including sync (Picture period amplitude, 0.7 Vp-p) Pins 4, 5 9, 10: 100% color bar, not including sync Pins 3, 8 Pins 4, 5, 9, 10 Pins 15, 16 Pin 14: 100% color bar, including sync Pin 17 CP BPP At 28 k/31 k/33 k/37 kHz At 15 k/31 k/33 k/45 kHz 28.125 kHz or 15.75 kHz Pin 22 31.5 kHz 33.75 kHz 37.9 kHz or 45 kHz FBP input level FBP input width H-OUT input current DAC input current SCL/SDA pull-up voltage SDA input current Analog RGB input level Analog OSD input level YS3 switching voltage YS1/2 switching voltage Pin 24 Pin 24 Pin 26 Pins 28, 36 Pins 30, 31 Pin 31 Pins 33, 34, 35: White 100% Pins 37, 38, 39: White 100% Pin 49 Pins 51, 50 OSD VSM MUTE BLK YM switching voltage Pin 52 P-MUTE HALF TONE External V-BLK input current Pin 27 H-AFC H-BLK Description Board A (Note 5) Boards B and C (Note 5) Min 8.5 8.7 1.8 ⎯ ⎯ 0 0 2.0 0.9 4.2 2.2 0 8.0 8.0 5.0 2.0 0 6.5 3.0 0.16 ⎯ ⎯ 3.3 ⎯ ⎯ ⎯ 1.5 2.9 1.1 7.0 2.7 1.2 0.78 Typ. 8.8 9.0 2.0 1.0 0.7 ⎯ ⎯ 5.0 1.0 5.0 2.5 0 VCC VCC 6.0 3.0 0 7.0 3.5 ⎯ 9.0 0.3 5.0 ⎯ 0.7 0.7 5.0 5.0 1.5 VCC 3.5 1.5 ⎯ Max 9.1 9.3 2.2 ⎯ ⎯ 30 15 VCC 1.1 VCC 2.8 1.0 VCC VCC 7.0 4.0 1.0 VCC 4.0 0.3 15.0 1.0 VCC 2 ⎯ ⎯ VCC VCC 1.7 VCC 4.0 1.8 1 mA V H mA V mA Vp-p V MHz V Vp-p Vp-p V Unit Supply voltage (VCC) Pin 13 Horizontal frequency switching voltage Note 5: See “Maximum Ratings” about the boards A, B, and C. Electrical Characteristics (unless otherwise specified, VCC = 9 V/2 V, Ta = 25°C) Current Dissipation Pin Name DEF/DAC VCC (9 V) RGB VCC (9 V) I L VDD (2 V) Y/C VCC (9 V) 2 Symbol ICC1 ICC2 ICC3 ICC4 Test Circuit ⎯ ⎯ ⎯ ⎯ Min 19.2 48.8 21.3 36.8 Typ. 24.0 61.0 25.0 46.0 Max 28.2 67.8 29.4 51.1 Unit mA 24 2005-08-18 TA1360ANG Pin Voltage Test Condition (1) (2) BUS = Preset SW1 = B, SW2 = B, SW3 = C, SW4 = B, SW5 = B, SW7 = B, SW8~10 = B, SW14 = B, SW20 = ON, SW23 = B, SW24 = A, SW26 = A, SW33~35 = A, SW37 to 39 = A, SW54 = OFF, SW56 = ON Pin Name DARK AREA DET FILTER BPH FILTER Y1 IN Cb/Pb1 IN Cr/Pr1 IN LIGHT AREA DET FILTER Y2 IN Cb/Pb2 IN Cr/Pr2 IN COLOR LIMITER VSM FILTER SYNC IN VD IN HD IN CP IN AFC FILTER HVCO H CURVE CORRECTION ANALOG B IN ANALOG G IN ANALOG R IN ANALOG OSD B IN ANALOG OSD G IN ANALOG OSD R IN B S/H G S/H R S/H YS3 YS2 YS1 YM ABCL IN VSM OUT APL FILTER Symbol V1 V2 V3 V4 V5 V7 V8 V9 V10 V11 V12 V14 V15 V16 V17 V20 V21 V23 V33 V34 V35 V37 V38 V39 V46 V47 V48 V49 V50 V51 V52 V53 V54 V56 Test Circuit Min ⎯ 5.5 4.7 4.7 4.7 ⎯ 4.7 4.7 4.7 6.65 7.5 1.8 ⎯ ⎯ ⎯ 5.4 4.4 2.2 3.65 3.65 3.65 3.65 3.65 3.65 4.2 4.2 4.2 ⎯ ⎯ ⎯ ⎯ 6.1 4.1 4.8 Typ. 0.09 5.8 5.0 5.0 5.0 0.09 5.0 5.0 5.0 6.9 7.7 2.1 0 0 0 6.2 5.0 2.5 3.95 3.95 3.95 3.95 3.95 3.95 5.2 5.2 5.2 0.1 0.1 0.1 0.1 6.35 4.3 5.0 Max 0.15 6.1 5.3 5.3 5.3 0.15 5.3 5.3 5.3 7.15 7.9 2.4 0.3 0.3 0.3 7.0 5.6 2.8 4.25 4.25 4.25 4.25 4.25 4.25 6.2 6.2 6.2 0.2 0.2 0.2 0.2 6.6 4.5 5.2 V Unit Pin No. 1 2 3 4 5 7 8 9 10 11 12 14 15 16 17 20 21 23 33 34 35 37 38 39 46 47 48 49 50 51 52 53 54 56 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 25 2005-08-18 TA1360ANG Picture Quality (Sharpness) Block Characteristics Y input dynamic range Black detection level shift Black stretch amp maximum gain Black stretch start point 1 Symbol DRY VB VB3 GBS PBST1 PBST2 PBS1 PBS2 PBSC1 PBSC2 Black stretch characteristic switch PBSC3 PBSC4 PBSC5 PBSC6 Black stretch area reinforcement current IBSA DV01 D.ABL detection voltage DV10 DV11 D.ABL sensitivity Black level correction Dark area Yγ correction point Dark area dynamic Yγ gain Dark area static Yγ gain Light area Yγ correction point Light area dynamic Yγ gain Light area static Yγ gain SDAMIN SDAMAX BLC PDGP GDDGMAX GDSGMIN GDSGMAX LPG GLDG GLSGMIN GLSGMAX DAMIN Dark area detection sensitivity DACEN DAMAX ADT100 DC restoration rate ADT135 ADT65 DC restoration point VDT0 VDT1 PDTL60 DC restoration limit PDTL75 PDTL87 PDTL100 Test Circuit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Note P19) (Note P18) (Note P17) (Note P16) (Note P08) (Note P09) (Note P10) (Note P11) (Note P12) (Note P13) (Note P14) (Note P15) (Note P07) (Note P06) (Note P05) Test Condition ⎯ (Note P01) (Note P02) (Note P03) Min 0.7 −15 35 2.4 20 50 0 14 26 −8 26 −5.5 26 −3.5 13 80 240 380 ⎯ 0.25 4.5 25 5.5 −6.5 2 64 1.1 0.3 1.4 0.25 0.88 0.95 0.9 1.2 0.55 −5 47 64 74 74 74 Typ. 1.0 10 45 2.8 25 55 5 21 28 −6 28 −3 28 −2 18 120 280 420 0.01 0.28 6.5 28 6 −5 2.4 74 1.7 0.6 1.7 0.3 0.98 1.05 1.1 1.35 0.70 0 49 67 77 80 80 Max 1.5 15 55 3.2 35 60 10 30 30 −4 30 −1 30 −0.5 23 160 320 460 0.02 0.31 8.5 33 6.5 −4 2.6 80 2.3 0.9 2.3 0.37 1.08 1.15 1.2 1.5 0.85 5 55 70 80 82 82 % % times V V/V IRE IRE dB dB IRE dB dB mV µA IRE Unit Vp-p mV dB IRE Black stretch start point 2 (Note P04) IRE 26 2005-08-18 TA1360ANG Characteristics Symbol FAP00 Sharpness control peak frequency FAP01 FAP10 FAP11 DC fluctuation at switching sharpness control peak frequency VRDC GMAX00 GMIN00 GMAX01 Sharpness control range GMIN01 GMAX10 GMIN10 GMAX11 GMIN11 GCEN00 Sharpness control center characteristic GCEN01 GCEN10 GCEN11 TSRT00 2T pulse response SRT control TSRT01 TSRT10 TSRT11 VSM peak frequency FVSM GV000 GV001 GV010 VSM gain GV011 GV100 GV101 GV110 GV111 VSR49 VSM mute threshold voltage VSR50 VSR51 VSM limit Y input to R output delay time VLU VLD TYR YDLA Y delay time switch YDLB YDLC GAMIN Y group delay correction GBMIN GAMAX GBMAX Test Circuit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Note P27) (Note P26) ⎯ (Note P25) Pins 49, 50, 51 (Note P24) ⎯ (Note P23) (Note P22) (Note P21) (Note P20) ⎯ Test Condition Min 10.5 7 5 3.5 ⎯ 15 −4 15 −5 15 −7 15 −12 7 7 7 7 0.9 3.5 6.7 11.5 19 ⎯ −2 3.7 7.1 8.9 11.4 13.5 14.8 0.62 0.62 0.62 0.55 0.55 110 3 7 10 −4 2.5 1 −5 Typ. 13.5 9.5 7.2 4.5 0.01 17.5 −0.6 17.5 −0.3 17.5 −2.5 17.5 −5 10 10 10 10 1.6 4.8 8.5 12.5 19.5 −40 −1.2 4.6 8.2 10.5 12.6 14.4 15.7 0.78 0.78 0.78 0.66 0.66 125 5 10 15 −2.5 3 1.7 −4 Max 17 12 7.8 6.3 0.02 19 2.5 19 2.5 19 1.5 19 0 13 13 13 13 2.7 7.1 11.3 15.5 25.5 −35 −0.4 5.5 9.3 12.1 13.8 15.3 16.6 0.85 0.85 0.85 0.75 0.75 145 10 15 25 −1 3.5 2.4 −2 dB ns Vp-p ns V dB MHz dB dB dB V MHz Unit 27 2005-08-18 TA1360ANG Characteristics Symbol GCDE00 Color detail enhancer GCDE01 GCDE10 GCDE11 Y detail frequency FYD GYDMAX Y detail control range GYDCEN GYDMIN Test Circuit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Note P29) ⎯ (Note P28) Test Condition Min 9 9 9 9 4 11 8 3 Typ. 10 10 10 10 5 13 10 5 Max 11 11 11 11 6 15 12 7 dB MHz dB Unit 28 2005-08-18 TA1360ANG Color Difference Block 1: YUV input and matrix Characteristics Color difference input dynamic range Symbol DRB DRR TRMAX Color difference tint control characteristic TRMIN TBMAX TBMIN FB00 Color SRT peak frequency FB01 FR00 FR01 GSB00CEN GSB00MAX GSB01CEN Color SRT gain GSB01MAX GSR00CEN GSR00MAX GSR01CEN GSR01MAX Cb1 input to B output delay time Cr1 input to R output delay time TB TR GCBDY1 Dynamic Y/C compensation GCBDY2 GCRDY1 GCRDY2 GY00 GY01 GCBB YUV gain GPBB GPBR GCRR GPRB GPRR Test Circuit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Note S03) (Note S02) ⎯ ⎯ (Note S01) ⎯ ⎯ Test Condition ⎯ Min 0.7 0.7 25 −37 27 −36 3.6 4.6 3.6 4.6 1.5 2.9 2.0 3.5 3.4 5.4 3.1 5.2 130 130 1.8 −1.65 1.8 −1.65 2.4 2.4 9.5 9.9 −18.0 9.5 −15.0 10.0 Typ. 0.9 0.9 29 −33 31 −32 4.5 5.8 4.5 5.8 2.8 4.2 3.3 4.8 4.7 6.7 4.4 6.5 155 155 2.25 −1.2 2.25 −1.2 3.4 3.4 11.0 11.4 −16.0 11.0 −13.5 11.5 Max 1.0 1.0 33 −29 35 −28 5.4 7.0 5.4 7.0 4.1 5.5 4.6 6.1 6.0 7.0 5.7 7.8 185 185 2.7 −0.75 2.7 −0.75 4.4 4.4 12.5 12.9 −14.0 12.5 −12.0 13.0 dB dB ns ns dB MHz ° Unit Vp-p 29 2005-08-18 TA1360ANG Characteristics Symbol GrA01 GrA10 GrA11 GrB01 GrB10 GrB11 GrC01 Green stretch GrC10 GrC11 GrD01 GrD10 GrD11 GrE01 GrE10 GrE11 Test Circuit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Note S04) Test Condition Min 0.98 0.95 0.93 1.01 1.05 1.12 1.10 1.23 1.35 1.09 1.21 1.32 0.98 0.95 0.93 Typ. 1 1 1 1.05 1.1 1.19 1.14 1.27 1.42 1.13 1.25 1.39 1 1 1 Max 1.02 1.05 1.07 1.10 1.15 1.26 1.18 1.31 1.49 1.17 1.29 1.46 1.02 1.05 1.07 times Unit 30 2005-08-18 TA1360ANG Color Difference Block 2 Characteristics Color difference contrast adjustment characteristic Color adjustment characteristic Symbol ∆VuCY ∆vcCY+ ∆vcCY− θRMAX θRCNT R-Y relative phase and amplitude θRMIN VR/VBMAX VR/VBCNT VR/VBMIN θGMAX θGCNT G-Y relative phase and amplitude θGMIN VG/vBMAX VG/vBCNT VG/vBMIN GHTRY Color difference halftone characteristic GHTGY GHTBY Vγ1 Color γ characteristic Vγ2 Vγ3 ∆γ Color limiter characteristic High-bright color gain CLT0 CLT1 HBC1 Test Circuit ⎯ ⎯ ⎯ ⎯ Test Condition (Note A01) (Note A02) Min 14.5 3.0 −35 109 98.5 ⎯ 88 0.86 0.65 0.42 251 244 ⎯ 229 0.43 0.33 0.22 0.47 (Note A03) 0.47 0.47 0.09 (Note A04) 0.26 0.44 0.60 (Note A05) (Note A06) 1.45 1.80 0.02 Typ. 16.0 4.0 −22 111.5 101 90 0.90 0.69 0.45 254 247 232 0.48 0.37 0.25 0.50 0.50 0.50 0.23 0.40 0.58 0.70 1.65 2.00 0.04 Max 17.5 5.0 −17 114 103.5 92 0.94 0.73 0.49 257 250 235 0.53 0.41 0.28 0.53 0.53 0.53 0.37 0.54 0.72 0.80 1.85 2.20 0.06 ⎯ Vp-p times Vp-p times times ° times ° Unit dB dB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 31 2005-08-18 TA1360ANG Text Block Characteristics Symbol GR AC gain (Y1in~R/G/B out) GG GB AC gain axis difference GG/R GB/R GfR Frequency characteristic (Y1in~R/G/B out) GfG GfB Frequency characteristic (Cb1/Cr1in~R/G/B out) GfCb GfCr GfY1 Y frequency characteristic 2 (Y in~R/G/B out) GfY15 GfY30 VYDC1 Difference among DC center voltages of RGB output amplitudes Unicolor adjustment characteristic VYDC15 VYDC30 ∆Vu VbrMAX Brightness adjustment characteristic VbrCNT VbrMIN White peak slice level Black peak slice level Vwps1 Vwps2 Vbps N41 RGB output S/N N42 N43 Halftone characteristic Halftone on voltage GHT1 GHT2 VHT VVR V-BLK pulse output level VVG VVB VHR H-BLK pulse output level VHG VHB BLK pulse delay time tdON tdOFF ∆vsu+ ∆vsu− CUT+ CUT− ∆V#41 RGB output voltage ∆V#42 ∆V#43 RGB output voltage 3-axis difference ∆VOUT Test Circuit ⎯ Test Condition Min 3.08 (Note T01) 3.08 3.08 ⎯ 0.94 0.94 30 At −3dB, sharpness characteristic is flat 30 30 ⎯ 10 10 2.05 2.40 (Note T02) 1.85 Typ. 3.45 3.45 3.45 1.00 1.00 60 60 60 12.5 12.5 2.30 2.75 2.20 0.02 0.02 0.05 16.0 4.45 3.40 2.30 2.32 2.74 1.35 −52 −52 −52 0.50 0.50 0.85 0.80 0.80 0.80 0.80 0.80 0.80 0.00 0.08 2.45 −3.3 0.47 0.47 2.30 2.30 2.30 0 Max 3.90 3.90 3.90 1.06 1.06 ⎯ ⎯ ⎯ ⎯ ⎯ 2.59 3.10 2.65 0.05 0.05 0.10 17.0 4.80 3.75 2.65 2.44 2.89 1.45 −46 −46 −46 0.55 0.55 1.05 1.30 1.30 1.30 1.30 1.30 1.30 0.30 0.30 2.95 −2.8 0.52 0.52 2.55 2.55 2.55 150 mV V µs V V times V dB Vp-p V V dB V Vp-p MHz MHz times Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Pin 52 ⎯ ⎯ ⎯ (Note T03) 15.0 4.10 (Note T04) 3.05 1.95 (Note T05) (Note T06) 2.20 2.59 1.15 ⎯ (Note T07) ⎯ ⎯ (Note T08) 0.45 0.45 0.65 0.30 ⎯ 0.30 0.30 0.30 ⎯ 0.30 0.30 (Note T09) ⎯ ⎯ 1.95 −3.8 0.42 0.42 2.05 2.05 2.05 ⎯ Sub-contrast variable range ⎯ ⎯ dB Cut-off voltage variable range V 32 2005-08-18 TA1360ANG Characteristics Symbol DRR1+ DRR1− DRR2+ DRR2− DRG1+ DRG1− DRG2+ Drive adjustment variable range DRG2− DRG3+ DRG3− DRB1+ DRB1− DRB2+ DRB2− DRB3+ DRB3− MURD Output voltage at P-mute MUGD MUBD P-mute ON voltage VMUTE BBR Output voltage at blue background BBG BBB Input impedance of #53 ACL characteristic Zin ACL1 ACL2 ABLP1 ABLP2 ABLP3 ABL point ABLP4 ABLP5 ABLP6 ABLP7 ABLP8 ABLG1 ABLG2 ABLG3 ABL gain ABLG4 ABLG5 ABLG6 ABLG7 ABLG8 Test Circuit Test Condition Min 2.5 −5.5 2.5 −5.5 2.5 −5.5 2.5 (Note T10) −5.5 2.5 −5.5 2.5 −5.5 2.5 −5.5 2.5 −5.5 1.7 Typ. 3.0 −5.0 3.0 −5.0 3.0 −5.0 3.0 −5.0 3.0 −5.0 3.0 −5.0 3.0 −5.0 3.0 −5.0 1.85 1.85 1.85 2.15 1.2 1.2 1.25 30 −4.5 −13.5 −0.16 −0.23 −0.32 −0.40 −0.49 −0.57 −0.65 −0.70 −0.02 −0.12 −0.29 −0.47 −0.63 −0.80 −0.96 −1.04 Max 3.5 −4.5 3.5 −4.5 3.5 −4.5 3.5 −4.5 3.5 −4.5 3.5 −4.5 3.5 −4.5 3.5 −4.5 2.0 2.0 2.0 2.40 1.4 1.4 1.4 36 −2.5 −11.0 −0.11 −0.18 −0.27 −0.35 −0.44 −0.52 −0.60 −0.65 0.00 −0.07 −0.24 −0.42 −0.59 −0.75 −0.91 −0.99 V V V V Vp-p kΩ dB V dB Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Note T14) (Note T13) (Note T11) (Note T12) Pin 52 ⎯ 1.7 1.7 1.90 1.0 ⎯ 1.0 1.1 24 −6.5 −15.0 −0.21 −0.28 −0.37 −0.45 −0.54 −0.62 −0.70 −0.75 −0.06 −0.17 −0.34 −0.52 −0.68 −0.85 −1.01 −1.09 33 2005-08-18 TA1360ANG Characteristics Symbol V43R V42R V41R V43G RGB output mode V42G V41G V43B V42B V41B γ1 γ2 Y-OUT γ characteristic ∆1 ∆2 ∆3 BSPmin BSPcnt White-peak blue characteristic BSPmax BSGmin BSGcnt BSGmax Forced BLK input threshold voltage VBLKIN θACBR θACBG θACBB VACB1R VACB1G ACB insertion pulse phase and amplitude VACB1B VACB2R VACB2G VACB2B VACB3R VACB3G VACB3B IKR IK input amplitude IKG IKB IK input cover range DIKin+ DIKin− Test Circuit Test Condition Min 2.15 0.30 0.30 0.30 (Note T15) 2.15 0.30 0.30 0.30 2.15 56 72 (Note T16) 0.49 −1.67 −4.59 37 72 (Note T17) 101 2.1 6.4 9 Pin 52 5.1 ⎯ ⎯ ⎯ 0.15 0.15 (Note T18) 0.15 0.27 0.27 0.27 0.52 0.52 0.52 0.73 (Note T19) 0.73 0.73 (Note T20) 3.00 −0.50 Typ. 2.40 0.80 0.80 0.80 2.40 0.80 0.80 0.80 2.40 66 82 1.24 −0.92 −3.84 42 77 106 3.1 7.4 10 5.6 1 2 3 0.20 0.20 0.20 0.32 0.32 0.32 0.57 0.57 0.57 0.93 0.93 0.93 3.30 −0.30 Max 2.65 1.30 1.30 1.30 2.65 1.30 1.30 1.30 2.65 76 92 1.99 −0.17 −3.09 47 82 111 4.1 8.4 11 6.1 ⎯ ⎯ ⎯ 0.25 0.25 0.25 0.37 0.37 0.37 0.62 0.62 0.62 1.13 1.13 1.13 3.60 −0.10 V Vp-p Vp-p H V dB IRE dB IRE V Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 34 2005-08-18 TA1360ANG Characteristics Symbol GTXR Analog RGB gain GTXG GTXB Analog RGB gain 3-axis difference GTXG/R GTXB/R GfTXR Analog RGB frequency characteristic GfTXG GfTXB DR35 Analog RGB input dynamic range DR34 DR33 TXVWPSR Analog RGB white peak slice level TXVWPSG TXVWPSB VBPSR Analog RGB black peak limit level VBPSG VBPSB ∆vuTXR RGB contrast adjustment characteristic ∆vuTXG ∆vuTXB VbrTXmax Analog RGB bright adjustment characteristic Analog RGB mode switching voltage VbrTXcnt VbrTXmin VTXON τRYS tPRYS Analog RGB mode switching transfer characteristic ∆tRYS τFYS tPRYS ∆tRYS Text ACL characteristic TXACL1 TXACL2 GOSDR Analog OSD gain GOSDG GOSDB Analog OSD gain 3-axis difference GOSDG/R GOSDB/R GfOSDR Analog OSD frequency characteristic GfOSDG GfOSDB DR39 Analog OSD input dynamic range DR38 DR37 Test Circuit Test Condition Min 3.03 (Note T21) 3.03 3.03 ⎯ 0.94 0.94 30 At −3dB 30 30 0.80 ⎯ 0.80 0.80 2.45 (Note T22) 2.45 2.45 1.15 (Note T23) 1.15 1.15 15.5 (Note T24) 15.5 15.5 3.0 (Note T25) 2.6 2.1 Pin 49 0.65 ⎯ ⎯ (Note T26) ⎯ ⎯ ⎯ ⎯ (Note T27) −6.7 −16.5 2.95 (Note T28) 2.95 2.95 ⎯ 0.94 0.94 35 At −3dB 35 35 0.80 ⎯ 0.80 0.80 Typ. 3.40 3.40 3.40 1.00 1.00 35 35 35 1.20 1.20 1.20 2.70 2.70 2.70 1.30 1.30 1.30 16.5 16.5 16.5 3.2 2.8 2.3 0.85 15 20 0 10 30 0 −4.7 −14.5 3.30 3.30 3.30 1.00 1.00 40 40 40 1.20 1.20 1.20 Max 3.83 3.83 3.83 1.06 1.06 ⎯ ⎯ ⎯ 1.50 1.50 1.50 2.95 2.95 2.95 1.45 1.45 1.45 18.5 18.5 18.5 3.4 3.0 2.5 1.05 50 50 10 50 50 10 −2.7 −12.5 3.70 3.70 3.70 1.06 1.06 ⎯ ⎯ ⎯ 1.50 1.50 1.50 Vp-p MHz ⎯ times dB ns V V dB V Vp-p Vp-p MHz ⎯ times Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 35 2005-08-18 TA1360ANG Characteristics Symbol OSDVWPSR OSDVWPSG OSDVWPSB OSDVBPSR Analog OSD black peak limit level OSDVBPSG OSDVBPSB VUOSDR11 VUOSDG11 VUOSDB11 VUOSDR10 VUOSDG10 OSD contrast adjustment characteristic VUOSDB10 VUOSDR01 VUOSDG01 VUOSDB01 VUOSDR00 VUOSDG00 VUOSDB00 VbrOSD0 Analog OSD bright adjustment characteristic VbrOSD1 VbrOSD2 VbrOSD3 Analog OSD mode switching voltage VOSDON1 VOSDON2 τRYS1 tPRYS1 ∆tPRYS1 τFYS1 tPRYS1 Analog OSD mode switching transfer characteristic ∆tPRYS1 τRYS2 tPRYS2 ∆tPRYS2 τFYS2 tPRYS2 ∆tPRYS2 OSDACL1 OSD ACL characteristic OSDACL2 OSDACL3 OSDACL4 Test Circuit Test Condition Min 2.45 (Note T29) 2.45 2.45 1.30 (Note T30) 1.30 1.30 0.58 0.58 0.58 0.47 0.47 (Note T31) 0.47 0.31 0.31 0.31 0.19 0.19 0.19 2.20 (Note T32) 2.05 1.95 1.80 Pin 51 Pin 50 2.05 2.05 Typ. 2.70 2.70 2.70 1.45 1.45 1.45 0.64 0.64 0.64 0.53 0.53 0.53 0.37 0.37 0.37 0.22 0.22 0.22 2.40 2.25 2.15 2.00 2.30 2.30 15 20 0 10 30 0 15 20 0 10 30 0 0.00 0.00 −4.7 −14.5 Max 2.95 2.95 2.95 1.60 1.60 1.60 0.71 0.71 0.71 0.59 0.59 0.59 0.45 0.45 0.45 0.24 0.24 0.24 2.60 2.45 2.35 2.20 2.55 2.55 50 50 10 50 50 10 50 50 10 50 50 10 ns V V Vp-p V Vp-p Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Note T34) (Note T33) Analog OSD input white peak slice level ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −6.7 −16.5 ⎯ ⎯ −2.7 −12.5 dB 36 2005-08-18 TA1360ANG Characteristics Symbol α41TV1 α42TV1 α43TV1 α41TV2 α42TV2 α43TV2 α41TV3 α42TV3 OSD blending characteristic α43TV3 α41OSD1 α42OSD1 α43OSD1 α41OSD2 α42OSD2 α43OSD2 α41OSD3 α42OSD3 α43OSD3 Y → RGB input Y → OSD input RGB input → Y RGB input → OSD input Input crosstalk OSD input → Y OSD input → RGB input RGB input in three axes OSD input in three axes VV → A VV → O VA → V VA → O VO → V VO → A ⎯ ⎯ BLPmin Blue stretch point/gain BLPmax BLGmin BLGmax BLγ1 Blue stretch γ correction BLγ2 BLγ3 BLγ4 WPL1 White letters improvement WPL2 WPL3 Test Circuit Test Condition Min −7 −7 −7 −4 −4 −4 Typ. −6 −6 −6 −3 −3 −3 −55 −55 −55 −5.5 −5.5 −5.5 −10.5 −10.5 −10.5 −40 −40 −40 −50 −55 −50 −50 −45 −50 −50 −50 28 60 2.9 6.4 89 94 98 103 21 56 102 Max −5 −5 −5 −2 −2 −2 −50 −50 −50 −4.5 −4.5 −4.5 −9.0 −9.0 −9.0 −30 −30 −30 −45 −45 −45 −45 −40 −45 −40 −40 33 65 3.4 7.4 94 99 103 108 25 61 107 Vp-p IRE IRE dB dB Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (Note T38) (Note T37) (Note T36) Input: Signal 1 (fo = 1 MHz, Amplitude 0.7 Vp-p) Input: Signal 1 (fo = 4 MHz, Amplitude 0.7 Vp-p) (Note T35) ⎯ ⎯ ⎯ −6.5 −6.5 −6.5 −12.0 −12.0 −12.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 23 55 2.4 5.4 84 89 93 98 16 51 97 dB 37 2005-08-18 TA1360ANG Sync Block Characteristics Sync input horizontal sync phase HD input horizontal sync phase Symbol SPH HDPH HDDUTY1 Polarity detecting rage HDDUTY2 HDDUTY3 HDDUTY4 VthS00 Sync input threshold amplitude VthS01 VthS10 VthS11 HD input threshold voltage Horizontal picture position (phase) adjustment variable range Horizontal picture position (phase) shift switching amount Curve correction variable amount VthHD ∆HSFT− ∆HSFT+ HSFT ∆H#23 CPS0 CPW0 CPV0 CPS1 Clamp pulse phase/width/level CPW1 CPV1 CPS2 CPW2 CPV2 HBPS00a HBPS00b HBPS01a Black peak detection pulse phase HBPS01b HBPs10a HBPs10b HBPs11a HBPs11b FBP threshold HVCO oscillation start voltage H-OUT start voltage H-OUT stop voltage H-OUT pulse duty VthFBP VVCO VHON VHOFF THA THB Test Circuit ⎯ ⎯ ⎯ ⎯ ⎯ (Note HA03) Test Condition (Note HA01) (Note HA02) Min 0.55 0.58 ⎯ 62 ⎯ 47.5 10 (Note HA04) 18 26 34 (Note HA05) (Note HA06) ⎯ (Note HA07) 0.65 11 11 5.2 2.9 3.1 2.0 4.7 0 (Note HA08) 1.9 4.7 3.2 2.2 4.7 1.1 1.2 6.0 (Note HA09) 6.0 10.0 10.0 15.5 16.0 (Note HA10) Pin 21: Monitor, VCC voltage Pin 26: Monitor, VCC voltage Pin 26: Monitor, VCC voltage (Note HB01) 4.8 3.0 5.0 4.3 38 44 Typ. 0.65 0.68 0.5 67 99.5 52.5 16 24 32 40 0.75 12.5 12.5 6.7 3.4 3.8 2.5 5.0 0.7 2.4 5.0 4.2 2.7 5.0 3.0 3.0 8.0 8.0 13.0 13.0 18.0 18.0 5.3 4.0 6.0 5.3 41 47 Max 0.75 0.78 2.0 72 98 57.5 22 30 38 46 0.85 14 14 9.2 3.9 4.5 3.0 5.3 1.5 2.9 5.3 5.2 3.2 5.3 8.1 5.9 13.0 11.0 17.0 15.0 22.5 21.0 5.8 5.0 7.0 6.3 43 49 V V V V % % Vp-p % % % % V % V % V % % Unit µs µs ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 38 2005-08-18 TA1360ANG Characteristics Symbol F15K F28K Horizontal free-run frequency F31K F33K F37K F45K F15KMIN F15KMAX F28KMIN F28KMAX F31KMIN Horizontal oscillation frequency variable range F31KMAX F33KMIN F33KMAX F37KMIN F37KMAX F45KMIN F45KMAX BH15K BH28K Horizontal oscillation control sensitivity BH31K BH33K BH37K BH45K H-OUT output voltage Pin 13 Horizontal oscillation frequency control voltage threshold VHOH VHOL VfHSW1 VfHSW2L Pin 22 VfHSW2M VfHSW2H DAC1 DAC switch voltage DAC2 VP output pulse width 000 001 010 Vertical free-run (maximum pull-in range) 011 100 101 110 Vertical minimum pull-in range VDAC1H VDAC1L VDAC2H VDAC2L VPW VPt0 VPt1 VPt2 VPt3 VPt4 VPt5 VPt6 TVPULL Test Circuit Test Condition Min 15.59 27.90 (Note HB02) 31.19 33.41 37.60 44.52 14.58 16.52 25.91 29.37 29.12 (Note HB03) 33.03 31.09 35.24 35.82 40.59 42.34 47.99 176 320 Hz/0.1 V (Note HB04) 352 376 390 520 (Note HB05) 4.8 ⎯ 1.7 ⎯ 1.3 4.3 7.3 TEST = (00), DAC1 = (0) TEST = (00), DAC1 = (1) TEST = (00), DAC2 = (1) TEST = (00), DAC2 = (0) (Note V01) 8.5 ⎯ 8.5 ⎯ 4 1278 846 722 ⎯ 657 610 360 304 (Note V02) 47 Typ. 15.75 28.125 31.5 33.75 37.9 45.0 14.88 16.85 26.44 29.96 29.72 33.70 31.73 35.95 36.54 41.39 43.20 48.93 220 400 440 470 480 650 5.1 0.1 2.0 1.5 4.5 7.5 9.0 0.3 9.0 0.3 4.5 1281 849 725 660 613 363 307 48 Max 15.91 28.35 31.82 34.09 38.40 45.48 15.18 17.18 26.97 30.55 30.32 34.37 32.37 36.66 37.26 42.19 44.06 49.87 264 480 528 564 570 780 5.2 0.3 2.3 1.7 4.7 7.7 ⎯ 0.7 ⎯ 0.7 5 1284 852 728 663 616 366 310 49 H H H V V V ⎯ kHz kHz Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 39 2005-08-18 TA1360ANG Characteristics 000 Symbol VBPP0E VBPP0S VBPP1E VBPP1S VBPP2E VBPP2S VBPP3E VBPP3S VBPP4E VBPP4S VBPP5E VBPP5S VBPP6E VBPP6S VBLKMIN VBLKMAX High Low VVPH VVPL 15.75 kHz 28.125 kHz SYNC input to VP output delay time 31.5 kHz 33.75 kHz 37.9 kHz 45 kHz 000 CBLK1000min CBLK1000max CBLK1001min CBLK1001max CBLK1010min CBLK1010max CBLK1011min CBLK1011max CBLK1100min CBLK1100max CBLK1101min CBLK1101max CBLK1110min CBLK1110max Test Circuit Test Condition Min 51 Typ. 52 Max 53 Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ pin 27 voltage (Note V04) (Note V03) 1099.5 1100.5 1101.5 51 729.5 49.5 599.5 49.5 544.5 51 499.5 51 289.5 51 239.5 15 45 4.6 ⎯ 10.0 5.4 4.8 4.4 3.9 3.1 1087 1117 719 749 591 621 527 557 487 517 279 309 223 253 52 730.5 50.5 600.5 50.5 545.5 52 500.5 52 290.5 52 240.5 16 46 5.0 0.1 11.6 6.4 5.8 5.4 4.8 4.1 1088 1118 720 750 592 622 528 558 488 518 280 310 224 254 53 731.5 51.5 601.5 51.5 546.5 53 501.5 53 291.5 53 241.5 17 47 5.4 0.5 13.4 8.8 7.6 7.2 6.6 5.9 1089 1119 721 751 593 623 529 559 489 519 281 311 225 255 H µs H H 001 010 Vertical black peak detection pulse 011 100 101 110 Vertical blanking end phase VP output voltage V 001 010 Compression BLK 1 (start phase) 011 100 101 110 40 2005-08-18 TA1360ANG Characteristics 000 Symbol CBLK2000min CBLK2000max CBLK2001min CBLK2001max CBLK2010min CBLK2010max CBLK2011min CBLK2011max CBLK2100min CBLK2100max CBLK2101min CBLK2101max CBLK2110min CBLK2110max IEXTBLK Test Circuit ⎯ ⎯ Test Condition Min 49 77 49 77 49 77 ⎯ 49 77 49 77 49 77 49 77 Pin 27 input current 520 Typ. 50 78 50 78 50 78 50 78 50 78 50 78 50 78 625 Max 51 79 51 79 51 79 51 79 51 79 51 79 51 79 780 µA H Unit 001 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 010 Compression BLK 2 (end phase) 011 100 101 110 External V-BLK input current 41 2005-08-18 TA1360ANG Test Condition for Picture Quality (Sharpness) Block Common Test Condition for Picture Quality (Sharpness) Block 1. 2. 3. 4. SW4 = SW5 = B, SW8~SW10 = B, SW20 = ON, SW23 = B, SW33∼SW39 = A, SW54 = OPEN Send bus control data as preset values, turn ACB operation switching to ACB OFF (00), select Sync input (1), turn P-MODE to Normal 1(000), WPL-LEVEL to max (111), and change subaddress (1C) to (03). Input sync signal, which is in sync with input signal for testing except “Sweep”, to #14 (Sync input). “H-Freq.” should be the same frequency as the one of #14. Set Y/color difference input mode to (0), sync separator level to 20 % (01), and vertical free-running frequency to 307H (110). Test Conditions SW Mode SW2 SW3 SW7 C C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. 3. 4. 5. Connect external power supply PS to #3, and monitor #2 and #56. Set black stretch point 1 to OFF (000), and black detection level to 0 IRE (1). Increase PS voltage from 4.95 V in steps of 1 mV. At the moment when #2 picture period (High) drops to Low level, monitor DC difference on #56 VB. Set black detection level to 3 IRE (0). Repeat the step 3 above and monitor DC difference, VB3 on #56. Note No. P01 Characteristics SW1 Black detection level shift B #56 waveform VB, VB3 #2 waveform P02 Black stretch amp maximum gain B A A B OPEN 1. 2. 3. 4. 5. Set SW2 to A (maximum gain), and input 500-kHz sine wave to TPA. Adjust signal amplitude to 0.1 Vp-p on #3. Set black stretch point 1 to OFF (000), and measure #56 amplitude VA. Set black stretch point 1 to 001 (black stretch ON), and measure #56 amplitude VB. Calculate GBS using a following equation. GBS = 20 × log (VB ÷ VA) [dB] 42 2005-08-18 TA1360ANG Note No. P03 Characteristics SW1 Black stretch start point 1 A Test Conditions SW Mode SW2 SW3 SW7 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. 3. 4. 5. Set SW2 to A (maximum gain), and black stretch point 1 to OFF (000). Apply 0 V to #1. Connect external power supply PS to #3, increase voltage from V3, and plot #56 voltage change S1. The #56 voltage is set as V0 when V3 is applied, and as V100 when V3 + 0.7 V is applied. Set black stretch point 1 to minimum (001), increase PS voltage from V3, and then plot #56 voltage change S2. Set black stretch point to maximum (111), repeat 3 above, then plot #56 voltage change S3. Determine intersection points of S1, S2 (VBST1), and S3 (VBST2) as shown in the figure below. Also calculate PBST1 and PBST2 using following equations. VZ [V] = V100 [V] − V0 [V] PBST1 [(IRE)] = [(VBST1 [V] − V56 [V]) ÷ VZ] × 100 (IRE) PBST2 [(IRE)] = [(VBST2 [V] − V56 [V]) ÷ VZ] × 100 (IRE) #56 S3 VBST2 S1 VBST1 S2 V56 #3 43 2005-08-18 TA1360ANG Note No. P04 Characteristics SW1 Black stretch start point 2 A Test Conditions SW Mode SW2 SW3 SW7 A A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. Set black stretch point 1 to OFF (000), apply 0 V to #1, input TG7 LINEARITY to TPA, adjust amplitude on #3 as shown in the figure below, set unicolor to center (1000000), and measure amplitude of #43 (R OUT), VP43. Set black stretch point 1 to 001 (black stretch ON), connect external power supply PS to #56, and monitor #43 (R OUT). Set black stretch start point 2 data to minimum (00). When PS is V56 (APL 0%), and V56 + 1.0 V (APL 100%), determine black stretch start point difference ∆V00 as shown in the figure below. (Monitor input waveform and output waveform with an oscilloscope, adjust the both waveforms to have the same amplitude (gradient), and compare them to determine the bend point of the output.) Set black stretchstart point 2 data to maximum (11), determine black stretch start point difference ∆V11. Calculate following equations. PBS1 = (∆V00/VP43) × 100 PBS2 = (∆V11/VP43) × 100 LINEARITY 2. 3. 4. 5. APL 100% 0.7 Vp-p APL 0% ∆V*** 0.3 Vp-p #3 waveform (linearity) #43 (R OUT) 44 2005-08-18 TA1360ANG Note No. P05 Characteristics SW1 Black stretch characteristic switch A Test Conditions SW Mode SW2 SW3 SW7 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. 3. 4. Set SW2 to A (maximum gain), black stretch point 1 (18) to maximum (E0), subaddress (1C) data to (00) and (1E) data to (08). Apply 0 V to #1 and connect external power supply PS to #3. Set PS to V3 + 0.7 V, and adjust unicolor so that DC level of #43 is +1.0 V. Plot voltage change S4 of #43 (voltage in picture period). Determine intersection points (VBSC1 and VBSC2) of S2 and S4 obtained from the plot in black stretch start point 1. Then calculate PBSC1 and PBSC2 using following equation. Set black stretch characteristic switch subaddress data (1C)/(1E) to (20)/(00) and (20)/(08) respectively. As described in steps 2 and 3, determine intersection points (VBSC3, VBSC4, VBSC5 and VBSC6) and calculate PBSC3, PBSC4, PBSC5 and PBSC6. PBSC* = (VBSC* [V] − V43 [V]) ÷ 1.0 × 100 [(IRE)] #43 VBSC2 V43 VBSC1 V3 S2 #3 V3 + 0.7 V S4 Black stretch characteristic switch ON 45 2005-08-18 TA1360ANG Note No. P06 Characteristics SW1 Black stretch area reinforcement current B Test Conditions SW Mode SW2 SW3 SW7 Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. Connect external power supply PS1 to #3. 2. Leave SW2 open, put an ammeter between SW2A and #2, connect external power supply PS2 to SW2A, set PS1 to 5.7 V, and set PS2 to 5 V. 3. Measure current value IBSA0 and IBSA1 when bus data of black stretch area reinforcement [18] is set to ON [80] and OFF [81]. Calculate IBSA using the following equation. IBSA = IBSA0－IBSA1 ⎯ C B SW2A A µ Ａmmeter PS2 5V P07 D.ABL detection voltage B A C B OPEN 1. 2. 3. 4. Set D.ABL sensitivity to maximum (11), and black stretch point 1 to OFF (000). Connect external power supply PS to #53 and decrease voltage from 6.5 V. Repeat 2 when D.ABL detection voltage is changed to 00, 01, 10, and 11. At the moment when #56 picture period changes to Low, measure respective PS voltages V00, V01, V10, and V11. Calculate voltage differences between V00 and V01 (DV01), between V00 and V10 (DV10), and between V00 and V11 (DV11) DV*** = V00 − V01 (V10, V11) #56 undetected #56 detected #2 waveform 46 2005-08-18 TA1360ANG Note No. P08 Characteristics SW1 D.ABL sensitivity B Test Conditions SW Mode SW2 SW3 SW7 A C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. Set black stretch point 1 to OFF (000), and connect external power supply to #53. Set D.ABL detection voltage to minimum (00). Interrelation between #53 voltage and #56 voltage when D.ABL sensitivity is set to minimum (00) and maximum (11) can be plotted as figure shown below. Measure gradients SDAMIN and SDAMAX using the figure below. SDAMIN = ∆Y/∆X SDAMAX = ∆Y/∆X #56 10% 100% ∆Y 10% ∆X #53 47 2005-08-18 TA1360ANG Note No. P09 Characteristics SW1 Black level correction B Test Conditions SW Mode SW2 SW3 SW7 A A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. 3. Set black stretch point 1[18] to OFF (00). Input signal of 0.7-V picture period amplitude to #3, and measure #43 picture period amplitude VB [V]. Set black level correction [18] to ON [04], determine DC change VBLC [V], and calculate BLC [V] using the following equation BLC = (VBLC/VB)] × 100 [(IRE)] #43 VBLC VB Black level correction OFF Black level correction ON 48 2005-08-18 TA1360ANG Note No. P10 Characteristics SW1 Dynamic Yγ correction point A Test Conditions SW Mode SW2 SW3 SW7 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. 3. 4. 5. 6. Connect external power supply PS1 to #3, PS2 to TP1, and set PS2 to 0 V. Set dark area dynamic Yγ gain VS dark area to MIN (00), static Yγ gain1 to OFF (000). Increase PS1 from V3 [V] to V3 [V] + 0.7 V and plot voltage change of #43 picture period. Take 0 for V3 [V] when the change is plotted. (V3 is pin voltage of pin 3) Set dark area dynamic Yγ gain VS dark area max (11), static Yγ gain1 to max (111) and PS2 to 1.2 V. Increase PS1 from V3 [V] to V3 [V] + 0.7 V and plot voltage change of #43 picture period. Measure VDGP by the following figure, and PDGP using the following equation. DGP = (VDGP [V] − V3 [V])/0.7 [V] × 100 #43 voltage [V] ON OFF V3 VDGP V3 + 0.7V (100 IRE) #3 voltage [V] 49 2005-08-18 TA1360ANG Note No. P11 Characteristics SW1 Dark area dynamic Yγ gain A Test Conditions SW Mode SW2 SW3 SW7 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. 3. 4. Connect external power supply PS1 to #3, external power supply PS2 to TP1, and set PS2 to 0 V. Set dark area dynamic Yγ gain [1C] to MIN [03], and dark area static Yγ gain [1C] to 0dB [17]. Set PS1 to V3 [V], and measure #43 picture period voltage VDDGV3 [V]. Set PS1 VDGP [V], and measure #43 picture period voltage VDDGMIN [V]. Set dark area dynamic Yγ gain [1C] to MAX [D7], PS2 to 1.2 V, measure voltage VDDGMAX [V] of #43 picture period when PS1 is VDGP [V], and calculate the following equations. VDDGMAX − VDDGMIN = A VDDGMIN − VDDGV3 = B GDDGMAX = 20 log [B/(B-A)] [dB] #43 voltage [V] OFF VDDGMAX VDDGMIN VDDGV3 VDDGMIN − VDDGV3 = B #3 voltage [V] V3 + 0.7 V (100IRE) ON VDDGMAX − VDDGMIN = A V3 VDGP 50 2005-08-18 TA1360ANG Note No. P12 Characteristics SW1 Dark area static Yγ gain A Test Conditions SW Mode SW2 SW3 SW7 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. Connect external power supply PS1 to #3, external power supply PS2 to TP1, and set PS2 to 0 V. 2. Set dark area dynamic Yγ gain [1C] to MIN [03], and dark area static Yγ gain [1C] to OFF [03]. 3. Set PS1 to V3 [V], and measure #43 picture period voltage VSGOFF1 [V]. 4. Set PS1 to VDGP [V], and measure #43 picture period voltage VSGOFF2 [V]. 5. Set dark area static Yγ gain [1C] to MAX [1F], PS1 to VDGP [V], measure #43 picture period voltage VSGMAX, and calculate GDSGMAX using the following equations. VSGMAX − VSGOFF2 = A VSGOFF2 − VSGOFF1 = B GDSGMAX = 20 × log [B/(B - A)] [dB] #43 voltage [V] OFF VSGMAX VSGOFF2 VSGOFF1 V3 VDGP #3 voltage [V] V3 + 0.7 V (100IRE) ON VSGMAX − VSOFF2 = A 6. Set dark area static Yγ gain [1C] to MIN [07], PS1 to VDGP [V], measure #43 picture period voltage VSGMIN, and calculate GDSGMIN using the following equation. GDSGMIN = 20 × log [(VSGMIN − VSGOFF1)/(VSGOFF2 − VSGOFF1)] #43 voltage [V] [dB] OFF VSGOFF2 VSGMIN VSGOFF1 VSGOFF2 − VSGOFF1 ON V3 VDGP VSGMIN − VSGOFF1 V3 + 0.7 V (100IRE) #3 voltage [V] 51 2005-08-18 TA1360ANG Note No. P13 Characteristics SW1 Light area Yγ correction point A Test Conditions SW Mode SW2 SW3 SW7 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. Connect external power supply PS1 to #3, external power supply PS2 to TP1, and set PS2 to 0 V. 2. Set dark area static Yγ gain [1C] to 0dB [17], and bright area static Yγ gain [1C] to 0dB [17]. 3. Increase PS1 from V3 [V] to V3 [V] + 0.7 [V], and plot the voltage change of #43 picture period. Take 0 for V3 [V] when the change is plotted. (V3 is pin voltage of pin 3) 4. Set light area static Yγ gain [1C] to MAX [04]. 5. Increase PS1 from V3 [V] to V3 [V] + 0.7 [V], and plot the voltage change of #43 picture period. 6. Measure VLGP using the following figure, and PLGP using the following equation. LGP = (VLGP [V] − V3 [V])/0.7 [V] × 100 #43 voltage [V] ON (IRE) OFF V3 VLGP #3 voltage [V] V3 + 0.7 V (100IRE) 52 2005-08-18 TA1360ANG Note No. P14 Characteristics SW1 Light area dynamic Yγ gain A Test Conditions SW Mode SW2 SW3 SW7 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. 3. 4. 5. Connect external power supply PS1 to #3, external power supply PS2 to TP7, and set PS2 to 1.2 V. Set dark area static Yγ gain [1C] to 0dB [17], and light area static Yγ gain [1C] to 0dB [17]. Set PS1 to V3 [V], and measure #43 picture period voltage VLDGOFF1. Set PS1 to VLGP [V], and measure #43 picture period voltage VLDGOFF2. Set light area static Yγ gain [1C] to MAX [14], PS2 to 0 V, PS1 to VLGP [V], determine #43 picture period voltage VLDGMAX [V] using the following equations. VLDGMAX − VLDGOFF2 = A VLDGOFF2 − VLDGOFF1 = B GLDG = 20 × log [B/(B − A)] #43 voltage [V] VLDGMAX VLDGOFF2 ON VLDGMAX − VLDGOFF2 = A VLDGOFF2 − VLDGOFF1 = B OFF VLDGOFF1 V3 VLGP V3 + 0.7 V (100IRE) #3 voltage [V] 53 2005-08-18 TA1360ANG Note No. P15 Characteristics SW1 Light area static Yγ gain B Test Conditions SW Mode SW2 SW3 SW7 B C A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. 3. 4. 5. Connect external power supply PS1 to #3, external power supply PS2 to TP7, and set PS2 to 0 V. Set dark area static Yγ gain [1C] to 0dB [17], and light area static Yγ gain [1C] to 0dB [17]. Set PS1 to V3 [V], and measure #43 picture period voltage VLSGOFF1 [V]. Set PS1 to VLGP [V], and measure #43 picture period voltage VLDGOFF2 [V]. Set light area static Yγ gain [1C] to MAX [14], PS1 to VLGP [V], measure #43 picture period voltage VlSGMAX, and calculate GLASGMAX [dB] using the following equations. VLSGMAX − VLSGOFF2 = A VLSGOFF2 − VLSGOFF1 = B GLSGMAX = 20 × log [B/(B − A)] [dB] #43 voltage [V] VLSGMAX VLSGOFF2 ON VLSGMAX − VLDGOFF2 = A VLSGOFF2 − VLSGOFF1 = B OFF VLSGOFF1 V3 VLGP #3 voltage [V] V3 + 0.7 V (100IRE) 6. Set light area static Yγ gain [1C] to MIN [16], PS1 to VLGP [V], measure #43 picture period voltage VLSGMIN, and calculate GLASGMIN [dB] using the following equations. VLSGMIN − VLSGOFF2 = C VLSGOFF2 − VLSGOFF1 = B GLSGMIN = 20 × log [B/(B − C)] [dB] #43 voltage [V] VLSGMIN ON VLSGMIN − VLDGOFF2 = C VLSGOFF2 − VLSGOFF1 = B OFF VLSGOFF1 V3 VLGP V3 + 0.7 V (100IRE) #3 voltage [V] 54 2005-08-18 TA1360ANG Note No. P16 Characteristics SW1 Dark area detection sensitivity A Test Conditions SW Mode SW2 SW3 SW7 B A A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 OPEN 1. 2. Input the signal whose picture period amplitude is 0.18 V to #3 as shown in the figure below. Measure #1 pin voltage DAMIN, DACEN, and DAMAX [V] when dark area detection sensitivity [1D] is set to MIN [00], CEN [04] and MAX [07]. #3 0.18 V #1 DAMIN･CEN･MAX [V] 55 2005-08-18 TA1360ANG Note No. P17 Characteristics SW1 DC restoration rate correction gain B Test Conditions SW Mode SW2 SW3 SW7 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. 4. 5. 6. Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80% (11), and connect external power supply PS1 to #3. Monitor DC level of #43 picture period. Set PS1 to V3 + 0.7 V, and adjust uncolor so that DC level is + 0.7. Set DC restoration correction rate to minimum (000), and measure VDT1 and VDT2 of V3 [V] and V3 + 0.1 V as shown in the figure below. Set #3 to V3 + 0.1 V, DC restoration correction rate to maximum (111), and measure VDT3. Set DC restoration correction rate SW to less than 100 % (1), #3 to V3 + 0.1 V, DC restoration correction rate to maximum (111), and measure VDT4. Calculate ADT100, ADT135, and ADT65 using following equations. ADT100 = (VDT2 [V] − VDT1 [V]) ÷ 0.1 [V] ADT135 = (VDT3 [V] − VDT1 [V]) ÷ 0.1 [V] ADT65 = 1 − ( (VDT2 [V] − VDT4 [V]) ÷ 0.1 [V]) V3 [V] Picture period VDT1 V3 + 0.1 V #43 waveform VDT2 VDT4 VDT3 56 2005-08-18 TA1360ANG Note No. P18 Characteristics SW1 DC restoration rate correction point B Test Conditions SW Mode SW2 SW3 SW7 B C B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. 4. 5. 6. Set DC restoration rate correction point to minimum (000), DC restoration rate correction limit point to 80% (11), and connect external power supply PS1 to #3. Monitor DC level of #43 picture period. Set PS1 to V3 + 0.7 V, and adjust unicolor so that DC level is + 1.0. Set DC restoration correction rate to minimum (000), and increase PS1 from V3. Plot relation between #56 (DC voltage) and #43 (voltage in picture period). Set DC restoration correction rate to maximum (111), and increase PS1 from V3. Plot relation between #56 and #43. Set DC restoration correction rate to maximum (111), DC restoration rate correction point (111), and increase PS1 from V3. Plot relation between #56 and #43. Determine VDT0, and VDT1 using the following equations. VDT0 = [(VSP0 − V56)/1 V] × 100% VDT1 = [(VSP1 − V56)/1 V] × 100% #43 DC restoration rate correction point 000 DC restoration rate correction point 111 DC restoration correction rate 000 VSP0 VSP1 VPC #56 57 2005-08-18 TA1360ANG Note No. P19 Characteristics SW1 DC restoration rate correction limit point B Test Conditions SW Mode SW2 SW3 SW7 B B C Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. 4. Set unicolor to maximum (1111111), DC restoration rate correction point to minimum (000), and connect external power supply PS1 to #56. Set DC restoration correction rate to maximum (111). Increase PS from 5 V. Monitor #43, and plot DC restoration correction amount. Repeat the step 3 above by changing data at DC restoration rate correction limit point. Measure the value using the figure below. Calculate PDTL60, PDTL75, PDTL87, and PDTL100 using following equations. PDTL60 = [(VL60 − V56)/1.0] × 100% PDTL75 = [(VL75 − V56)/1.0] × 100% PDTL87 = [(VL87 − V56)/1.0] × 100% PDTL100 = [(VL100 − V56)/1.0] × 100% #43 100% (00) 87% (01) 73% (10) 60% (11) VL60 VL75 VL100 VL87 #56 58 2005-08-18 TA1360ANG Note No. P20 Characteristics SW1 DC fluctuation at switching sharpness control peak frequency B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. Set unicolor [05] to MAX [7F], SRT gain [19] to MIN [00], and CDE [15] to CEN [80]. Input setup signal (0.2 Vp-p) to TPA as shown in the figure below. Set sharpness [09] to MIN [00] and MAX [80]. Monitor #43, measure DC level VRDCMIN and VRDCMAX [V]. Calculate VRDC [V] using the following equation. VRDC = VRDCMIN − VRDCMAX [V] #3 0.2 V #43 VRDC* 59 2005-08-18 TA1360ANG Note No. P21 Characteristics SW1 Sharpness control range B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. 4. 5. 6. 7. 8. 9. Input sine wave to TPA. (The frequency is variable.) Set #3 amplitude to 20 mVp-p. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), APACON peak frequency to 13.5 M (00), and color detail enhancer (CDE) to center (10). Set picture mute to OFF (P-MODE: Normal 1, 000), and monitor #43. Set picture sharpness to center (1000000). Set input frequency to 100 kHz, and measure the amplitude V100. Set picture sharpness to maximum (1111111). Set input frequency to FAP00, measure the amplitude VMAX00, and calculate GMAX00 using the following equations. Set picture sharpness to minimum (0000000). Set input frequency to FAP00, measure the amplitude VMIN00, and calculate GMIN00 using the following equations. Set APACON peak frequency to 9.5 M (01). Set input frequency to FAP01, measure VMAX01/VMIN01 and calculate GMAX01/GMIN01. Set APACON peak frequency to 6.4 M (10). Set input frequency to FAP10, measure VMAX10/VMIN10 and calculate GMAX10/GMIN10. 10. Set APACON peak frequency to 4.5 M (11). Set input frequency to FAP11, measure VMAX11/VMIN11 and calculate GMAX11/GMIN11. GMAX*** = 20 × log (VMAX*** ÷ V100) [dB] GMIN*** = 20 × log (VMIN*** ÷ V100) [dB] Note: When a spectrum analyzer is used, measure gain for low frequency. 60 2005-08-18 TA1360ANG Note No. P22 Characteristics SW1 Sharpness control center characteristic B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. 4. 5. 6. 7. 8. 9. Input sine wave to TPA. (The frequency is variable.) Set the amplitude of #3 to 20 mVp-p. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), APACON peak frequency to 13.5 M (00), and color detail enhancer (CDE) to center (10). Set picture mute to OFF (P-MODE: Normal 1, 000), and monitor #43. Set picture sharpness to center (1000000). Set input frequency to 100 kHz, and measure the amplitude V100. Set picture sharpness to center (1000000). Set input frequency to FAP00, measure #43 amplitude VCEN00, and calculate GCEN00 using the following equations. Set APACON peak frequency to 9.5 M (01). Set input frequency to FAP01, measure VCEN01 and calculate GCEN01. Set APACON peak frequency to 6.4 M (10). Set input frequency to FAP10, measure VCEN10 and calculate GCEN10. Set APACON peak frequency to 4.5 M (11). Set input frequency to FAP11, measure VCEN11 and calculate GCEN11. GCEN*** = 20 × log (VCEN*** ÷ V100) [dB] Note: When a spectrum analyzer is used, measure gain for low frequency. 61 2005-08-18 TA1360ANG Note No. P23 Characteristics SW1 2T pulse response SRT control B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. 4. 5. 6. 7. 8. Input 2T pulse (0.7 Vp-p) signal to TPA. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), CDE to center (10) picture sharpness control to center (1000000). Set APACON peak frequency to13.5 M (00), and monitor #43. Measure TSRTMIN00 and VSRTMIN00 as shown in the figure below. Set SRT-GAIN to maximum (11111), and measure TSRTMAX00 and VSRTMAX00. Set APACON peak frequency to 9.5 M (01). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN01/VSRTMIN01 and TSRTMAX01/ VSRTMAX01. Set APACON peak frequency to 6.4 M (10). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN10/VSRTMIN10 and TSRTMAX10/ VSRTMAX10. Set APACON peak frequency to 4.5 M (11). Set SRT-GAIN to minimum (00000) and maximum (11111). Measure TSRTMIN11/VSRTMIN11 and TSRTMAX11/VSRTMAX11. Calculate the following equations. TSRT00 = 20 × log [((VSRTMAX00/TSRTMAX00)/(VSRTMIN00/TSRTMIN00)) TSRT01 = 20 × log [(VSRTMAX01/TSRTMAX01)/(VSRTMIN01/TSRTMIN01)] TSRT10 = 20 × log [(VSRTMAX10/TSRTMAX10)/(VSRTMIN10/TSRTMIN10)] TSRT11 = 20 × log [(VSRTMAX11/TSRTMAX11)/(VSRTMIN11/TSRTMIN11)] T*** 20% V*** 100% 20% 62 2005-08-18 TA1360ANG Note No. P24 Characteristics SW1 VSM gain B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. Input sine wave of FVSM frequency to TPA. Set #3 amplitude to 0.02 Vp-p. Turn on SW54 and change VSM gain from minimum (001) to maximum (111). Measure #54 amplitude, V001, V011, V100, V101, V110, and V111. Set input amplitude to 0.7 Vp-p, and VSM gain to OFF (000). Measure TP54 amplitude V000. Calculate the following equations. GV000 = 20 × log (V000/0.7) [dB] GV001 = 20 × log (V001/0.02) [dB] GV010 = 20 × log (V010/0.02) [dB] GV011 = 20 × log (V011/0.02) [dB] GV100 = 20 × log (V100/0.02) [dB] GV101 = 20 × log (V101/0.02) [dB] GV110 = 20 × log (V110/0.02) [dB] GV111 = 20 × log (V111/0.02) [dB] P25 VSM limit B B B A ON 1. 2. 3. Input sine wave of frequency FVSM to TPA. Set VSM gain to 111, and #3 amplitude to 0.7 Vp-p. Turn on SW54 and measure TP54 amplitude VLU and VLD [Vp-p] as shown in the figure below. 3. VLU VLD 63 2005-08-18 TA1360ANG Note No. P26 Characteristics SW1 Y delay time switching B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. 4. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), and input 2T pulse signal (approximately 0.7 V (p-p)) to TPA. Set picture sharpness to center (1000000). Monitor #3 and #43 as shown in the figure below. Measure YDL00 that is the time difference between signals #3 and #43. Set Y/C-DL1 to +5 ns (1), and measure YDL01 as shown in the figure below. Set Y/C-DL1 to 0 ns (0), Y/C-DL2 to +10 ns (1) and measure YDL10 as shown in the figure below. Set Y/C-DL1 to +5 ns (1), Y/C-DL2 to +10 ns (1) and measure YDL11 as shown in the figure below. Determine YDLA, YDLB, and YDLC using the following equations. YDLA = YDL01 − YDL00 YDLB = YDL10 − YDL00 YDLC = YDL11 − YDL00 YDL00 YDL01 YDL10 YDL11 50% 5. 2T pulse Approximately 0.7 Vp-p 6. #43 #3 50% 7. 64 2005-08-18 TA1360ANG Note No. P27 Characteristics SW1 Y group delay correction B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. Input Multi Burst signal (4.2-MHz frequency, 0.1 Vp-p at #3) of A signal in TPA. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), and Color detail enhancer (CDE) to minimum (00000). Set sharpness to flat (DEC [30]), APACON peak frequency to 4.5 M (11), and monitor #43. Sine wave signal A input becomes like signal B on #43 as shown in the figure on the right. Measure SA and SB. When group delay correction is set to minimum (0000), signal A becomes like signal C on #43. Measure SAMIN and SBMIN. When group delay correction is set to maximum (1111), signal A becomes like signal D on #43. Measure SAMAX and SBMAX. Calculate the following equations. GAMIN = 20 × log (SAMIN/SA) [dB] GBMIN = 20 × log (SBMIN/SB) [dB] GAMAX = 20 × log (SAMAX/SA) [dB] GBMAX = 20 × log (SBMAX/SB) [dB] Signal C SAMIN 3. Signal A 4. SA Signal B SB 5. 6. SBMIN SAMAX Signal D SBMAX Note: Sine wave input starts and ends within the picture period such as a burst signal. The wave is not continuous. 65 2005-08-18 TA1360ANG Note No. P28 Characteristics SW1 Color detail enhancer (CDE) B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), color to center (1000000), and color limiter level to 2 Vp (1). Input SWEEP signal to TPA so that #3 amplitude is 20 mVp-p. Set SW4 to A, and input signal as shown in the figure below (#4 amplitude is 0.2 Vp-p) to TP4. Set picture sharpness to center (1000000), Y detail control to center (1000), and monitor #41 with a spectrum analyzer. When CDE is at minimum (00), set low frequency area to 0dB, and determine peak level GCDEMIN. When CDE is at maximum (11), set low frequency area to 0dB, and determine peak level GCDEMAX. Calculate the following equation. GCDE00 = GCDEMAX00 − GCDEMIN00 When APACON peak frequency is 13.5 M (00), 9.5 M (01), 6.4 M (10), and 4.5 M (11), calculate GCDE00, GCDE01, GCDE10, and GCDE11 respectively using above equation. 2. 3. 4. 5. 6. Output gain [dB] max 0.2 Vp-p min 0dB BLK period picture period Input frequency [MHz] 66 2005-08-18 TA1360ANG Note No. P29 Characteristics SW1 Y detail control range B Test Conditions SW Mode SW2 SW3 SW7 B A B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW56 ON 1. 2. 3. 4. 5. 6. Set unicolor to maximum (1111111), SRT-GAIN to minimum (00000), CDE to center (10), and APACON peak frequency to 4.5 M (11). Input SWEEP signal to TPA. Set #3 amplitude to 20mVp-p. Set picture sharpness to center (1000000), Y detail control to maximum (1111), and monitor #43 with a spectrum analyzer. Set low frequency area to 0dB, and measure each peak level GYDMAX. Set Y detail control to center (1000), and measure peak level GYDCEN. Set Y detail control to minimum (0000), and measure peak level GYDMIN. 67 2005-08-18 TA1360ANG Test Conditions for Color Difference Block 1: YUV input and matrix Common Test Condition for Color Difference Block 1: YUV input and matrix 1. 2. 3. 4. SW1 = B, SW2 = B, SW20 = ON, SW33∼SW39 = A, SW54 = OPEN, SW56 = OPEN Transfer BUS control data with preset values. Turn ACB operation switching to ACB OFF (0), and turn high blight color OFF (0). Input sync signal [must be sync with input signal for testing except Sweep.] to #14 (sync input), and set SYNC-IN-SW to 1. Test Conditions SW Mode SW4 SW5 A SW9 B A SW10 B Note No. S01 Characteristics SW3 Color SRT gain C SW8 B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW7 B 1. 2. 3. Set Y mute ON (P-MODE: Y-MUTE, 001), brightness to center (10000000), color to center (1000000), unicolor to maximum (1111111). Input 2T pulse signal to TP4 so that #4 amplitude is 423 mVp-p. Monitor #41 output waveform. When color SRT peak frequency is 4.5 MHz (0), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11) that are SB00MIN, SB00CEN, and SB00MAX as shown in the figure below. Set SB00MIN to 0dB, calculate GSB00CEN = 20 × log (SB00CEN/SB00MIN) and GSB00MAX = 20 × log (SB00MAX/SSB00MIN). When color SRT peak is 5.8 MHz (1), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11). Calculate GSB01CEN and GSB01MAX. Input 2T pulse signal to TP5 so that #5 amplitude is 300 mVp-p. Monitor #43 output waveform. When color SRT peak frequency is 4.5 MHz (0), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11) that are SR00MIN, SR00CEN, and SR00MAX as shown in the figure below. Set SR00MIN to 0dB, calculate GSB00CEN = 20 × log (SB00CEN/SB00MIN) and GSB00MAX = 20 × log (SB00MAX/SSB00MIN). T*** When color SRT peak is 5.8 MHz (1), measure gradients of color SRT gain for minimum (00), center (10), and maximum (11). Calculate GSR01CEN and GSR01MAX. Gradient 20% S*** = V***/T*** ― ― 4. 5. 6. 7. V*** 100% 20% 68 2005-08-18 TA1360ANG Note No. S02 Characteristics SW3 Dynamic Y/C compensation C SW8 B Test Conditions SW Mode SW4 SW5 A SW9 B A SW10 B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW7 B 1. Input 100-kHz sync signal to TP4, and set #4 amplitude to 0.2 Vp-p. Set Y mute OFF (P-MODE: Normal 1, 000), brightness to center (1000000), color to center (1000000), unicolor to maximum (1111111), and Y/C Gain Comp to minimum (00). Set black stretch point 1 to OFF (000), dark area static Yγ gain to minimum (00), light area static Yγ gain to maximum (11), and SW1 to B. Apply 5.16 V to #3 from external power supply PS1. Monitor #41 output waveform, and measure amplitude VBDY0. Set Y/C Gain Comp to maximum (11). Set SW1 to B. Set black stretch point 1 to OFF (000), dark area static Yγ gain to maximum (11), light area static Yγ gain to maximum (00), and monitor #41 amplitude VBDY1. Set Y/C Gain Comp to maximum (11). Switch SW1 to A, and TPI to GND. Set black stretch point 1 to maximum (111), dark area static Yγ gain to minimum (00), bright area static Yγ gain to maximum (11), and monitor #41 amplitude VBDY2. Calculate the following equations. GCBDY1 = 20 × log (VBDY1/VBDY0), GCBDY2 = 20 × log (VBDY2/VBDY0) 7. Input 100-kHz sync signal to TP5, and repeat the procedure above. Calculate the following equations. GCRDY1 = 20 × log (VRDY1/VRDY0), GCRDY2 = 20 × log (VRDY2/VBDY0) SW56 2. OPEN 3. 4. 5. 6. 69 2005-08-18 TA1360ANG Note No. S03 YUV gain Characteristics SW3 A/C SW8 B Test Conditions SW Mode SW4 SW5 A/B SW9 B A/B SW10 B Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW7 B SW56 OPEN 2. 3. 4. 5. 6. 7. 8. 9. 1. Set picture mute to OFF (P-MODE: Normal 1, 000), brightness to maximum (11111111), color to center (1000000), and unicolor to maximum (1111111). Set SW3 to A. Set SW4 and SW5 to B, and input 100-kHz sine wave to TPA. Set #3 amplitude to 0.2 Vp-p. Set SW56 open. Measure #56 amplitude VY00 and VY01 when Y/color difference input mode is set to Y/Cb/Cr (0) and Y/Pb/Pr (1). Set SW3 to C, SW4 to A, and SW5 to B. Input 100-kHz sine wave to TP4, and set #4 amplitude to 0.2 Vp-p. Measure #41 amplitude VB00 when Y/color difference input mode is set to Y/Cb/Cr (0). Measure #41 and #43 amplitude VBB01 and VBR01 when Y/color difference input mode is set to Y/Pb/Pr (1). Set SW3 to C, SW4 to B, and SW5 to A. Input 100-kHz sine wave to TP5, and set #5 amplitude to 0.2 Vp-p. Measure #43 amplitude VR00 when Y/color difference input mode is set to Y/Cb/Cr (0). Measure #41 and #43 amplitude VRB01 and VRR01 when Y/color difference input mode is set to Y/Pb/Pr (1). 10. Calculate the following equations. GY00 = 20 × log (VY00/0.2), GY01 = 20 × log (VY01/0.2) GCBB = 20 × log (VB00/0.2), GPBB = 20 × log (VBB01/0.2), GPBR = 20 × log (VBR01/0.2) GCRR = 20 × log (VR00/02), GPRB = 20 × log (VRB01/0.2), GPRR = 20 × log (VRR01/0.2) 70 2005-08-18 TA1360ANG Note No. S04 Characteristics SW3 Green stretch C SW33 A SW38 A Test Conditions SW Mode SW4 SW5 A SW34 A SW39 A A SW35 A Test Method (Test condition: VCC = 9 V/2 V, Ta = 25 ± 3°C) SW7 ⎯ 1. Input signal B as shown in the figure below from TP4 (Cb/Pb1 input), and signal A from TP5 (Cr/Pr input). Set brightness [06] to maximum (FF). Measure amplitudes A, B, C, D, and E at #42 (Gout) as shown in the figure below. (A00 to E00) Set green stretch [14] data to (08), and repeat the step 3 above. (A01 to E01) Set green stretch [14] data to (10), and repeat the step 3 above. (A10 to E10) Set green stretch [14] data to (18), and repeat the step 3 above. (A11 to E11) Green stretch gain is calculated by the following equations A01 A00 B01 GrB01 = B00 C01 GrC01 = C00 D01 GrD01 = D00 E01 GrE01 = E00 GrA01 = A10 A00 B10 GrB10 = B00 C10 GrC10 = C00 D10 GrD10 = D00 E10 GrE10 = E00 GrA10 = A11 A00 B11 GrB11 = B00 C11 GrC11 = C00 D11 GrD11 = D00 E11 GrE11 = E00 GrA11 = SW37 2. A 3. 4. 5. 6. 7. ⎯ ⎯ ⎯ ⎯ 0.05 Vp-p Signal A ±0 Vp-p −0.05 Vp-p −0.087 Vp-p −0.1 Vp-p ±0 Vp-p −0.07 Vp-p −0.122 Vp-p −0.122 Vp-p −0.14 Vp-p B C A Pin 42 150° 180° D 210° 240° E 270° Signal B 71 2005-08-18 TA1360ANG Test Conditions for Color Difference Block 2 Common Test Conditions for Color Difference Block 2 1. 2. 3. SW1 = B, SW2 = B, SW7~SW10 = B, SW20 = ON, SW23 = B Unless otherwise specified, measure each bus data with preset values. Set the following data. Subaddress (00) Data (02) Subaddress (02) Data (0C) Subaddress (05) Data (7F) Subaddress (06) Data (6C) Subaddress (07) Data (40) Subaddress (0B) Data (7F) Subaddress (0C) Data (84) Subaddress (12) Data (F0) Subaddress (13) Data (F0) Subaddress (15) Data (00) Subaddress (18) Data (00) Subaddress (1A) Data (C0) Subaddress (1B) Data (E0) Subaddress (1C) Data (03) Subaddress (1D) Data (78) Test Conditions SW Mode SW33 SW34 SW35 A A A Note No. A01 Characteristics SW3 Color difference contrast adjustment characteristic C SW4 A or B SW5 A or B Test Method SW37 A SW38 A SW39 A 1. 2. 3. Set brightness to maximum, and subaddress (12) data to (F0). Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.23 Vp-p) from pin 5. Change unicolor data to maximum (7F), center (40), and minimum (00), and measure pin 43 picture period amplitude VuCYMAX, VuCYCNT, and VuCYMIN respectively. Determine unicolor amplitude ratio between maximum and minimum in decibels. (∆VuCY) Repeat the steps 2 to 4 above with the following pins: Input (picture period amplitude 0.2 Vp-p) from pin 4, and measure pin 41. 4. 5. 72 2005-08-18 TA1360ANG Note No. A02 Characteristics SW3 Color adjustment characteristic C SW4 A or B SW5 A or B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. Set brightness to maximum, and subaddress (12) data to (F0). Input signal 3 (f0 = 100 kHz, picture period amplitude = 0.115 Vp-p) from pin 5. Change color data to maximum (7F), center (40), and minimum (01), and measure pin 43 picture period amplitudes VCCYMAX、VCCYCNT, and VCCYMIN respectively. Calculate amplitude ratios of maximum and minimum against color center in decibels. (∆VCCY) Repeat the steps 2 to 4 above with the following pins: Input (picture period amplitude 0.1Vp-p) from pin 4 and measure pin 41. Input signal 3 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 5. Measure pin 43 output picture period amplitude vHTARY. Apply 1.5 V to pin 52 from external power supply. Measure pin 43 output picture period amplitude vHTBRY. Calculate GHTRY = vHTBRY/vHTARY Repeat the steps 1 to 5 above and measure pin 42. Calculate GHTGY = vHTBGY/vHTAGY Repeat the steps 1 to 5 above and measure pin 4. Calculate GHTBY = vHTBBY/vHTABY. 4. 5. A03 Color difference halftone characteristic C A or B A or B A A A A A A 1. 2. 3. 4. 5. 6. 7. 73 2005-08-18 TA1360ANG Note No. A04 Characteristics SW3 Color γ characteristic C SW4 B SW5 A Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. Input signal 2 from pin 5. Increase signal 2 amplitude A. Determine gamma correction point Vγ1, Vγ2, and Vγ3 of subaddress data (14). Set subaddress (14) data as follows: (01) − γOFF (03) −γ1ON (05) −γ2ON (07) −γ3ON Measure #43 output signal amplitude levels and chart a characteristic diagram. 3. Determine Vγ where γ starts applying and gradient ∆ at γ ON when linearity at γ OFF is 1. #43 output amplitude γOFF Vγ γON #5 input amplitude 74 2005-08-18 TA1360ANG Note No. A05 Characteristics SW3 Color limiter characteristic C SW4 B SW5 A Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. C B A A A A A A A 1. 2. 3. 4. Input signal 2 (picture period amplitude = 0.56 Vp-p) from pin 4. Set subaddress (14) to (00)/(01), and measure pin 43 output signal picture period amplitude, CLT0/CLT1. Input signal 2 (picture period amplitude = 0.28 Vp-p) from pin 4. Adjust color so that pin 41 output picture period amplitude is 1.2 Vp-p. Set subaddress (0B) data to (80) and measure pin 41 output signal picture period amplitude v41. Calculate the following equation. HBC1 = (1.2 − v41)/1.2 A06 High-bright color gain 75 2005-08-18 TA1360ANG Test Conditions for Text Block Common Test Conditions for Text Block 1. 2. 3. SW1 = B, SW2 = B, SW7~SW10 = B, SW20 = ON, SW23 = B Unless otherwise specified, measure each bus data with preset values. Set the following data. Subaddress (00) Data (02) Subaddress (02) Data (0C) Subaddress (05) Data (7F) Subaddress (06) Data (6C) Subaddress (07) Data (40) Subaddress (0B) Data (7F) Subaddress (0C) Data (84) Subaddress (12) Data (F0) Subaddress (13) Data (F0) Subaddress (15) Data (00) Subaddress (18) Data (00) Subaddress (1A) Data (C0) Subaddress (1B) Data (E0) Subaddress (1C) Data (03) Subaddress (1D) Data (78) Test Conditions SW Mode SW33 SW34 SW35 A A A Note Characteristics No. T01 AC gain Test Method SW37 A SW38 A SW39 A 1. 2. 3. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Measure pins 41, 42, and 43 picture period amplitude, V41, V42, and V43. Calculate AC gain using the following equations. GR = V43/0.2 GG = V42/0.2 GB = V41/0.2 SW3 A SW4 B SW5 B T02 Y frequency characteristic 2 A B B A A A A A A 1. 2. 3. 4. 5. Set APACON f0 to (00), SRT gain to minimum, Sharpness gain to (1F) and Sub-contrast to (C). Input signal 1 (f0 = 1 MHz, picture period amplitude = 0.7 Vp-p) from pin 3. Measure pins 41, 42 and 43 picture period amplitude, GfY1. Calculate the difference among DC center voltages of RGB output amplitudes, VYDC1. As well, measure GfY15 and GfY30 against each input with f0 = 15 or 30 MHz, Calculate the difference among DC center voltages of RGB output amplitudes, VYDC15, and VYDC30. 76 2005-08-18 TA1360ANG Note Characteristics No. T03 Unicolor adjustment characteristic SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. T04 Brightness adjustment characteristic White peak slice level A B B A A A A A A 1. 2. 1. 2. 3. 4. T06 Black peak slice level RGB output S/N C B B A A A A A A 1. 2. C B B A A A A A A 1. 2. 3. 4. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Change unicolor data to maximum (7F), center (40), and minimum (00) and measure pin 43 picture period amplitude, VuMAX, VuCNT, and VuMIN respectively. Calculate amplitude ratio of VuMAX and VuMIN in decibels (∆Vu) Input signal 2 from pin 3 and adjust pin 43 picture period output amplitude to 1 Vp-p. Change brightness data to maximum (7F), center (80), and minimum (00) and measure pin 43 voltages, VbrMAX, VbrCNT, and VbrMIN respectively. Set subcontrast to maximum. Apply external power supply to pin 3 and gradually increase voltage from 5.8 V. When picture period of pin 43 is clipped, measure pin 43 picture period amplitude voltage, Vwps1. Change subaddress (0C) data to (FC) and repeat the steps 1 to 3 above. (Vwps2) Apply external power supply to pin 3 and gradually decrease voltage from 5.8 V. When picture periods are clipped, measure pins 41, 42, and 43 voltage, Vbps. Adjust brightness data so that picture period voltage of pin 41 is 2.4 V. Set color data to minimum. Measure noise levels n41-, n42-, and n43-Vp-p in picture period of pin 41, 42, and 43 with an oscilloscope. Calculate S/N. N41 = −20 × log [2.3/(0.2 × n41)] N42 = −20 × log [2.3/(0.2 × n42)] N43 = −20 × log [2.3/(0.2 × n43)] T08 Halftone characteristic A B B A A A A A A 1. 2. 3. 4. 5. 6. 7. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 3. Measure pin 41 picture period amplitude v41A. Apply 1.5 V to pin 52 from external power supply. Measure pin 41 picture period amplitude v41B Calculate the following equation. GHT1 = v41B/v41A T05 C B B A A A A A A T07 Stop applying voltage to pin 52. Set subaddress (1A) to data (E2) and measure pin 41-picture period amplitude, v41C. Calculate the following equation. GHT2 = v41C/v41A 77 2005-08-18 TA1360ANG Note Characteristics No. T09 BLK pulse delay time SW3 C SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. Apply signal shown in the figure (A) below to pin 24 (BLK input), and measure tdON and tdOFF of output signals from pins 41, 42, and 43 shown in the figure (B) below. 63.5 µs (A) Appling signal to pin 24 tdON tdOFF (B) Output signal from pins 41, 42, and 43 78 2005-08-18 TA1360ANG Note Characteristics No. T10 Drive adjustment variable range SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. 5. 6. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 3. Measure picture period amplitude of pin 42 when subaddress (0D) data is changed to maximum (FE), center (80), and minimum (00). Use picture period amplitude at center as the base. Determine amplitude ratio DRG1+ and DRG1− at maximum and minimum in decibels. Repeat the steps 1 to 3 above to measure amplitude ratio of pin 41, DRB1+ and DRB1− in decibels when subaddress (0E) data is changed. Repeat the steps 1 to 3 above to measure amplitude ratio of pin 42, DRG2+ and DRG2− in decibels when subaddress (0E) center data is set to (81) used as the base. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 41, DRB2+ and DRB2− in decibels when subaddress (0E) data is changed to maximum (FF), center (81), and minimum (01). Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 43, DRR1+ and DRR2− in decibels when subaddress (0D) data is changed to maximum (FF), center (81), and minimum (01). Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 41, DRB3+ and DRB3− in decibels when subaddress (0D) data is set to (81), and subaddress (0E) data is changed. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 42, DRG3+ and DRG3− in decibels when subaddress (0E) data is set to (81), and subaddress (0D) data is changed to maximum (FF), center (81), and minimum (01). 7. 8. 9. 10. Repeat the steps 1 to 3 above to measure picture period amplitude ratio of pin 43, DRR2+ and DRR2− in decibels when subaddress (0D) data is set to (81), and subaddress (0E) data is changed to maximum (FF), center (81), and minimum (01). T11 #53 input impedance C B B A A A A A A 1. 2. 3. Connect external power supply, an ammeter, and a voltmeter to pin 53. Adjust voltage so that current value is set to zero. Measure the current when voltage of pin 53 is increased by 0.2V. (lin) Calculate the following equation.Ｚin53 = 0.2 V/Iin (Ω) 53 − A + Ammeter (µA) V Voltmeter 79 2005-08-18 TA1360ANG Note Characteristics No. T12 ACL characteristic SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. 5. Input signal 1 (f0 = 100 kHz, picture period amplitude 0.2 Vp-p) from pin 3. Measure pin 43 picture period amplitude, vACL1. Apply “DC voltage of pin 53 − 0.8 V” to pin 53 from external power supply and measure pin 43-picture period amplitude, vACL2. Apply “DC voltage of pin 53 − 1.3 V” to pin 53 from external power supply and measure pin 43-picture period amplitude, vACL3. Calculate the following equations. ACL1 = −20 × log (vACL2/vACL1) ACL2 = −20 × log (vACL3/vACL1) T13 ABL point C B B A A A A A A 1. 2. 3. 4. Measure DC voltage of pin 53, VABL1. Set subaddress (1B) data to (1C). Apply external voltage to pin 53, and decrease voltage from 6.5 V. When voltage of pin 43 starts changing, measure pin 53 voltage, VABL2. Change subaddress (1B) data to (3C), (5C), (7C), (9C), (BC), (DC), and (FC) under the status of the step 3 above. Measure pin 53 voltage: VABL3, VABL4, VABL5, VABL6, VABL7, VABL8, and VABL9. ABLP1 = VABL2 − VABL1 ABLP5 = VABL6 − VABL1 ABLP2 = VABL3 − VABL1 ABLP6 = VABL7 − VABL1 ABLP3 = VABL4 − VABL1 ABLP7 = VABL8 − VABL1 ABLP4 = VABL5 − VABL1 ABLP8 = VABL9 − VABL1 5. 80 2005-08-18 TA1360ANG Note Characteristics No. T14 ABL gain SW3 C SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. 5. Apply 6.5-V external voltage to pin 53. Set subaddress (1B) data to (00). Set brightness data to maximum. Apply 4.5-V external voltage to pin 53. Change subaddress (1B) data to (00), (04), (08), (0C), (10), (14), (18), and (1C). Repeat the step 3 above, and measure VABL11, VABL12, VABL13, VABL14, VABL15, VABL16, VABL17, and VABL18. ABLG1 = VABL11 − VABL10 ABLG2 = VABL12 − VABL10 ABLG3 = VABL13 − VABL10 ABLG4 = VABL14 − VABL10 ABLG5 = VABL15 − VABL10 ABLG6 = VABL16 − VABL10 ABLG7 = VABL17 − VABL10 ABLG8 = VABL18 − VABL10 T15 RGB output mode C B B A A A A A A 1. 2. 3. 4. 5. Adjust brightness data so that picture period voltage of pin 43 is 2.4 V. Set subaddress (1B) data to (01). Measure pins 43, 42, and 41 picture period voltage, V43R, V42R, and V41R. Set subaddress (1B) data to (02), and repeat the step 3 above. Measure pins 43, 42, and 41 picture period voltage, V43G, V42G, and V41G. Set subaddress (1B) data to (03), and repeat the step 3 above. Measure pins 43, 42, and 41 picture period voltage, V43B, V42B, and V41B. 6. 81 2005-08-18 TA1360ANG Note Characteristics No. T16 Y-OUT γ characteristic SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. Input RAMP waveform from pin 3. Adjust input amplitude so that picture period amplitude of pin 43 is 2.3 Vp-p. Set subaddress (0C) data to (81). Adjust input amplitude so that picture period amplitude of pin 43 is 2.3 Vp-p. Monitor pin 43. According to the figure below, determine Y-OUT γ correction start points γ1 and γ2. Also determine ratios of gradients at Y-OUT ON to Y-OUT OFF in decibel. (∆1, ∆2, and ∆3) Output amplitude (Y-OUT) 100 IRE ∆3 γ2 ∆2 γ1 2.3 Vp-p ∆1 Note: Solid line indicates gamma OFF. Dotted line indicates gamma ON. Input amplitude 82 2005-08-18 TA1360ANG Note Characteristics No. T17 Whitepeak blue characteristic SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. 5. 6. 7. 8. Input 0.7-Vp-p RAMP signal from pin 3. Set subcontrast data to maximum. Set subaddress (1F) data to (04). Set subaddress (1E) data to (01), and monitor pin 41. Determine blue stretch start point BSPmin using the figure below. Repeat the step 4 above by changing subaddress (1E) data to (04) and (07). Determine blue stretch start point BSPCNT and BSPmax. Set subaddress (1E) data to (04). Monitor pin 41 and calculate ratio of blue stretch ON gradient in relative to blue stretch OFF gradient in decibel (BSGCNT) using the figure below. Repeat the step 7 above by changing subaddress (1F) data to (00) and (07). Calculate gradient ratio in decibel (BSGmin and BSGmax). Note: Calculate white-peak blue start point in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. ON Output (Output from pin 41) OFF Start point Input amplitude 83 2005-08-18 TA1360ANG Note Characteristics No. T18 ACB insertion pulse phase and amplitude SW3 A or C 2. 3. 4. SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Set brightness data to 108. Measure pins 46, 47, and 48 voltage. Apply measured voltages from external power supply. Set subaddress (02) data to (40). Use output signals from pins 43, 42, and 41, and measure ACB insertion pulse phase as shown in the Figure 1. Note: Take picture period following FBP input fall after V・BLK ends as phase 1H. After next H･ BLK, count the phase as 2H, 3H, and so on. ACB insertion pulse V･BLK period Figure 1: RGB Output 1H 2H 3H 4H Figure 2: FBP Input (#24) 5. 6. 7. Monitor pins 43, 42, and 41. Measure ACB insertion pulse amplitudes (level from picture period amplitude at quiescent.): VACB1R, VACB1G, and VACB2B. Set subaddress (02) data to (80), and repeat the step 5 above: VACB2R, VACB2G, and VACB2B. Set subaddress (02) data to (C0), and repeat the step 5 above: VACB3R, VACB3G, and VACB3B. 84 2005-08-18 TA1360ANG Note Characteristics No. T19 IK input amplitude SW3 A or C 2. 3. SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Set subaddress (02) data to (40). Measure voltage amplitude of pin-45 input signal in ACB insertion period. 1H = IKR T20 IK input cover range C B B A A A A A A 1. 2. 3. 4. 5. 6. 7. 8. T21 Analog RGB gain A B B A or B A or B A or B 2. 3. 4. 5. A A A 1. 2H = IKG 3H = IKB Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Set subaddress (02) data to (40). Measure pin 45 DC voltage in V･BLK period. (#45VBLK) Apply the current externally to pin 45. Measure DC voltage of pin 45 in V･BLK period when pin-43 picture period voltage begins to be decreased. (#45VBLK+) Apply current outward from pin 45. Measure DC voltage of pin 45 in V･BLK period when pin-43 picture period voltage begins to be increased. (#45VBLK−) DIKin+ = (#45VBLK+) − (#45VBLK) DIKin− = (#45VBLK−) + (#45VBLK) Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pin 49. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 35. Measure pin 43 picture period amplitude, v43R. Repeat the steps 3 and 4 above with the following pins: Input from pin 34, and measure output from pin 42 (v42G). Input from pin 33, and measure output from pin 41 (v41B). Calculate the following equations. GTXR = v43R/0.2 GTXG = v42G/0.2 GTXB = v41B/0.2 6 T22 Analog RGB white peak slice level A B B A A A A A A 1. 2. 3. 4. 5. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pin 49. Set RGB contrast data to maximum (7F). Input signal 2 to pin 35. Gradually increase picture amplitude, and measure picture period amplitude voltage when output from pin 43 is clipped. Repeat the steps 3 and 4 above with following pins: Input from pin 34 and measure output from pin 42. Input from pin 33 and measure output pin 41. 85 2005-08-18 TA1360ANG Note Characteristics No. T23 Analog RGB black peak limit level SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. 5. T24 RGB contrast adjustment characteristic A B B A or B A or B A or B 2. 3. 4. 5. 6. T25 Analog RGB brightness adjustment characteristic A B B A or B A or B A or B 2. 3. 4. 5. A A A 1. A A A 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pin 49. Set RGB contrast data to maximum (7F). Input signal 2 to pin 35. Gradually decrease picture amplitude, and measure picture period amplitude voltage when output from pin 43 is clipped. Repeat the step 4 above with the following pins: Input from pin 34 and measure output from pin 42. Input from pin 33 and measure output pin 41. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pin 49. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 35. RGB contrast data to maximum (7F), center (40), and minimum (00). Measure pin 43 picture period amplitudes VuTXR (maximum, center, and minimum) respectively. Calculate amplitude ratio of maximum and minimum in decibels. Repeat the steps 4 and 5 above with the following pins: Input from pin 34 and measure pin 42. Input from pin 33 and measure pin 41. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Input signal 2 from pins 33, 34, and 35. Apply 5-V external voltage to pin 49. Adjust amplitude A of signal 2 so that picture period amplitude of pin 43 is 0.5 Vp-p. Change RGB brightness data to maximum (FE), center (80), and minimum (00). Measure pins 43, 42, and 41 picture period voltage VbrTX (maximum, center, and minimum) respectively. Set RGB brightness data to maximum (FE). Input signal 4 (signal amplitude = 1.5 Vp-p) from pin 49. Measure input/output transfer characteristics using pin 43 according to the figure T-2. Repeat the steps 2 and 3 above with the following pins: Input from pin 34 and measure pin 42. Input from pin 33 and measure pin 41. Calculate maximum inter-axial rise/fall transfer delay time, using the data measured above. T26 Analog RGB mode switching transfer characteristic C B B A A A A A A 1. 2. 3. 4. 5. 86 2005-08-18 TA1360ANG Note Characteristics No. T27 Text ACL characteristic SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A B Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. 5. 6. 7. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pin 49. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 35. Measure pin 43 picture period amplitude, vTXACL1. Apply “pin 53 DC voltage − 0.8 V” to pin 53 from external power supply, and measure pin 43-picture period amplitude, vTXACL2. Apply “pin 53 DC voltage − 1.3 V” to pin 53 from external power supply, and measure pin 43-picture period amplitude, vTXACL3. TXACL1 = −20 × log (vTXACL2/vTXACL1) TXACL2 = −20 × log (vTXACL3/vTXACL1) T28 Analog OSD gain A B B A A A A or B A or B A or B 2. 3. 4. 5. 6. T29 Analog OSD input white peak slice level A B B A A A A A A 1. 2. 3. 4. T30 Analog OSD black peak limit level A B B A A A A A A 1. 2. 3. 4. 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pins 50 and 51. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 39. Measure pin 43 picture period amplitude, v43R. Repeat the steps 3 and 4 above with the following pins: Input from pin 38, and measure pin 42. Input from pin 37 and measure pin 41. (v42G and v41B) Calculate the following equations. GOSDR = v43R/0.2 GOSDG = v42G/0.2 GOSDB = v41B/0.2 Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pins 50 and 51. Input signal 2 from pin 39. Gradually increase picture amplitude, and measure picture period amplitude voltage when output from pin 43 is clipped. Repeat the step 3 above with the following pins: Input from pin 38, and measure pin 42. Input from pin 37, and measure pin 41. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pins 50 and 51. Input signal 2 from pin 39. Gradually decrease picture amplitude, and measure picture period amplitude voltage when output from pin 43 is clipped. Repeat the step 3 above with the following pins: Input from pin 38, and measure pin 42. Input from pin 37, and measure pin 41. 87 2005-08-18 TA1360ANG Note Characteristics No. T31 OSD contrast adjustment characteristic SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A or B SW38 A or B SW39 A or B 2. 3. 4. 5. 1. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pins 50 and 51. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 39. Change OSD contrast data to (11), (10), (01), and (00). Measure pin 43 picture period amplitude VuOSDR (11), (10), (01), and (00) respectively. Repeat the steps 3 and 4 above with the following pins: Input from pin 38, and measure pin 42, VuOSDG (11), (10), (01), and (00). Input from pin 37, and measure pin 41, VuOSDB (11), (10), (01), and (00). Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Apply 5-V external voltage to pins 50 and 51. Change OSD brightness data (subaddress 1D) to (38), (78), (B8), and (F8), and measure picture period voltage of pins 43, 42, and 41 respectively. Data (38) = VbrOSD0 Data (78) = VbrOSD1 Data (B8) = VbrOSD2 Data (F8) = VbrOSD3 T33 Analog OSD mode switching transfer characteristic C B B A A A A A A 1. 2. 3. 4. 5. 6. Set OSD brightness data to maximum (11). Input signal 4 (signal amplitude = 4.5 Vp-p) from pin 50. Measure input/output transfer characteristics using pin 43 according to the figure T-2. Repeat the steps 2 and 3 above, and measure pins 42 and 41. Calculate maximum inter-axial rise/fall transfer delay time, using the data measured above. Repeat the steps 1 to 5 above with the following pin. Input signal 4 (signal amplitude 4.5 Vp-p) from pin 51. T32 Analog OSD brightness adjustment characteristic C B B A A A A A A 1. 2. 3. 88 2005-08-18 TA1360ANG Note Characteristics No. T34 OSD ACL characteristic SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 B 1. 2. 3. 4. 5. 6. 7. 8. 9. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Control drive gain adjustment data so that pins 41 and 42 picture period amplitude equals that of pin 43. Set subaddress (07) data to (01). Apply 5-V external voltage to pins 50 and 51. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 39. Measure pin 43 picture period amplitude, vOSDACL1. Apply “pin 53 DC voltage − 0.8 V” to pin 53 from external power supply, and measure pin 43-picture period amplitude, vOSDACL2. Apply “pin 53 DC voltage − 1.3 V” to pin 53 from external power supply, and measure pin 43-picture period amplitude, vOSDACL3. OSDACL1 = −20 × log (vOSDACL2/vOSDACL1) OSDACL2 = −20 × log (vOSDACL3/vOSDACL1) OSDACL3、OSDACL4 Change subaddress (07) data to (80), and repeat the steps 6 to 8 above to measure OSDACL3 and OSDACL4. 89 2005-08-18 TA1360ANG Note Characteristics No. T35 OSD blending characteristic SW3 A ↓ C SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A ↓ B SW38 A ↓ B SW39 B ↓ B 1. 2. 3. 4. 5. 6. 7. 8. 9. Input signal 1(f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pin 3. Measure pins 41, 42, and 43 picture period amplitude, v41a, v42a, and v43a. Apply 5-V external voltage to pin 51. Measure pins 41, 42, and 43 picture period amplitude, v41b, v42b, and v43b. Calculate v41b amplitude in relation to v41a, v42b amplitude in relation to v42a, and v43b amplitude in relation to v43a in decibel: α41TV1, α42TV1, and α43TV1. Apply 5-V external voltage to pin 50, and repeat the steps 3 to 5 above: α41TV2, α42TV2, and α43TV2. Apply 5-V external voltage to pins 50 and 51, and repeat the steps 3 to 5 above: α41TV3, α42TV3, and α43TV3. Set SW3 to C. Set SW37, 38, and 39 to B. Input signal 1 (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) from pins 37, 38, and 39. 10. Apply 5-V external voltage to pins 50 and 51. 11. Measure pins 41, 42, and 43 picture period amplitude, v41c, v42c, and v43c. 12. Apply 5-V external voltage to pin 50. 13. Measure pins 41, 42, and 43 picture period amplitude, v41d, v42d, and v43d. 14. Calculate v41d amplitude in relation to v41c, v42d amplitude in relation to v42c, and v43d amplitude in relation to v43c in decibel: α41OSD1, α42OSD1, and α43OSD1. 15. Apply 5-V external voltage to pin 51, and repeat the steps 12 to 14 above: α41OSD2, α42OSD2, and α43OSD2. 16. Apply 5-V external voltage to pins 50 and 51, and repeat the steps 12 to 14 above: α41OSD3, α42OSD3, and α43OSD3. 90 2005-08-18 TA1360ANG Note Characteristics No. T36 Blue stretch point/gain SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. 5. 6. 7. 8. Input RAMP signal 0.7 Vp-p from pin 3. Set subcontrast data to maximum. Set subaddress (15) data to (0C). Set subaddress (1A) data to (C0), monitor pin 41, and measure blue stretch start point using the figure below (BLPmin). Set subaddress (1A) data to (CC), and repeat the step 4 above. (BLPmax) Set subaddress (1A) data to (C4). Monitor pin 41 and measure gradient at blue stretch ON in decibel in relation to the one at blue stretch OFF according to the figure below. (BLGmax) Set subaddress (15) data to (04), and repeat the step 7 above. (BLGmin) Note: Calculate blue stretch start point in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. Output amplitude Blue stretch ON Blue stretch OFF Input amplitude 91 2005-08-18 TA1360ANG Note Characteristics No. T37 Blue stretch gamma correction SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. 5. Input RAMP signal 0.7 Vp-p from pin 3. Set subcontrast data to maximum. Set subaddress (15) data to (08). Set subaddress (09) data to (81). Monitor pin 41 and measure amplitude of the intersection point of blue stretch γ OFF and blue stretch γ ON according to the figure below. Calculate pin 41 output amplitude in IRE as setting positive amplitude at pedestal level of output signal to 2.3 Vp-p = 100 IRE. Set subaddress (1A) data to (C4), (C8), and (CC). Repeat the step 5 above. (BLγ2, BLγ3, and BLγ4) Output amplitude Blue stretch γ OFF BLγ Intersection poiint Blue stretch γ ON 6. Input amplitude 92 2005-08-18 TA1360ANG Note Characteristics No. T38 White letters improvement SW3 A SW4 B SW5 B Test Conditions SW Mode SW33 SW34 SW35 A A A Test Method SW37 A SW38 A SW39 A 1. 2. 3. 4. Apply a pulse to pin 3 as shown in Figure A. Monitor # 43 output waveform. Plot # 43 output amplitude when changing # 3 input signal amplitude from 0 to 120 IRE (0.857 Vp-p) (See Figure B below). Set subaddress (19) data to (80). Monitor # 43 output waveform. Plot # 43 output amplitude when changing # 3 input signal amplitude from 0 to 120 IRE (0.857 Vp-p). Then, compare to the plot in the step 2, calculate a point where a gradient changes (WPL1). Repeat the step 4 above by changing subaddress (19) data to (83) and (86). Calculate points where gradients change (WPL2, WPL3). 5. 80 ns Figure A # 43 output amplitude Data 87 WPL3 Data 86 Data 83 WPL2 Data 80 WPL1 # 3 input amplitude Figure B 93 2005-08-18 TA1360ANG Test Condition for Synchronization Block Common Test Conditions for Synchronization Block: unless otherwise specified, VCC = 9 V, Ta = 25°C, bus data; preset value, SW3 = A, SW14 = A, SW INPUT = B, SW20 = ON, SW22 = OPEN, SW23 = B, SW24a = B, SW24b = OPEN, SW26 = B Note Characteristics Test Conditions Input signal A (as shown in the figure below) to TPA. Set subaddress (00) data to 82H. Monitor # 14 (Sync input) and #20 (AFC filter) waveforms. Measure phase difference (SPH). HA01 Sync input horizontal 1. sync phase 2. 29.36 µs Signal A 0.285 V 0.593 µs SPH #20 waveform HA02 HD input horizontal sync phase 1. 2. 3. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP 16. Monitor # 16 (Sync input) and #20 (AFC filter) waveforms. Measure phase difference (HDPH). 31.75 µs Signal B 1.5 V 2.35 µs HDPH #20 waveform 94 2005-08-18 TA1360ANG Note Characteristics 1. 2. 3. 4. 5. 6. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP16 pin. Decrease signal B duty from 10% (to shorter negative polarity period) and measure signal B duty (HDDUTY1) when #16 input signal phase no longer locks with that of #26 (H-OUT). Increase signal B duty from 10% (to longer negative polarity period) and measure signal B duty (HDDUTY2) when #24 (FBP input) phase changes in relation to signal B. Further increase signal B duty (to longer negative polarity period) and measure signal B duty (HDDUTY3) when #16 input signal phase no longer locks with that of #26 (H-OUT). Decrease signal B duty from 90 % (to shorter negative polarity period) and measure signal B duty (HDDUTY4) when #24 (FBP input) phase changes in relation to signal B. Test Conditions HA03 Polarity detection range 31.75 µs Signal B A B Duty = A/B × 100% (0 to 100%) HA04 Sync input threshold amplitude 1. 2. 3. 4. 5. 6. 1.5 V Set subaddress (00) data to 82H, and TEST mode to 01. Connect variable power supply to #14 via 20-kΩ resistor. Set variable power supply voltage to 0 V, and measure #14 voltage. (SYNC_TIP_00) Also check that #28 voltage is set to Low (GND level). Increase variable power supply voltage so that #28 voltage becomes High (VCC level). Measure #14 voltage. (SYNC_OFF_00) Calculate the following equation to determine SYNC input separation level at SYNC separation level is 00. VthS00 = (SYNC_OFF_00 − SYNC_TIP_00)/0.286 × 100 Change SYNC separation level to 01, 10, and 11. Calculate following equations to determine VthS01, VthS10, and VthS11. VthS01 = (SYNC_OFF_01 − SYNC_TIP_01)/0.286 × 100 VthS10 = (SYNC_OFF_10 − SYNC_TIP_10)/0.286 × 100 VthS11 = (SYNC_OFF_11 − SYNC_TIP_11)/0.286 × 100 ＃14 1H 0.08H 40IRE (= 286 mVp-p) Sync separation level Sync tip level ＃28 (SYNC output mode） 95 2005-08-18 TA1360ANG Note Characteristics 1. 2. 3. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP 16. Increase signal B amplitude from 0 Vp-p. When #26 (H-OUT) phase locks with that of signal B, measure signal B amplitude VthHD. 31.75 µs Test Conditions HA05 HD input threshold amplitude Signal B VthDH 2.35 µs HA06 Horizontal picture phase adjustment variable range 1. 2. 3. 4. Set subaddress (00) data to 40H. Input signal B (the figure is shown below) to TP16. Change subaddress (01) data from 80H to 00H, and measure phase change amount ∆HSFT− of #24 (H-OUT) waveform. Change slave address (01) data from 80H to FEH, and measure phase change amount ∆HSFT+ of #24 (H-OUT) waveform. 31.75 µs Signal B 1.5 V 2.35 µs #24 waveform Data: 00H ∆HSFT− #24 waveform Data: 80H ∆HSFT+ #24 waveform Data: FEH 96 2005-08-18 TA1360ANG Note Characteristics 1. 2. 3. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP16. Connect external voltage to #23 (curve correction), and measure phase change amount (∆H#23) of #26 (H-OUT) output waveform at 1.5 V and 3.5 V. 31.75 µs Test Conditions HA07 Curve correction amount Signal B 1.5 V 2.35 µs #26 waveform (#23 voltage; 1.5 V) ∆H#23 #26 waveform (#23 voltage; 3.5 V) HA08 Clamp pulse phase, width and level 1. 2. 3. 4. 5. 6. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP16. Measure #18 (SCP output) clamp pulse phase (CPS0), width (CPPW0), and output level (CPV0) in relation to signal B. Set subaddress (01) data to 81H, and repeat the step 3 above to measure (CPS1), (CPW1), and (CPV1). Apply no signal input to TP16. Measure #18 clamp pulse phase (CPS2), width (CPW2), and output level (CPV2) in relation to #24. 31.75 µs Signal B 2.35 µs CPS0/1 #18 waveform 1.5 V CPV0/1 CPW0/1 #24 waveform CPS2 #18 waveform CPV2 CPW2 97 2005-08-18 TA1360ANG Note Characteristics 1. 2. 3. 4. 5. Set subaddress (00) data to 40H. Set SW2 to C, SW3 to C, and SW24A to OPEN Input signal C (as the figure shown below) to #24 (FBP input). Measure #2 (BPH filter) black peak detection pulse phase (HBPS00a and HBPS00b) in relation to signal C. Set HBP-PHS 1/2 to (01), (10), and (11). Measure black peak detection pulse phase. Test Conditions HA09 Black peak detection pulse phase and level 31.5 µs 4.13 µs 2V Signal C 0V HBPS**a HBPS**b #2 waveform HA10 FBP input threshold 1. 2. 3. Set subaddress (00) data to 40H. Input signal B (as shown in the figure below) to TP16. Increase amplitude of FBP signal to be input to #24 (FBP input) from 0 Vp-p. When #26 (H-OUT) phase locks with that of signal B, measure #24 input amplitude VthFBP. 31.75 µs 1.5 V 2.35 µs 98 2005-08-18 TA1360ANG Note Characteristics 1. 2. No signal input. Measure T1 and T2 (as shown in the figure below) from #26 (H-OUT) output waveform when subaddress (00) data is 80H and A0H. Calculate duties (THA and THB) using the following equation: TH = T1/(T1 + T2) × 100 % T1 T2 Test Conditions HB01 H-OUT pulse duty #26 waveform HB02 Horizontal free-run frequency 1. 2. 3. Set SW20 to open. Set subaddress (00) data to 01H and measure horizontal free-run frequency (F15K) according to #26 (H-OUT) output waveform. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Measure horizontal free-run frequency F28K, F31K, F33K, F37K, and F45K as in the step 2 above. Set subaddress (00) data to 01H. Connect 10-kΩ resistor between #20 and VCC. Measure horizontal frequency (F15KMIN) according to #26 (H-OUT) output waveform. Connect 68-kΩ resistor between #20 and GND. Measure horizontal frequency (F15KMAX) according to #26 (H-OUT) output waveform. Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Repeat the steps 2 and 3 above and measure horizontal frequencies F28KMIN, F28KMAX, F31KMIN, F31KMAX, F33KMIN, F33KMAX, F37KMIN, F37KMAX, F45KMIN, and F45KMAX. Set SW20 to open. Connect external power supply to TP 20, and set subaddress (00) data to 01H. Apply V20 + 0.05 V, and V20 − 0.05 V to TP 20. Measure frequencies FA and FB according to #26 (H-OUT) output waveform. Calculate frequency change rate (BH15K) using the following equation. BH15K = (FB − FA)/0.1 Set subaddress (00) data to 00H, 41H, 81H, C0H, and C1H. Repeat the step 2 above, and measure frequency change rate BH28K, BH31K, BH33K, BH37K, and BH45K Set SW26 to open. Measure voltage at High (V26H) and Low (V26L) of #26 (H-OUT) output waveform. HB03 Horizontal oscillation frequency variable range 1. 2. 3. 4. HB04 Horizontal oscillation control sensitivity 1. 2. 3. 4. HB05 H-OUT output voltage 1. 2. 99 2005-08-18 TA1360ANG Note V01 Characteristics VP output pulse width, Vertical free-run (maximum pull-in range) 1. 2. 3. 4. Test Conditions Input signal D (shown in the figure below) to TP 16, and signal E (shown in the figure below) to #24 (FBP input). Measure VP output pulse width (VPw) according to TP 27 output waveform. Measure VP pull-in range (VPt0) according to TP 27 output waveform. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure pull-in range VPt1, VPt2, VPt3, VPt4, VPt5, and VPt6 as in the step 3 above. 2.35 µs 29.63 µs Signal D (TP 16 input signal) 5.6 µs Signal E (#24 input waveform) 9V 4V GND #24 input waveform TP 27 waveform VPw VPt V02 Vertical minimum pull-in range 1. 2. 3. Repeat the step 1 of Note# V01. Input signal F (shown in the figure below) to TP 15. Increase signal-F cycle from 30H. Measure the cycle (TVPULL) when phase locks with that of TP 27. Signal F (TP 15 waveform input) 3H TVPULL #24 input waveform TP 27 waveform 100 2005-08-18 TA1360ANG Note V03 Characteristics Vertical black peak detection pulse 1. 2. 3. 4. Test Conditions Repeat the step 1 of Note# V01. Set SW2 to C, and SW3 to C. Input signal F (shown in the figure below) to TP 15. Measure phase differences VBPP0E and VBPP0S according to #2 output waveform. Set subaddress (03) data to 01H, 02H, 03H, 04H, 05H, and 06H. Measure phase differences VBPP1E, VBPP1S, VBPP2E, VBPP2S, VBPP3E, VBPP3S, VBPP4E, VBPP4S, VBPP5E, VBPP5S, VBPP6E, and VBPP6S as in the step 3 above. Signal F (TP 15 waveform input) 3H 262.5H to 1125H #24 input waveform VBPPS VBPPE #2 waveform V04 Vertical blanking stop 1. phase 2. 3. Repeat the step 1 of Note# V01. Input signal F (shown in the figure below) to TP 15. Set subaddress (03) data to 00H and F0H. Measure blanking stop phase VBLKMIN and VBLKMAX according to #43 output waveform. Signal F (TP 15 waveform input) 3H 1125H #24 input waveform VBLK #24 input 101 2005-08-18 TA1360ANG (1) Video signal 63.5 µs Sine wave of frequency f0 (2) Input signal 1 (3) Input signal 2 Amplitude A Sine wave of frequency f0 (4) Input signal 3 Figure T-1 Signals for Text/Color Difference Signal 2 102 2005-08-18 TA1360ANG 63.5 µs 20 µs 20 µs 20 µs 20 ns 20 ns (1) Input signal 4 50% (2) 0% 10% tPR tPF 50% 90% 100% tPR τR τF tPF (3) 0% 10% 50% 90% 100% τR τF Figure T-2 Test Pulses for Text/Color Difference Signal 2 103 2005-08-18 1 µF 470 Ω A LED 2 kΩ B SW2 100 kΩ C 1 µF 20 kΩ TP1 #56 30 pF #1 SW56 10µF 100 µF SW54 0.01 µF 1 kΩ #53 TP54 TP53 A 56 1 3.9 kΩ #55 #2 55 2 0.1 µF BPH FILTER Y/C VCC #54 54 VSM OUT A B #3 20 kΩ SW3 3 Y1 IN TP4 #4 C TPB 0.1 µF A 53 4 SW4 0.1 µF #5 52 5 Cr1/Pr1 IN Y/C GND YS 1 (analog OSD) YS 2 (analog OSD) YS 3 (analog RGB) R S/H YM/P-MUTE/BLK ABCL IN TP5 BA TPC SW5 B 0.1 µF 6 10 µF 3.9 kΩ TP7 #7 A 7 LIGHT AREA DET FILTER Y2 IN BA 0.47 µF #8 0.1 µF 8 SW INPUT 0.1 µF B #9 A 9 SW9 0.1 µF #10 10 Cr2/Pr2 IN COLOR LIMITER 12 Cb2/Pb2 IN BA TP10 16 1 SW10 B 0.1 µF #11 11 15 2 2.2 µF #12 14 3 50 kΩ 7.5 kΩ 0.01 µF 30 kΩ 100 Ω 0.1 µF TP15 100 Ω TP16 100 Ω TP17 100 Ω TP18 100 Ω 0.01 µF 1200 pF 0.01 µF 14 50 kΩ 7.5 kΩ 13 4 470 Ω 100 µF #20 1 kΩ 1 µF 3 kΩ SW20 13 4 #13 13 1200 pF SW8 TP9 A SW7 B VSM FILTER H-FREQSW1 #14 75 Ω 5.1 kΩ 2 kΩ TPD 5.1 kΩ 50 kΩ 1000 pF 51 kΩ 12 5 A 10 µF 51 kΩ TP14b B SW14 11 6 10 7 TC4538BP TP13 TP14a 14 SYNC IN #15 15 VD IN #16 16 HD IN #17 17 TA1360ANG 51 50 49 48 47 G S/H 46 B S/H 45 IK IN RGB GND 44 43 R OUT 42 G OUT 41 B OUT Cb1/Pb1 IN #48 #47 #46 #45 #43 #42 #41 0.47 µF SW1 DARK AREA DET FILTER APL FILTER B TPA 75 Ω 5.1 kΩ 2 kΩ 10 µF 0.01 µF #52 0.01 µF 0.01 µF 0.01 µF 6.8 V 300 pF 10 kΩ 10 kΩ #51 #50 #49 10 kΩ 10 kΩ 100 Ω 100 Ω 100 Ω #40 100 µF 40 SCP IN #18 RGB VCC 18 CP OUT ANALOG OSD R IN 0.01 µF #39 39 0.1 µF #38 19 38 DEF/DAC VCC 20 AFC FILTER #21 ANALOG OSD G IN 0.1 µF #37 37 ANALOG OSD B IN 10 kΩ 10 kΩ 10 kΩ 100 kΩ Test Circuit 104 8 9 15.75 kHz 16 1 15 2 3 5.1 kΩ 50 kΩ 1000 pF 51 kΩ 5 10 µ F 51 kΩ 6 7 8 12 11 10 B 9 TC4538BP 31.5/33.75 kHz 5.1 kΩ 50 kΩ 14 3 4 1000 pF 51 kΩ 5 10 µ F 51 kΩ 6 7 8 45 kHz B 16 1 2 TC4538BP 15 13 12 11 10 9 VCC (9 V) 50 kΩ 7.5 kΩ 1200 pF A BA BA B SW39 TP39 SW38 TP38 SW37 0.1 µF #36 21 36 HVCO CSBLA503KECZF30 15 kΩ 15 kΩ 15 kΩ TP23a A 100 Ω SW23 A C A SW26 C TP27 3.9 kΩ #27 5.1 kΩ 1 kΩ 30 kΩ B SW24A 10 kΩ 10 kΩ #26 1 µF SW24b 25 32 DEF/DAC GND 26 I L GND 2 TP37 9V TP20 TP21 DAC2 (ACB pulse) #22 #23 22 23 10 kΩ A #35 35 ANALOG R IN H-FREQ SW2 TP23b H CURVE CORRECTION #24 #28 24 27 28 FBP IN 34 ANALOG G IN 33 ANALOG B IN 31 SDA H-OUT 30 SCL VP OUT 2 SW35 0.1 µF #34 #33 #31 470 Ω #30 470 Ω #29 29 I L VDD DAC1 (SYNC OUT) 0.1 µF BA BA B TP35 SW34 TP34 SW33 0.1 µF TP33 2.0 V 0.1 µF TP31 TP30 1/2W 220 Ω VCC (9 V) TA1360ANG 2005-08-18 Cb/Pb1-IN 75 Ω Y1-IN 10 µF 2.2 µF 100 µF Y/C VCC 0.01 µF VSM-OUT 100 kΩ 0.01 µF 52 54 VSM OUT 47 µ H 55 56 1 75 Ω 10 µF 0.47 µF 2 1 µF 3 M ○ 0.1 µF Application Circuit 1 kΩ 5.1 kΩ BPH FILTER 1 kΩ Y1 IN 10 µ F 53 4 M ○ 0.1 µF DARK AREA DET FILTER APL FILTER 75 Ω 1 kΩ 5 M ○ 0.1 µF 75 Ω 9 10 µ F M ○ 0.1 µF 1 kΩ 11 2.2 µF 0.01 µF Cr/Pr1-IN 3.9 kΩ Cb1/Pb1 IN ABCL IN Cr1/Pr1 IN Y/C GND YS 1 (analog OSD) YS 2 (analog OSD) YS 3 (analog RGB) R S/H YM/P-MUTE/BLK YM 51 6 Ys1 Y2-IN 10 µF Cb/ Pb2-IN 10 µF 75 Ω 7 5.1 kΩ 0.47 µF 8 M ○ 0.1 µF ABCL 75 Ω 3.9 kΩ Y2 IN LIGHT AREA DET FILTER Ys2 50 Cr/Pr2-IN 1 kΩ 1 kΩ Cb2/Pb2 IN Cr2/Pr2 IN COLOR LIMITER 12 10 M ○ 0.1 µF Ys3 49 48 47 G S/H 46 B S/H 45 2.2 µF 2.2 µF 2.2 µF 300 pF SYNC-IN 10 µF 13 3.9 kΩ 14 0.1 µF VD-IN 15 75 Ω 5.1 kΩ 1 kΩ VSM FILTER IK IN H-FREQ SW1 RGB GND 30 kΩ 44 43 6.8 V SYNC IN R OUT 100 Ω 100 Ω 42 G OUT VD IN 16 100 Ω 41 IK IN R-OUT TA1360ANG G-OUT 105 1.5 kΩ B H-FREQ 560 Ω 0.1 µF A 1 kΩ 31.5 kHz 33.75 kHz 45 kHz H * 9V 0V Tr. Application of H-FREQ switching (31.5 k/33.75 k/45 kHz) HD-IN HD IN B OUT B-OUT 100 µF 17 40 SCP-IN SCP IN RGB VCC 18 CP-OUT CP OUT 100 µF 0.01 µF 1 µF 3 kΩ M ○ 0.01 µF 47 µ H 0.01 µF 39 ANALOG OSD R IN ANALOG OSD G IN DEF/DAC VCC 20 CSBLA503KECZF30 22 35 H-FREQ SW2 470 Ω ANALOG R IN 21 AFC FILTER 0.1 µF 19 38 37 ANALOG OSD B IN 36 DAC2 (ACB pluse) HVCO 30 kΩ 0.1 µF 23 34 CURVE CORR H CURVE CORRECTION 24 FBP-IN 10 kΩ FBP IN 25 ANALOG G IN 0.1 µF 33 ANALOG B IN 2 OSD R-IN 0.1 µF 0.1 µF OSD G-IN OSD B-IN DAC2-OUT ANALOG R-IN ANALOG G-IN 0.1 µF 32 DEF/DAC GND 1 kΩ 26 H-OUT H-OUT VP-OUT A L L I L GND ANALOG B-IN 31 SDA SDA *: Don’t care 470 Ω 27 28 30 VP OUT 2 SCL SCL 470 Ω 29 DAC1-OUT 30 kΩ B L 9V 3V 9V 6V H DAC1 (SYNC OUT) I L VDD M ○: Mylar capacitor 0.01 µF 2.0 V 47 µ H VCC VCC Pin 13 voltage Pin 22 voltage TA1360ANG 2005-08-18 TA1360ANG ACB Application Circuit +B CRT CRT CRT R G B IK IN 51~330 pF 6.8 V Z CLAMP 45 1 Vp-p R G B 0~3.0 V (DC) 20~51 kΩ 106 2005-08-18 TA1360ANG Package Dimensions Weight: 5.55 g (typ.) 107 2005-08-18 TA1360ANG 108 2005-08-18