TA1375FG

TA1375FG TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC TA1375FG Single Conversion Tuner for Digital TV / CATV The TA1375FG is a tuner IC for for Digital TV and CATV applications that integrates a PLL block and mixer, oscillator, IF amplifier and IF GCA on a single chip. This oscillator and PLL circuits are low phase noise. The control data of the PLL block conforms to I²C-bus formats. Small flat package : LQFP48(0.5mm pitch) LQFP48-P-0707-0.5 Features Vcc: 5V（typ.） Weight: 0.17g (typ.) Two-band mixer Three-band oscillator Low phase noise oscillator circuit Built-In IF GCA circuit IF output driver GCA block: Gain changeover switch (3dB shift possible) Direct 2 modulus type frequency synthesizer I²C bus format control 33V high voltage tuning amplifier built-in Four-bit bandswitch drive transistor Frequency step : 50kHz, 62.5kHz, 142.86kHz, 166.67kHz (when a 4MHz crystal is used.) Four-programmable chip address Power-on reset circuit Package: Pb-free Power on reset status Frequency step : [62.5kHz] Charge pump current: [Low] Counter data: ALL [ 0 ] Band driver: [OFF] Tuning amplifier: [OFF] (charge pump is sink mode) Local oscillator and mixer: ALL [OFF] note1: These devices are easy to be damaged by high voltage or electric fields. In regards to this, please handle with care. note2: Install the product correctly. Otherwise, it may result in break down, damage and/or degration to the product or equipment. 2005/05/23 1 TA1375FG Block Diagram VHF-H OSC-C2 VHF-H OSC-B1 VHF-H OSC-C1 VHF-L OSC-C 36 Vcc4 (OSC) IF output GND5 (IF AMP) Vcc5 (IF) GND6 (IF DRIVER) GND7 (GCA) IF input1 IF input2 Vcc6 (GCA) GND8 (AMP) Gain SW (GCA) N.C. 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND3 (Mix) UHF RF input2 UHF RF input1 UHF PORT VHF RF input2 VHF RF input1 Vt output NF Vcc3 (MIX) VHF-H PORT VHF-L PORT FMT PORT 37 38 39 40 41 42 43 44 45 46 47 48 48 1 IF output1 GCA control Lock Detector Band Switch Power on Reset VHF-L OSC-B UHF OSC-B2 UHF OSC-E2 UHF OSC-E1 UHF OSC-B1 GND4 (OSC) MIX output2 MIX output1 Programmable Divider Charege Pump Phase Comparator Reference Divider 19 18 17 16 Band Driver 15 14 I2C bus Interface 13 8 Vcc1 (PLL) 2 IF output2 3 GCA control 4 GND1 (PLL) 5 SDA in/output 6 SCL input 7 ADR set 9 GND2 (PLL) 10 X'tal 1 11 X'tal 2 12 Vcc2 (BAND) Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purpose. 2005/05/23 2 TA1375FG Terminal Name Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin name IF output 1 IF output 2 GCA control terminal GND 1 (PLL) SDA In/out SCL In ADR set (address setting) Vcc 1 (PLL) GND 2 (PLL) Crystal 1 Crystal 2 Vcc 2 (BAND) FMT port (NPN-Tr) VHF-L port (NPN-Tr) VHF-H port (NPN-Tr) Vcc 3 (MIX) NF Vt output VHF RF Input 1 VHF RF Input 2 UHF port (NPN-Tr) UHF RF Input 1 UHF RF Input 2 GND 3 (MIX) VHF-L OSC-base VHF-L OSC-collector UHF OSC-base1 UHF OSC-emitter1 UHF OSC-emitter2 UHF OSC-base2 VHF-H OSC-collector1 VHF-H OSC-collector2 VHF-H OSC-base1 GND 4 (OSC) MIX output 1 MIX output 2 Vcc 4 (OSC) IF out GND 5 (IF AMP) Vcc 5 (IF) GND 6 (IF DRIVER) GND 7 (GCA) IF Input 1 IF Input 2 Vcc 6 (GCA) GND 8 (AMP) Gain SW（GCA） （Open: typical / GND:＋3dB gain up） N.C. （This pin does not connect the Inside circuit.） 2005/05/23 3 TA1375FG Terminal Function The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purpose. Pin No. Pin Name. Function Interface Vcc 1 IF output 2 IF output pin for the GCA block. Symmetrical output type. 1 2 GND Vcc Gain control pin of GCA block. 3 GCA control The gain of GCA block Is controllable by the voltage given to this pin. 160kΩ 40kΩ 3 GND 4 GND1 This Is the ground pin for the PLL circuit. ⎯ Vcc 5 SDA Serial data Input and output pin 5 22Ω 1kΩ 70kΩ GND Vcc 6 SCL Serial clock Input pin 6 1kΩ GND 2005/05/23 4 TA1375FG Pin No. Pin Name. Function Interface Vcc 150kΩ 100kΩ 1kΩ Address setting pin 7 ADR set The address of the PLL block Is set up using the voltage applied to this pin. 7 100Ω 50kΩ GND 8 9 Vcc1 GND2 This Is power supply for the PLL circuit. This Is the ground pin for the PLL circuit. ⎯ ⎯ Vcc 10 11 Crystal oscillator input pins. Crystal A 4MHz crystal is used. 10 11 50kΩ GND 12 Vcc2 This Is power supply for the Band circuit. ⎯ Vcc 13 14 15 21 Band driver Output port The output port of the band block can be set up using the control data. Bear in mind that drive current differs according to each band drive port. DATA I/F 13 14 15 21 GND 16 Vcc3 This Is power supply for the Mixer circuit. ⎯ Vcc 17 NF Be sure to connect a resistance (of about 33kΩ) between pin18 and the 33V external power supply for tuning. To prevent abnormal oscillation, connect between pin18 and GND a capacity element that does not affect a PLL. 18 Vt output 18 50Ω 50Ω GND 17 Vcc 2005/05/23 5 TA1375FG Pin No. Pin Name. Function Interface Vcc 3kΩ RF signal Input pin for the VHF band. 19 VHF RF input 20 It can be symmetrical Input, asymmetrical Input by grounding of one pin with a capacity element. 3kΩ 3kΩ 19 20 GND Vcc 22 UHF RF input 23 It can be symmetrical Input, asymmetrical Input by grounding of one pin with a capacity element. 3kΩ RF signal Input pin for the UHF band. 22 23 GND This Is the ground pin for the Mixer circuit. ⎯ 24 GND3 Vcc 26 25 6kΩ 6kΩ 25 26 VHF-L band Local oscillator Local oscillator for the VHF-L band The oscillator type Is symmetrical amplifier. GND Vcc 8kΩ 8kΩ 27 28 29 30 UHF band Local oscillator Local oscillator for the UHF band The oscillator type Is balanced clap. 27 28 3kΩ 3kΩ 30 29 GND Vcc 32 31 32 33 VHF-H band Local oscillator Local oscillator for the VHF-H band 6kΩ 31 6kΩ The oscillator type Is symmetrical amplifier. 33 GND 2005/05/23 6 TA1375FG Pin No. 34 Pin Name. GND4 Function This Is the ground pin for the Local oscillator circuit. Interface ⎯ Vcc Mixer output pins 35 Mixer ouytput 36 A tank circuit Is connected between the pins for tuning. Since these are open collector outputs, be sure to connect with a power supply through a load. (resistance, coil). 35 36 GND 37 Vcc4 This Is power supply for the Local oscillator circuit. ⎯ Vcc IF output 38 (MOP) IF output pin for the MOP block Asymmetrical output type. 38 GND 39 40 41 42 GND5 Vcc5 GND6 GND7 This Is the ground pin for the IF amplifier circuit. This Is power supply for the IF circuit. This Is the ground pin for the IF output circuit. This Is the ground pin for the GCA circuit. ⎯ ⎯ ⎯ ⎯ Vcc 43 44 IF input pin for the GCA block. IF Input Symmetrical Input type. 43 1.2kΩ 1.2kΩ 44 GND 2005/05/23 7 TA1375FG Pin No. 45 46 Pin Name. Vcc6 GND8 Function This Is power supply for the GCA circuit. This Is the ground pin for the GCA output circuit. Interface ⎯ ⎯ Vcc It Is the voltage gain changeover SW. Gain SW 47 (GCA) It changes by setting this pin to Open or GND. When based on an open state, about 3dB voltage gain can be increased by setting a pin to GND. 120kΩ 50kΩ 47 370kΩ GND This pin does not connect the Inside circuit. 48 N.C. ⎯ 2005/05/23 8 TA1375FG Maximum Ratings CHARACTERISTIC PIN No 8 12 16 37 40 45 18 ⎯ ⎯ ⎯ ⎯ Vcc Tuning Amplifier Voltage Applied Input Terminal Voltage Power Dissipation Operating Temperature Storage Temperature SYMBOL Vcc1 Vcc2 Vcc3 Vcc4 Vcc5 Vcc6 VBT VIN PD Topr Tstg RATING 6 6 6 6 6 6 38 GND-0.3∼Vcc+0.3 1190 (note4) -20∼85 -55∼150 UNIT V V V mW ℃ ℃ note3: The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be exceeded during operation, even for an instant. If any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, these operations with exceeded ratings may cause break down, damage and/or degradation to any other equipment. Applications using the device should be designed such that each maximum rating will never be exceeded in any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this documents. note4: 50 × 50 × 1.6mm, Cu36% board used. When using the device at above Ta=25 ℃ , decrease the power dissipation by 9.6mW for each Increase of 1℃ Operating Supply Voltage Pin No. 8 12 16 37 40 45 SYMBOL Vcc1 (PLL) Vcc2 (BAND) Vcc3 (MIX) Vcc4 (OSC) Vcc5 (IF) Vcc6 (GCA) MIN. 4.5 4.5 4.5 4.5 4.5 4.5 TYP. 5.0 5.0 5.0 5.0 5.0 5.0 MAX. 5.25 5.25 5.25 5.25 5.25 5.25 UNIT V 2005/05/23 9 TA1375FG Electric Characteristics （Unless otherwise specified,Vcc1 = Vcc2 = Vcc3 = Vcc4 = Vcc5 = Vcc6 = 5V, Ta = 25℃） TEST CHARACTERISTICS Power Supply and current Icc1+Icc2+Icc3+Icc4 +Icc5+Icc6(total) Down Converter Block VHF-L RF=90MHz -30dBmWin Conversion (see1) Gain CG 3 VHF-H RF=465MHz -30dBmWin UHF UHF RF=471MHz -30dBmWin RF=855MHz -30dBmWin 19.0 20.5 22.0 21.5 9 9 9 9 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 21.5 23.0 24.5 24.0 10 10 10 10 24.0 25.5 27.0 26.5 ⎯ ⎯ ⎯ ⎯ ±0.5 ±0.5 ±1.0 ±1.0 dB dBmW dB SYMBOL CIRC- BAND UIT Icc (total) VHF-L Bus data :B1 : ON(IBD=0mA) 1 VHF-H Bus data :B2 : ON(IBD=0mA) UHF Bus data :B3 or B4 : ON(IBD=0mA) 73 73 76 88 88 91 108 108 111 mA TEST CONDITION (note5,6,7) MIN. TYP. MAX. UNIT VHF-L RF=90MHz IF Output Power Level (see2) Ifp 3 VHF-H RF=465MHz UHF UHF RF=471MHz RF=855MHz VHF-L RF=90MHz –30dBmWin Conversion (see3) Gain Shift CGs 3 VHF-H RF=465MHz -30dBmWin UHF UHF Gain Control Amplifier Block (Pin47 = Open) Maximum Typical Minimum Gain Voltage Voltage Voltage G a i n VGmax Gain VGtyp 3 3 3 3 3 3 3 3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 ⎯ ⎯ 1 1 3 3 1 1 1 1 1 1 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 15-bits counter Pin5,6 Pin5,6 Pin5,6 Pin5,6 CP = 0 CP = 1 Isink = 3mA VGCA=3V, RF=-60dBmW VGCA=1.7V, RF=-37.5dBmW VGCA=0.5V, RF=-15dBmW VGCA=0.5∼3V VGCA=1.7V VGCA=1.1∼2.3V ⎯ Pin3 (apply voltage=0∼Vcc6) RF=471MHz -30dBmWin RF=855MHz -30dBmWin 45.0 21.5 -5.0 46 27 ⎯ 1.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.3 ⎯ 47.0 23.5 -3.0 50 30 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.15 ⎯ ⎯ 49.0 25.5 -1.0 54 33 ±1 ⎯ 50 dB dB/V dB Vp-p uA dB G a i n VGmin GR Sgain LGCA Variable Range Gain Control Sensitivity L i n e a r i t y Maximum Output Signal Amplitude Vomax Flow Into Current of PIN3 PLL Block IBD-FMT B a n d P o r t D r i v e C u r r e n t IBD-VHF IBD-UHF Band Port Drive Maximum Current IBDmax B and Port Drive Voltage Drop VBDsat T uning Amplifier Output Voltage (Close Loop) Tuning Amplifier Maximum Current Crystal Negative Resistance Ratio Setting Range Vt out Ivt XtR N VBsL VBsH I BsL I BsH Ichg VACK Cont-I Pin13 (FMT port) Pin14,15 (VHF port) Pin21 (UHF port) Maximum drive current / 2 port ON With each port at maximum current drive. 1 port ON Isink = 3mA VBT = 33V ⎯ 5 20 15 25 0.2 33 3 1.5 ⎯ mA V V mA kΩ mA 1.2 1024 -0.3 2.0 -20 -10 ±115 ±165 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32767 Ratio 1.1 Vcc2 +0.3 10 20 ±175 ±255 0.4 V V uA uA uA V Logic Input Low Voltage Logic Input High Voltage Logic Input Current (Low) Logic Input Current (High) Charge Pump Output Current ACK Output Voltage ±145 ±210 ⎯ note5: IF output frequency=43.75MHz、note6: IF output load=75Ω、note7: VGCA=voltage value applied to Pin3 2005/05/23 10 TA1375FG Reference Data（Unless otherwise specified,Vcc1=Vcc2=Vcc3=Vcc4=Vcc5=Vcc6=5V, Ta = 25℃） (The data is a reference value and is not guaranteed.) CHARACTERISTICS Down Converter Block VHF-L RF=90MHz Noise (see4) Figure (MO) NF 3, 4 VHF-H RF=465MHz UHF UHF OSC (see5) Frequency Shift △fB 3 RF=471MHz RF=855MHz ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 86 82 83 79 62 59 57 55 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 42 13.5 11.0 11.5 11.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 89 85 86 82 65 62 60 58 -75 -65 -72 -62 -65 -64 -89 -89 -90 -88 -89 -90 4.7 5.2 7.0 12.0 20.5 50 15.0 12.5 13.0 12.5 ±200 ±500 ±500 ±500 ±500 ±1000 ±500 ±1000 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ -68 -58 -64 -58 -58 -58 -86 -86 -86 -86 -86 -86 6.2 6.7 8.0 13.0 21.5 ⎯ dB dB dBc/Hz dBc/Hz dB dBuV kHz kHz dB SYMBOL TEST CIRCUIT BAND TEST CONDITION (note5,6,7) MIN. TYP. MAX. UNIT VHF-L OSC=133.75MHz (The PLL is not operating) VHF-H OSC=508.75MHz UHF UHF Switch (see6) On Drift △fs 3 OSC=514.75MHz OSC=898.75MHz VHF-L OSC=133.75MHz (The PLL is not operating) VHF-H OSC=508.75MHz UHF UHF OSC=514.75MHz OSC=898.75MHz VHF-L fd=90MHz 1% (see7) Cross Modulation CM 3, 5 VHF-H fd=465MHz UHF UHF rd fd=471MHz fd=855MHz VHF-L fd=90MHz 3 Inter Modulation (MO) (see8) IM3-MO 3, 5 VHF-H fd=465MHz UHF UHF fd=471MHz fd=855MHz VHF-L OSC=133.75MHz Phase (see9) freq-step=62.5kHz CP=Hi mode Noise (1kHz offset) PN1k 3 VHF-L OSC=238.75MHz VHF-H OSC=244.75MHz VHF-H OSC=508.75MHz UHF UHF OSC=514.75MHz OSC=898.75MHz VHF-L OSC=133.75MHz Phase Noise (10kHz offset) (see10) freq-step=62.5kHz CP=Hi mode PN10k 3 VHF-L OSC=238.75MHz VHF-H OSC=244.75MHz VHF-H OSC=508.75MHz UHF UHF Gain Control Amplifier Block (Pin47 = Open) ⎯ ⎯ Noise Figure (GCA) Nfgca 3, 6 ⎯ ⎯ ⎯ ⎯ 3 rd OSC=514.75MHz OSC=898.75MHz GR=0dB, DSB GR=10dB, DSB GR=20dB, DSB GR=30dB, DSB GR=40dB, DSB f1=43.75MHz, f2=44.75MHz VGCA=3V(MAX Gain) V-out=0.5Vpp / tone f1=43.75MHz, f2=44.75MHz Inter Modulation ( G C A ) IM3-GCA 3, 7 ⎯ VGCA=1.25V(Gain=10dB) V-out=0.5Vpp / tone 42 50 ⎯ dB PLL Block RF Input Maximum Level without Lock out RF-in 3 2 2 2 ⎯ ⎯ ⎯ ⎯ Pin19,20,22,23 4MHz signal input 4MHz signal input It is necessary D/U>10dB. ⎯ 300 ⎯ ⎯ ⎯ ⎯ ⎯ 4 120 dBuV ⎯ ⎯ mVp-p MHz 1000 mVp-p Crystal External Input Minimum Level Xoextl-l Crystal External Input Maximum Level Xoextl-h Crystal External Input Frequency Xoextf note5: IF output frequency=43.75MHz、note6: IF output load=75Ω、note7: VGCA=voltage value applied to Pin3 2005/05/23 11 TA1375FG I²C Bus Line Characteristic CHARACTERISTICS SCL Clock Frequency Bus Free Time between a STOP and a Start Condition Hold Time (Repeated) START Condition Low Period of the SCL Clock High Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Rise Time of both SDA and SCL Signal Fall Time of both SDA and SCL Signals Set up Time for STOP Condition SYMBOL fscl tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tsU;STO − TEST CONDITION MIN. 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 TYP. MAX. 400 0.9 300 300 UNIT kHz us us us us us us ns ns ns us SDA tBUF tLOW tR tF tHD; STA SCL P S tHD; STA tHD; DAT tHIGH tSU; DAT tSU; STA Sr tSU; STO P Figure.1 I²C-bus data timing chart (Rising edge timing) Timing charts may be simplified for explanatory purposes. 2005/05/23 12 TA1375FG Test Circuit Icc (total) 5V A A 240Ω 0.1uF Icc3 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 36 Icc4 0.1uF 35 34 33 32 31 30 29 28 27 26 25 24 2.2nF A N.C. 37 38 39 40 41 42 0.01uF Programmable Divider Charege Pump Phase Comparator GCA control Lock Detector Band Switch Power on Reset 23 22 21 20 19 18 17 16 Band Driver 2.2nF 2.2nF 2.2nF Icc5 0.1uF A 43 0.01uF Icc6 N.C. NF 0.1uF 44 45 A 0.1uF 46 47 Reference Divider 15 14 0.1uF N.C. 48 1 N.C. I2C bus Interface 13 8 0.1uF IBD A 2 N.C. 100Ω 100Ω 3 4 5 6 7 9 10 22pF 11 *4MHz 12 0.1uF 56pF V Vsat 100pF GCA cont SDA SCL ADR A Icc1 A Icc2 Figure.2 Test Circuit 1 note8: Components in the test circuits are only used to obtain and confirm the device characteristics. These components and circuits do not warrant to prevent the application equipment from malfunction or failure. 10 SG(50Ω) 4MHz 0.1uF 11 51Ω Figure.3 Test Circuit 2 (Crystal External Input ) 2005/05/23 13 TA1375FG 33kΩ 10kΩ 33V 10kΩ 10kΩ 2.2nF 10kΩ 10kΩ 2.2nF 10kΩ 10kΩ 22pF 470Ω L4 2.5pF L2 27Ω 1pF 1pF 470Ω 0.1uF 22pF 1SV283 56p 0.5pF L3 1SV283 68pF 1SV283 2pF 8pF 100pF 2.2nF L1 100pF 2pF 5pF 3pF 5pF 36 37 38 39 0.1uF 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 2.2nF 2.2nF 620Ω 2.2nF 2.2nF 0.1uF 2pF UHF RF input IF output 2.2nF 40 41 42 Programmable Divider Charege Pump Phase Comparator GCA control Lock Detector Band Switch Power on Reset VHF RF input 19 100pF IF input (*1) Balun trans 5V 0.01uF 51Ω 43 (*2) 44 18 17 16 3.3nF 0.01uF 0.1uF 27nF 0.1uF 46 0.1uF Reference Divider Band Driver 15 14 620Ω 620Ω 620Ω GC SW 47 48 1 0.01uF I2C bus Interface 13 8 9 0.1uF (*1)Balun trans 616DB-1048(TOKO) (*2)Test circuit condition It difers about a test item. 2 0.01uF 3 4 5 6 7 10 22pF 11 *4MHz 12 0.1uF 56pF 100Ω 240Ω 240Ω (*2) FET probe (10MΩ,2pF) GCA cont. SDA ADR SCL 5V IF output Figure.4 Test Circuit 3 note8: Components in the test circuits are only used to obtain and confirm the device characteristics. These components and circuits do not warrant to prevent the application equipment from malfunction or failure. NF meter 0.1uF (*1) Balun trans 100Ω 100pF L1 : 0.4mmd, 2.5mm φ, 5.5T L2 : 0.4mmd, 2.0mm φ, 2.5T L3 : 0.4mmd, 2.5mm φ, 1.5T L4 : TOKO (886BNF-0048AE) *4MHz : X'tal (NDK,AT-51) SG-1 20 DUT 38 Spectrum Analyzer Noise source 20 DUT 23 Vin or Uin 38 75-50Ω transformation 23 SG-2 75-50Ω transformation Figure.5 Test Circuit 4 (MOP Block : NF） Figure.6 Test Circuit 5 (MOP Block : IM3 / CM） 2005/05/23 14 0.1uF 45 10kΩ 5V TA1375FG NF meter balun 0.01uF 0.01uF 43 DUT 0.01uF 44 2 0.01uF 1 balun 51Ω balun:616DB-1008(TOKO) Figure.7 Test Circuit 6 (GCA Block : NF） SG-1 balun 0.01uF 200Ω 43 DUT 44 2 1 FET probe (10MΩ, 2pF) 0.01uF 1.5kΩ 0.01uF 1.5kΩ 12pF 12pF Spectrum Analyzer 0.01uF SG-2 balun:616DB-1008(TOKO) Figure.8 Test Circuit 7 (GCA Block : IM3） 2005/05/23 15 TA1375FG MOP Block Test Conditions (see1) Conversion Gain RF Input level = -30dBmW (untuned) (see2) IF Output Power Level Measure IF output level when It is maximum level. (see3) Conversion Gain Shift The conversion gain shift Is defined as a change In conversion gain when supply voltage varies from Vcc=5V to 4.5V or From Vcc=5V to 5.25V. (see4) Noise Figure (MO) Noise figure meter used. Direct reading. (see5) OSC Frequency Shift (The PLL is not operating) The frequency shift Is defined as a change In oscillator frequency when supply voltage varies from Vcc=5V to 4.5V or From Vcc=5V to 5.25V. (see6) Switch ON Drift (The PLL is not operating) Measure frequency change from 2 seconds after switching on to 3 minutes. (see7) 1% Cross Modulation fd = fp : (fd Input level = -30dBmW) fud = fp ±12MHz, 100kHz AM30% Input two signals, and Increase the fud Input level. Measure the fud Input level when the suppression level reaches 56.5dB. (see8) 3rd Internal Modulation (MO) fd = fp : (fd Input level = -30dBmW) fud = fp ±1MHz : (fud Input level = -30dBmW) Input two signals, measure the suppression level. (see9) Phase Noise (1kHz offset) Measure the phase noise at 1kHz offset. (PLL setting; frequency step = 62.5kHz / charge pump current = High mode) RF Input level = -30dBmW (see10) Phase Noise (10kHz offset) Measure the phase noise at 10kHz offset. (PLL setting; frequency step = 62.5kHz / charge pump current = High mode) RF Input level = -30dBmW 2005/05/23 16 TA1375FG Description of PLL Block Operation - I²C bus control The TA1375FG conforms to the I²C-bus format. The I²C-bus mode enables two-way bus communications with Write Mode, which receives data, and Read Mode, which sends data. Write Mode and Rear Mode are set using the last bit (R/W bit) of the address byte. If the last address bit is set to [0], Write Mode is selected; if it is set to [1], Read Mode is selected. Address can be set using the hardware bits and four programmable address are available. With this setting, multiple frequency synthesizers can be used in the same I²C-bus. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR:pin7).An address is selected according to the set bits. If the correct address bytes are received, the serial data (SDA) line is ‘’Low’’ during acknowledgment; when Write Mode is set, the serial data (SDA) line is ‘’Low’’ during the next acknowledgment if the data byte is programmed. This IC incorporates a built-in power-on reset circuit for which a detection voltage of approximately 1.4 V has been set. When the Vcc is supplied, a delay or stoppage in a power supply voltage close to this detection voltage may cause the power-on reset circuit to malfunction, in which case there is a risk that some data may not be received even after the recommended voltage has been restored. A) Write Mode (Setting Command) When Write Mode is set so that the different types of information may be received, byte1 is used to specify the address data; byte2 and byte3, the frequency data; byte4, function setting data such as the divider ratio setting; and byte 5, the output port data (bandswitch data). Data are latched and transferred at the end of byte 3,byte 4 and byte 5. Byte 2 and byte 3 are latched and transferred is done with a two bytes set (byte 2 + byte 3). Once a correct address is received and acknowledged, the data type is determined by whether the first bit of the next byte is set to [0] or [1]. [0] indicates frequency data, while [1] indicates function setting or output data. Until the I²C-bus STOP CONDITION is detected, the additional data can be input without transmitting the address data again. (For example: Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid. [[ BYTE 1 ]] Hardware bit setting of byte1 is possible using the address data. The hardware bit is set with the voltage applied to the address-setting pin (ADR:pin7). [[ BYTE 2 , BYTE 3 ]] Byte 2 , byte 3 are stored in the 15-bit shift register with counter data for the frequency setting, and control the 15-bit programmable counter ratio. The program frequency can be calculated in the following formula : fosc = fr×N fosc fr N : Program frequency : Phase comparator reference frequency (Step frequency) : Counter total divider ratio fr is calculated using the crystal oscillator and the reference frequency divider ratio set in byte 4 (control byte). (fr = crystal oscillator frequency / reference divider ratio) The reference frequency divider ratio can be set to 1/64 , 1/80, 1/24 and 1/28. When using a 4MHz crystal oscillator, fr=62.5kHz , 50.0kHz , 166.67kHz and 142.86kHz. The step frequency are 62.5kHz , 50.0kHz , 166.67kHz and 142.86kHz. [[ BYTE 4 ]] Byte4 is a control byte used to set the different function. Bit 2 (CP) and controls the output current of the charge-pump circuit. When bit 2 is set to [0] : the output current is set to +145uA ; when it is set to [1], it is +210uA. Bit 3 (T2), bit 4 (T1) and bit 5 (T0) are used to set the phase comparator reference signal output and counter divider output in test mode. (For details of test mode, see the test mode setting table.) Bit 6 (Rsa) and bit 7 (Rsb) are used to set the crystal reference frequency divider ratio.(For details of the crystal reference frequency divider ratio, see the table for crystal reference frequency divider ratios.) Bit 8 (OS) is used to set the charge-pump driver amplifier output setting. When bit 8 is set to [0] the output is ON (the normal setting used); when it is set to [1] the output is OFF (charge pump is sink mode). 2005/05/23 17 TA1375FG [[ BYTE 5 ]] Byte 5 is used to set the test mode and control the output ports (VHF-L, VHF-H, UHF and FMT). When an output port is set to [0], it is OFF; when it is set to [1], it is ON. As setting the band switch data, It can be control change of VHF or UHF, band switch driver. No. Band SW Data (setting data) Mixer Oscillator Band Drive Port B4 B3 B2 B1 VHF UHF VL VH U VL VH U FMT 1 0 0 0 0 × × × × × × × × × 2 0 0 0 1 ○ × ○ × × ○ × × × 3 0 0 1 0 ○ × × ○ × × ○ × × 4 0 1 0 0 × ○ × × ○ × × ○ × 5 1 0 0 0 × ○ × × ○ × × ○ × 6 0 1 0 1 ○ × ○ × × ○ × × ○ 7 1 0 0 1 ○ × ○ × × ○ × × ○ ○: Operation ×: Not operation When It Is setting the band sw data excepts from No.1 to No.7, this Is not operating mixer, oscillator and band switch driver. Please give the following currents to band switch driver respectively as the maximum value. If the band switch driver operates 2-port ‘ON’(when setting data Is No.6 and No.7) , total band driver curent Is below 25mA. VHF-L band switch driver (pin14) output current; 20mA(maximum) VHF-H band switch driver (pin15) output current; 20mA(maximum) UHF band switch driver (pin21) output current; 15mA(maximum) VHF-L and FMT band switch driver (pin13 and 14) output total current; 25mA(maximum) B) Read Mode (Status Request) When Read Mode is set, power-on reset operation status and phase comparator lock detector output status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply of Vcc1 stops, this bit is set to [1]. The conditions for reset to [0] are that voltage supplied to Vcc1 is 3V or higher, that transmission is requested in Read Mode, and that the status is output. (When Vcc1 is turned on, bit1 is also set to [1].) Bit 2 (FL) indicates the phase comparator lock status. When this is locked, [1] is output; when it is unlocked, [0] is output. 2005/05/23 18 TA1375FG DATA FORMAT A) WRITE MODE 1 2 3 4 5 Address Byte Divider Byte 1 Divider Byte 2 Control Byte Band SW Byte MSB 1 0 N7 1 × 1 N14 N6 CP × 0 N13 N5 T2 × 0 N12 N4 T1 × 0 N11 N3 T0 B4 LSB MA1 MA0 R/W=0 ACK N10 N9 N8 ACK N2 N1 N0 ACK(L) Rsa Rsb OS ACK(L) B3 B2 B1 ACK(L) × :DON’T CARE ACK :Acknowledged (L) :Latch and transfer timing B) READ MODE 1 2 Address Byte Status Byte MSB 1 POR 1 FL 0 1 0 1 0 1 LSB MA1 MA0 R/W=1 1 1 1 ACK :Acknowledged ACK - DATA SPECIFICATIONS ●MA1,MA0 : programmable hardware address bits MA1 0 0 1 1 MA0 0 1 0 1 ADDRESS PIN APPLIED VOLTAGE 0 to 0.1Vcc1 OPEN or 0.2Vcc1 to 0.3Vcc1 0.4Vcc1 to 0.6Vcc1 0.9Vcc1 to Vcc1 ●N14 – N0 : programmable counter data ● CP : charge pump output current setting [0] : + 145uA(typ.) [1] : + 210uA(typ) ●T2,T1,T0 : test mode setting bits CHARACTERISTIC Normal operation OFF Charge-pump SINK SOURCE Reference signal output 1/2 counter divider output T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 × × 0 1 0 1 NOTE Charge pump is OFF (check output : NF) Only charge pump sink current is ON (check output : NF) Only charge pump source current is ON (check output : NF) Reference signal output (check output : pin21) 1/2 counter output (check output : pin15) note9: Testing of the counter driver output requires the input of programmable counter data. ●Rsa,Rsb : Reference frequency divider ratio select bit. Rsa 0 0 1 1 Rsb 0 1 0 1 DIVIDER RATIO 1/80 1/28 1/24 1/64 STEP FREQUENCY 50.0kHz 142.86kHz 166.67kHz 62.5kHz ●OS : tuning amplifier control bit [0] : tuning amplifier ON (normal operation) [1] : tuning amplifier OFF (charge pump is sink mode) ●POR : power on reset flag [0] : normal operation [1] : reset operation 2005/05/23 19 TA1375FG ●FL : lock detect flag [0] : unlocked [1] : locked ●× : don’t care -EXAMPLE OF BUS DATA TRANSMITTERS : Start ADR : Address Byte DIV1 : Divider Byte 1 (frequency data) DIV2 : Divider Byte 2 (frequency data) CONT : Control Byte BAND : Band SW Byte A : Acknowledge P : Stop [1] Transmitter - 1 S ADR [2] Transmitter - 2 S ADR A DIV1 A DIV2 A CONT A BAND A P A CONT A BAND A DIV1 A DIV2 A P [3] Transmitter – 3 (This can be applies if control data and bandswitch data have already been programmed.) S ADR A DIV1 A DIV2 A P [4] Transmitter – 4 (This can be applies if frequency data have already been programmed.) S ADR A CONT A BAND A P [5] Transmitter – 5 (This can be applies if frequency data and bandswitch data have already been programmed.) S ADR A CONT A P Until the I²C-bus STOP Condition is detected, it is possible to input the additional data without transmitting the address data again. (For example: Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid. 2005/05/23 20 TA1375FG OUTLINE DRAWING Weight: 0.17g (typ.) 2005/05/23 21 TA1375FG HANDLING PRECAUTIONS 1. The device should not be inserted into or removed from the test apparatus while the voltage is being applied; otherwise breakdown or deterioration in performance of the device may result. Also, avoid any abrupt increasing or decreasing of the voltage. Overshoot or chattering of the power supply may cause the IC to be degraded. To avoid this problem, equip the power supply line with filters. 2. The peripheral circuits described in this datasheet are given only as system examples for evaluating the performance of the device. Toshiba neither recommend the configuration or related values of the peripheral circuits nor intend to manufacture such application systems in large quantities. Please note that the high-frequency characteristics of the device may vary depending on the external components, mounting method and other factors relating to the application design. Therefore it is the responsibility of users incorporating the device into their designs to evaluate the characteristics of application circuits. Toshiba only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customer’s application design. 3. In order better to understand the quality and reliability of Toshiba semiconductor products and to incorporate them into designs in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (Integrated Circuits) published by Toshiba Semiconductor Company. The handbook can also be viewed online at ‘’ http://www.semicon.toshiba.co.jp/ ’’ 2005/05/23 22 TA1375FG Solderability Regarding solderability, the following conditions have been confirmed. (1) Use of Sn-63Pb solder bath ・Solder bath temperature = 230°C ・Dipping time = 5 seconds ・The number Number of times = once ・Use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder bath ・Solder bath temperature = 245°C ・Dipping time = 5 seconds ・Number of times = once ・Use of R-type flux 2005/05/23 23 TA1375FG RESTRICTIONS ON PRODUCT USE The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 2005/05/23 24