TA2170FTG

TA2170FTG TOSHIBA Bipolar Linear IC Silicon Monolithic TA2170FTG Low Current Consumption Headphone Amplifier (Built-in input selector) The TA2170FTG is a stereo headphone amplifier built in the selector switch of 3 inputs. The mute switch is built in each 3 input, and an output can choose 1 output or a mixer output. Features • Low current consumption VCC = 3 V, f = 1 kHz, RL = 32 Ω, typ. • No signal mode ICCQ = 0.9 mA (1 input mode) ICCQ = 1.0 mA (2 inputs mode) ICCQ = 1.1 mA (3 inputs mode) • 0.1 mW × 2 ch ICC = 2.2 mA (1 input mode) ICC = 2.3 mA (2 inputs mode) ICC = 2.4 mA (3 inputs mode) • 0.5 mW × 2 ch ICC = 4.1 mA (1 input mode) ICC = 4.2 mA (2 inputs mode) ICC = 4.3 mA (3 inputs mode) • • • • • • • GV = −0.3dB (1 input mode, typ.) Built-in signal level adjustment circuit, so that a 1 output or a mixer output doesn’t change a feeling of volume either. Built-in power switch Built-in all mute switch Built-in mute switch at each buffer amplifier. Built-in one side mute switch at buffer amplifier 1. Operating supply voltage range (Ta = 25°C): VCC1 (opr) = 1.8 to 4.5 V VCC2 (opr) = 0.9 to 4.5 V Weight: 0.03 g (typ.) Marking: 2170 1 2006-04-19 TA2170FTG Block Diagram ON ON ON ON ON ON VCC1 ALL PW SW MUTE 18 17 MUTE3 MUTE2 MUTE1A MUTE1 16 15 14 13 PW SW MUTE SW 19 RF IN 12 EQA ALL MUTE PW A 20 GND 11 OUTA 10 PW GND 9 OUTB 8 EQB 7 VCC2 OUTA RL VCC1 21 BIAS VCC1 22 BIAS OUT 23 BIAS IN BUF1A PW B OUTB RL MUTE1-A MUTE1 BUF1B BUF2A MUTE2 BUF2B BUF3A MUTE3 BUF3B 24 OUT ADJ 1 2 3 4 5 6 VCC2 IN1A IN1B IN2A IN2B IN3A IN3B IN1 IN2 IN3 2 2006-04-19 TA2170FTG Pin Descriptions Pin Voltage: Typical Pin voltage for test circuit when no input signal is applied, VCC1 = VCC2 = 3 V, Ta = 25°C Pin No. and Name 1 2 3 4 5 6 7 IN1A Inputs to buffer amplifier 1 IN1B IN2A Inputs to buffer amplifier 2 IN2B IN3A Inputs to buffer amplifier 3 IN3B VCC2 VCC for power drive stage 7 9 OUTB Outputs from power amplifier 11 OUTA 10 10 PW GND GND for power drive stage 0 11 OUT 1.15 VCC2 3 1 10 kΩ 10 kΩ 1.15 1.15 Function Internal Circuit Pin Voltage (V) BIAS OUT 1.15 8 EQB 11 Low-pass Compensation pins 1.15 12 EQA 5 kΩ 15 kΩ 43 kΩ 12 BIAS OUT 3 2006-04-19 TA2170FTG Pin No. and Name Function Mute switch of buffer amplifier 1 Mute ON : L level Mute OFF: H level Refer to application note 4. Mute switch of buffer amplifier 1A Mute ON : L level Mute OFF: H level this switch is used when it turn on A channel mutes of a buffer amplifier 1. Refer to application note 4. Mute switch of buffer amplifier 2 Mute ON : L level Mute OFF: H level Refer to application note 4. Mute switch of buffer amplifier 3 Mute ON : L level Mute OFF: H level Refer to application note 4. Internal Circuit Pin Voltage (V) ⎯ 13 MUTE1 14 MUTE1A ⎯ 10 kΩ 13 15 MUTE2 ⎯ 16 MUTE3 ⎯ 17 ALL MUTE All mute switch Mute ON : L level Mute OFF: H level Refer to application note 4. VCC 10 kΩ 20 kΩ 17 ⎯ VCC1 100 kΩ 18 PW SW 10 kΩ Power switch IC ON : H level IC OFF: L level Refer to application note 4. 18 3 19 RF IN Ripple filter input VCC2 39 kΩ 2.7 21 VCC1 VCC for everything other than power drive stage Bias circuit output 3 47 kΩ 15 kΩ 22 BIAS OUT 19 1.15 23 BIAS IN Bias circuit input 24 DC output voltage adjustment Either connect this pin or leave it open depending on the level of VCC2. If the power supply of a 1.5 V system is applied to VCC2, connect this pin to BIAS IN (pin14) If the power supply of a 3 V system is applied to VCC2, leave this pin open. ⎯ 21 VCC1 1.15 23 62 kΩ 22 1.85 24 OUT ADJ 20 GND ⎯ 0 4 2006-04-19 TA2170FTG Application Notes 1. Mute switch and voltage gain This IC is designed so that a volume feeling may not change with a single output and many outputs. When the input signal to buffer amplifier is same and a linear domain, the relation between mute switches and voltage gain are as follows. Test condition: VCC = 3 V, f = 1 kHz, Vin = −20dBV, theoretical value (1) 1 input mode MUTE SW MUTE1 MUTE1A MUTE2 MUTE3 Attenuation to an input signal (dB) BUF1 BUF2 BUF3 Ach Bch Ach Bch Ach Bch ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Total gain (dB) Ach Bch Input signal is applied to BUF 1. OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON OFF ON OFF ON OFF ON OFF ON ON OFF OFF ON ON OFF OFF 0 −6 −6 −9.5 ⎯ ⎯ ⎯ ⎯ 0 −6 −6 −9.5 0 −6 −6 −9.5 0 −6 −6 −9.5 ⎯ ⎯ ⎯ ⎯ 0 −6 −6 −9.5 0 −6 −6 −9.5 Input signal is applied to BUF 2 ON ON OFF OFF OFF OFF ON/OFF ON/OFF OFF ON OFF ON OFF OFF OFF OFF OFF OFF ON OFF ON ON OFF OFF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 −6 −6 0 −9.5 −6 0 −6 −6 −6 −9.5 −9.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 −6 −6 0 −9.5 −6 0 −6 −6 −6 −9.5 −9.5 Input signal is applied to BUF 3. ON ON OFF OFF OFF OFF ON/OFF ON/OFF OFF ON OFF ON ON OFF ON ON OFF OFF OFF OFF OFF OFF OFF OFF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 −6 −6 0 −9.5 −6 0 −6 −6 −6 −9.5 −9.5 0 −6 −6 0 −9.5 −6 0 −6 −6 −6 −9.5 −9.5 5 2006-04-19 TA2170FTG (2) 2 inputs mode MUTE SW MUTE1 MUTE1A MUTE2 MUTE3 Attenuation to an input signal (dB) BUF1 BUF2 BUF3 Ach Bch Ach Bch Ach Bch −6 −9.5 ⎯ ⎯ −6 −9.5 ⎯ −6 −6 −9.5 ⎯ −9.5 −6 −9.5 ⎯ −6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Total gain (dB) Ach Bch Input signal is applied to BUF 1 and BUF 2. OFF OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF ON OFF ON OFF 0 −3.5 ⎯ −3.5 0 −3.5 ⎯ 0 Input signal is applied to BUF 1 and BUF 3. OFF OFF OFF OFF OFF OFF ON ON ON OFF ON OFF OFF OFF OFF OFF −6 −9.5 ⎯ ⎯ −6 −9.5 −6 −9.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −6 −9.5 −6 −9.5 −6 −9.5 −6 −9.5 0 −3.5 −6 −9.5 0 −3.5 0 −3.5 Input signal is applied to BUF 2 and BUF 3. ON OFF OFF ON/OFF ON OFF OFF OFF OFF OFF OFF OFF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −6 −6 −9.5 −6 −9.5 −9.5 −6 −6 −9.5 −6 −9.5 −9.5 0 0 −3.5 0 −3.5 −3.5 (3) 3 inputs mode MUTE SW Attenuation to an input signal (dB) BUF1 BUF2 BUF3 Ach Bch Ach Bch Ach Bch −9.5 ⎯ −9.5 −9.5 −9.5 −9.5 −9.5 −9.5 −9.5 −9.5 −9.5 −9.5 Total gain (dB) Ach Bch 0 −3.5 0 0 MUTE1 OFF OFF MUTE1A OFF ON MUTE2 OFF OFF MUTE3 OFF OFF 2. Low-cut compensation The low-frequency range can be decreased using an output-coupling capacitor and a load (fc = 50 Hz at C = 100 µF, R = 32 Ω). However, since the capacitor is connected between the IC’s output pin (pin 9/11) and EQ pin (pin 8/12), the low-frequency gain of the power amplifier increases, enabling low-cut compensation to be performed. For the response of capacitors of different values, please refer to Figure 1. RES – f 4.0 0.1 µF 2.0 0.15 µF 0.0 Response (dB) −2.0 −4.0 0.22 µF −6.0 No compensation −8.0 −10.0 −12.0 10 Coupling C = 100 µF RL = 32 Ω 50 100 500 1000 5000 Frequency f (Hz) Figure 1 Capacitor response 6 2006-04-19 TA2170FTG 3. Adjustment of DC output voltage Please perform the OUT ADJ pin (pin 24) as follows by the power supply of VCC1 and VCC2. • If a boost voltage is applied to VCC1, VCC2 is connected to a battery and the difference between VCC1 and VCC2 is greater than or equal to 0.7 V, short pins 23 and 24 together. In this case the DC output voltage will be VCC2 . 2 • If the difference between VCC1 and VCC2 is less than 0.7 V, or if VCC1 and VCC2 are connected to the same power supply, leave pin 24 open. In these cases the DC output voltage will be VCC2 − 0.7 V . 2 4. Switch (1) Timing chart Refer to Fig. 2 for the IC timing chart. ON PW SW OFF OFF ALL MUTE ON OFF MUTE ON OUT 200 ms 100 ms Figure 2 Timing chart (2) PW SW The device is ON when this pin is set to High. To prevent the IC being turned ON by external noise, it is necessary to connect an external pull-down resistor to the PW SW pin. The pin is highly sensitive. Mute smoothing The resistor is connected to a mute pin less than 100 kΩ When larger than this, the switch circuit doesn’t operate normally. (3) 7 2006-04-19 TA2170FTG (4) 5 4.5 V Switch sensitivity (Ta = 25°C) 5 4.5 V (V) 4 (V) Applied voltage V13~17 H 4 Applied voltage V18 3 3 H 2 2 1.5 V 1 0.3 V 0 0 1 2 1 0.8 V 0.1 V L 1 2 3 4 5 L 3 4 5 0 0 Supply voltage VCC1 (V) Supply voltage VCC1 (V) PW SW H level L level IC ON IC OFF H level L level MUTE Mute OFF Mute ON Figure 3 Switch sensitivity 5. Capacitor The following capacitors must have excellent temperature and frequency characteristics. Absolute Maximum Ratings (Ta = 25°C) Characteristic Supply voltage 1 Supply voltage 2 Output current Power dissipation Operating temperature Storage temperature Symbol VCC1 VCC2 Io (peak) PD (Note) Topr Tstg Rating 4.5 4.5 100 350 −25~75 −55~150 mA mW °C °C Unit V Note: Derated by 2.8 mW/°C above Ta = 25°C 8 2006-04-19 TA2170FTG Electrical Characteristics (Unless otherwise specified, VCC1 = VCC2 = 3 V, Rg = 600 Ω, RL = 32 Ω, f = 1 kHz, Ta = 25°C, SW1~SW5: a, SW6~SW8: a) Symbol ICCQ1 Test condition IC OFF mode SW1~5: b 1 input on mode BUF1: ON (SW5: a, SW3/4: b) BUF2: ON (SW4: a, SW3/5: b) BUF3: ON (SW3: a, SW4/5: b) 2 input on mode BUF1/2: ON (SW4/5: a, SW3: b) BUF1/3: ON (SW3/5: a, SW4: b) BUF2/3: ON (SW3/4: a, SW5: b) 3 input on mode 1 input on mode VCC1 = 2.4 V, VCC2 = 1.2 V BUF1: ON (SW5: a, SW3/4: b) BUF2: ON (SW4: a, SW3/5: b) BUF3: ON (SW3: a, SW4/5: b) 1 input on mode 0.1 mW/32 Ω × 2 ch BUF1: ON (SW5: a, SW3/4: b) BUF2: ON (SW4: a, SW3/5: b) BUF3: ON (SW3: a, SW4/5: b) 2 input on mode 0.1 mW/32 Ω × 2 ch BUF1/2: ON (SW4/5: a, SW3: b) BUF1/3: ON (SW3/5: a, SW4: b) BUF2/3: ON (SW3/4: a, SW5: b) 3 input on mode 0.1 mW/32 Ω × 2 ch 1 input on mode Vo = −20dBV BUF1: ON (SW5: a, SW3/4: b) BUF2: ON (SW4: a, SW3/5: b) BUF3: ON (SW3: a, SW4/5: b) 2 input on mode Vo = −20dBV BUF1/2: ON (SW4/5: a, SW3: b) BUF1/3: ON (SW3/5: a, SW4: b) BUF2/3: ON (SW3/4: a, SW5: b) 3 input on mode Vo = −20dBV Vo = −20dBV THD = 10% VCC1 = 2.4 V, VCC2 = 1.2 V THD = 10% Po = 1 mW Rg = 600 Ω, Filter: IHF-A, SW6~8: b Vo = −20dBV fr = 100 Hz, Vr = −20dBV ALL MUTE SW: ON, Vo = −20dBV MUTE SW: ON, Vo = −20dBV VCC1 = 1.8 V, VCC2 = 0.9 V VCC1 = 1.8 V, VCC2 = 0.9 V VCC1 = 1.8 V, VCC2 = 0.9 V VCC1 = 1.8 V, VCC2 = 0.9 V Min. ⎯ ⎯ Typ. ⎯ Max. 5 Characteristic Unit µA ICCQ2 0.9 1.6 Quiescent supply current ICCQ3 ⎯ ⎯ 1.0 1.8 mA ICCQ4 1.1 2.0 ICCQ5 ⎯ 0.9 1.6 ICC1 ⎯ 2.2 ⎯ Power supply current during drive ICC2 mA ⎯ ⎯ −1.8 2.3 ⎯ ⎯ ICC3 2.4 −0.3 GV1 1.2 Voltage gain GV2 dB −1.0 −0.8 −1.5 15 3 ⎯ ⎯ −53 −70 −75 −47 5 0 5 0 0.5 2.0 GV3 Channel balance CB Po1 Output power Po2 Total harmonic distortion Output noise voltage Cross talk Ripple rejection ratio Muting attenuation PW SW ON current PW SW OFF voltage MUTE SW OFF current MUTE SW ON voltage THD Vno CT RR ATT1 ATT2 I19 V19 I20-24 V20-24 0.7 0 20 6 0.1 −100 −60 −80 −90 −62 ⎯ ⎯ ⎯ ⎯ 2.2 1.5 ⎯ ⎯ 0.3 −96 ⎯ ⎯ ⎯ ⎯ ⎯ 0.3 ⎯ 0.1 mW dB % dBV dB dB dB µA V µA V 9 2006-04-19 TA2170FTG Test Circuit (a) 100 kΩ (b) SW2 0.1 µF (a) 100 kΩ (b) SW3 0.1 µF (a) 100 kΩ (b) SW4 0.1 µF (a) 100 kΩ (b) SW5b 0.1 µF 100 kΩ SW5a 0.1 µF VCC1 SW1 (a) (b) 18 PW SW 19 RF IN 17 16 ALL MUTE MUTE3 15 MUTE2 14 MUTE1A 13 MUTE1 EQA 12 0.22 µF 0.22 µF 100 µF OUTA 4.7 Ω RL 4.7 µF 20 GND OUTA 11 22 µF VCC1 21 VCC1 TA2170FTG PW GND 10 100 µF 0.22 µF 10 µF 0.22 µF 22 BIAS OUT OUTB 9 OUTB 4.7 Ω RL 4.7 µF 23 BIAS IN EQB 8 IN1A 1 1 µF IN1B 2 1 µF IN2A 3 1 µF IN2B 4 1 µF IN3A 5 1 µF IN3B 6 1 µF SW8a SW8b SW7a SW7b SW6a SW6b (a) (b) (a) (b) (a) (b) (a) (b) (a) (b) (a) (b) Rg = 600 Ω Rg = 600 Ω Rg = 600 Ω Rg = 600 Ω Rg = 600 Ω Rg = 600 Ω 600 Ω 600 Ω 600 Ω 600 Ω 600 Ω 600 Ω 22 µF 24 OUT ADJ VCC2 7 VCC2 10 2006-04-19 TA2170FTG Package Dimensions Note: The die length by the projective technique from a package top face prescribes the part of a package side-face part, And it is made into 0.15 maximum. The flux of solder cream should use RMA type or RA type. Weight: 0.03 g (typ.) 11 2006-04-19 TA2170FTG RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 021023_D 060116EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux 12 2006-04-19