TB2173FTG

TB2173FTG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB2173FTG 2-Source Stereo Headphone Amplifier The TB2173FTG is a stereo headphone amplifier IC that can accept two sources, developed for portable audio systems. It is particularly ideal for digital portable audio systems having built-in tuners. Features • • • • • • Accepts headphone amplifier inputs from two sources Selectable headphone amplifier output: Output coupling or OCL Incorporates beep circuit Incorporates power switch (controlled using port or command) Supports power muting (controlled using port or command) Features with single source only (tuner mode): • • • • Electronic volume Provides logic reset feature Low-frequency boost (with AGC) Weight: 0.05 g (typ.) Product indication: B2173G Two port expansion circuits Operating supply voltage range: Ta = 25°C VDD (opr) = 1.8 to 4.5 V VCC1 (opr) = 1.8 to 4.5 V VCC2 (opr) = 0.9 to 4.5 V Note: Use the device with VCC1 greater than or equal to VCC2. • • Handle the product with great care because its surge resistance is low. Ensure that the product is mounted correctly. Otherwise, the product or connected equipment may get damaged or degrade. 1 2006-04-19 TB2173FTG Block Diagram (OCL Type) Tuner IN VDD C-Cup OCL VOL PRE PRE VOL PRE C-SW GND IN2A OUTA INA INB OUTB IN2B IN1A IN1B GND 33 32 31 30 29 28 27 26 25 24 23 ON 34 MUTE SW ON 35 PW SW 36 RESET 37 CK 38 DATA 39 STB 40 VDD BIAS OUT 41 PRE NFA 42 PRE NFB 43 P1 44 P2 MODE SW VOL VOL ATT ATT 22 MODE TC 21 MUTE TC BEEP 20 BEEP IN 19 VCC1 18 BIAS IN 17 OUT ADJ 16 RF 15 BIAS OUT 14 LPF1 PORT 13 BST NF 12 LPF2 BIAS OUT Music IN VDD MCU VOL, SW, PORT CONT BIAS OUT BST AGC 9 10 11 1 2 3 4 5 6 7 8 BEEP OUTA OUTC PW OUTB BEEP VCC2 BST AGC AGC BST OUTA GND OUTB TC DET IN OUT RL RL Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purpose. BIAS 2 2006-04-19 TB2173FTG Pin Functions Pin voltages: Typical quiescent pin voltages in test circuit, VDD = VCC1 = 2.1 V, VCC2 = 1.2 V, Ta = 25°C The equivalent circuit diagrams are intended as an aid for describing circuits; they may be shown in abbreviated or simplified format. Pin No. and Name BEEP OUTA Beep signal output 6 BEEP OUTB 1 20 6 Function Internal Equivalent Circuit Pin Voltage (V) 1 VCC1 ⎯ 20 BEEP IN Beep signal input ⎯ VCC2 2 OUTA PWA 7 2 Power amplifier output 0.6 4 5 OUTB 15 kΩ 10 kΩ 10 kΩ BIAS OUT BST2 4 PW GND Power drive stage ground 11 0 10 kΩ 30 kΩ 7 VCC2 Power drive stage VCC 10 kΩ 10 kΩ 15 kΩ PWB 5 11 BST OUT Boost amplifier output 0.6 BIAS OUT BIAS OUT 1.2 3 2006-04-19 TB2173FTG Pin No. and Name Function Internal Equivalent Circuit Pin Voltage (V) 3 OUTC Center amplifier output VCC2 33 0.6 BIAS OUT 33 C-SW Output application select switch VDD : OCL GND : Output coupling 3 0.6 PW GND VCC1 8 8 BST TC Pin for reducing boost ON/OFF pop noise to BST SW to BST Amp. ⎯ VCC1 10 kΩ 9 AGC DET Boost AGC detection 9 ⎯ 10 AGC IN Boost AGC input The level of the input signal to the BST amplifier is varied according to the input level at this pin. Input impedance: 37 kΩ (typ.) 5 kΩ BIAS OUT 0.6 10 32 kΩ 4 2006-04-19 TB2173FTG Pin No. and Name Function Internal Equivalent Circuit Pin Voltage (V) BIAS OUT Boost filter pin 2 Cutoff frequency setting 2 for low-frequency boost 20 kΩ 12 LPF2 0.6 12 kΩ 13 BST NF Boost amplifier NF 2 kΩ 60 kΩ 12 0.6 13 14 LPF1 Boost filter pin 1 Cutoff frequency setting 1 for low-frequency boost 29 50 kΩ BIAS OUT BIAS OUT 0.6 20 kΩ 10 pF 20 kΩ to PWA 16 kΩ 500 Ω 28 PRE INB 41 29 PRE INA 5 kΩ Tuner mode: Power amplifier input 0.6 50 kΩ BIAS OUT 20 kΩ to PWB 20 kΩ 10 pF 16 kΩ 28 500 Ω 41 PRE NFA Tuner mode: Power amplifier NF 42 5 kΩ 0.6 BIAS OUT 14 42 PRE NFB 5 2006-04-19 TB2173FTG Pin No. and Name BIAS OUT Function Internal Equivalent Circuit Pin Voltage (V) 0.6 15 Bias circuit output VCC2 16 RF Ripple filter pin 16 30 kΩ 1.1 17 OUT ADJ Output DC voltage adjustment The output bias voltage is set to an optimum value according to the voltage applied to VCC2. Bias circuit input 94 kΩ VCC1 19 0.6 17 19 VCC1 VCC other 2 than VDD and VCC2 124 kΩ 18 BIAS IN 18 15 0.6 2.1 21 MUTE TC Mute smoothing VCC1 50 kΩ 24 kΩ ⎯ 34 MUTE SW Power mute switch Mute switch for power amplifier. When controlling MUTE SW using a port, specify "0" in a command. In that case, the IC operates as follows according to the port state: High: Mute ON Low: Mute OFF When controlling MUTE SW using a command, drive the port low. 21 34 ⎯ to BUS VCC1 22 Pin for reducing mode change 22 MODE TC pop noise to BUS 100 kΩ ⎯ 23 PRE GND Ground for circuits other than logic and power drive stage ⎯ 0 6 2006-04-19 TB2173FTG Pin No. and Name Function Internal Equivalent Circuit Pin Voltage (V) VCC1 24 IN1B Input pin 1 Input pin with GV = 8dB 10 kΩ 25 to ADD OUT 0.6 20 kΩ 25 IN1A BIAS OUT BIAS OUT 26 IN2B 31 IN2A Input pin 2 The input signal is supplied to the power amplifier through the electronic volume circuit and preamplifier. 1 kΩ 31 30 0 27 VOL OUTB Volume output IN2 electronic volume output 20 kΩ 0 30 VOL OUTA Logic ground Power switch IC ON/OFF switch. The switch does not, however, control the electronic volume circuit. When controlling PW SW using a port, specify "1" in a command. In that case, the IC operates as follows according to the port state: High: IC ON Low: IC OFF When controlling PW SW using a command, drive the port high. ⎯ 0 32 GND 2 kΩ 35 ⎯ to BUS 35 PW SW 36 RESET 36 40 VDD Logic power supply 50 kΩ Command reset This pin resets the bus data. High: No reset Low: Reset 40 VDD 2.1 200 Ω 2.1 7 2006-04-19 TB2173FTG Pin No. and Name Function Internal Equivalent Circuit Pin Voltage (V) 37 CK Clock input VDD ⎯ 38 DATA Data input 37 ⎯ 200 Ω 39 STB Strobe input ⎯ 43 P1 to BUS VDD Port expansion 41 ⎯ 44 P2 8 2006-04-19 TB2173FTG Functional Description Bus Data Timing Charts 1. Serial Data Specification (initial data is not set.) CK DATA1 Ach Bch D1 D2 D3 D4 D5 D6 AD DATA2 MODE BST PW SW MUTE P1 P2 NONE NONE AD STB l/fck twcH twcL ts th tp twl Characteristics Clock frequency High-level pulse width Low-level pulse width Data setup time Data hold time STB setup time STB pulse width Symbol fck twcH twcL ts th tp twl1 Min ⎯ 500 500 100 100 150 0.80 Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 1.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit MHz nSec nSec nSec nSec nSec µSec (1) Ach/Bch control data: 2 bits (Ach, Bch) Bch 0 0 1 1 Operation No volume data set Volume data set for Ach only Volume data set for Bch only Volume data sets for both channels Ach 0 1 0 1 9 2006-04-19 TB2173FTG (2) Volume data: 6 bits (D1 to D6) D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Volume Value 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 −34.3 −34.7 −35.1 −35.5 −36.0 −36.5 −37.0 −37.6 −38.2 −38.9 −39.6 −40.4 −41.5 −42.7 −43.3 −43.9 −44.7 −45.3 −46.1 −46.9 −47.7 −48.7 −49.9 −51.1 −52.5 −54.4 −56.1 −57.8 −60.0 −63.5 −68.9 −90.0 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Volume Value 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 −0.1dB −2.1 −4.0 −5.5 −6.9 −8.2 −9.6 −10.9 −12.3 −13.6 −14.9 −16.3 −17.6 −19.0 −20.3 −22.1 −23.7 −25.1 −26.6 −27.9 −28.5 −29.1 −29.3 −29.8 −30.5 −30.8 −31.3 −31.7 −32.2 −32.8 −33.2 −33.9 (3) Identification data: 1 bit (AD) AD 0 1 Operation Recognized as DATA1 Recognized as DATA2 (4) MODE SW data: 1 bit (MODE) MODE 0 1 Operation Outputs the input signal components for IN2 (tuner mode). Outputs the input signal components for IN1 (music mode). 10 2006-04-19 TB2173FTG (5) BST SW data: 1 bit (BST) BST 0 1 Boost OFF Boost ON Operation (6) PW SW: 1 bit (PW SW) PW SW can be controlled using either a command or port, with the following truth table: Command 0 (OFF) 1 (ON) 0 (OFF) 1 (ON) 0 (IC OFF) 0 (IC OFF) 0 (IC OFF) 1 (IC ON) Operation Port 0 (OFF) 0 (OFF) 1 (ON) 1 (ON) (7) MUTE SW: 1 bit (MUTE) MUTE SW can be controlled using either a command or port, with the following truth table: Command 0 (OFF) 1 (ON) 0 (OFF) 1 (ON) Operation 0 (MUTE OFF) 1 (MUTE ON) 1 (MUTE ON) 1 (MUTE ON) Port 0 (OFF) 0 (OFF) 1 (ON) 1 (ON) (8) Power expansion: 1 bit (P1/P2) P1/P2 0 1 Port Low Port High Operation (9) NONE An invalid bit (10) Strobe data (STB) STB 0 1 No data write Data write Operation (11) Initial command upon command reset DATA1 Initial value DATA2 Initial value Ach 1 MODE 0 Bch 1 BST 0 D1 1 PW SW 0 D2 1 MUTE 1 D3 1 P1 1 D4 1 P2 0 D5 1 Invalid D6 1 Invalid AD 0 AD Bit 9 specifies the address. The initial address selected upon a reset is DATA1. Command data is maintained over a power cycle. 11 2006-04-19 TB2173FTG 2. IC Settings According to Supply Voltage (1) Connecting power supplies The TB2173FTG supports an end product that uses either one or two batteries. Connect the power supply pins according to the number of batteries, as follows: Microcontroller power supply Single battery Two batteries VDD, VCC1 VDD Battery power supply VCC2 VCC1, VCC2 Note: Use the device with VCC1 greater than or equal to VCC2. (2) Handling the OUT ADJ pin (pin 17) When using a single battery: Jumper OUT ADJ (pin 17) and BIAS IN (pin 18). When using two batteries: Leave OUT ADJ (pin 17) open. Absolute Maximum Ratings (Ta = 25°C) Characteristics DC supply voltage Symbol VDD VCC Operating supply voltage Power block output current Power dissipation Operating temperature Storage temperature PD VDD VCC IO (Note 1) (Note 2) Topr Tstg 100 350 mW 1200 −25 to 75 −55 to 150 °C °C mA 4.5 V Rating 5.0 Unit V Note 1: IC alone: When the IC is used at 25°C or higher, reduce 2.8 mW per 1°C. Note 2: When mounted on Toshiba standard board: When the IC is used at 25°C or higher, reduce 9.6 mW per 1°C. The absolute maximum ratings of a semiconductor device are a set of specified parameter values which must not be exceeded during operation, even for an instant. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning. The equipment manufacturer should design so that no absolute maximum rating value is exceeded with respect to current, voltage, power dissipation, temperature, etc. Ensuring that the parameter values remain within these specified ranges during device operation will help to ensure that the integrity of the device is not compromised. 12 2006-04-19 TB2173FTG Electrical Characteristics (VDD = VCC1 = 2.1 V, VCC2 = 1.2 V, Rg = 600 Ω, RL = 16 Ω, f = 1 kHz, OCL mode, Ta = 25°C, SW3: b, SW4: a, unless otherwise specified) Music mode Input: IN1, Output: OUT, SW1: a Tuner mode Input: PRE IN, Output: OUT, SW2: a Electronic volume Input: IN2, Output: VOL OUT Characteristics Symbol ICCQ1 ICCQ2 ICCQ3 ICCQ4 Quiescent current ICCQ5 ICCQ6 ICCQ7 ICCQ8 ICCQ9 ICCQ10 Driving current Voltage gain Channel balance Output power Music mode Total harmonics distortion Output noise voltage Interchannel crosstalk Intermode crosstalk Ripple rejection ratio Mute attenuation Voltage gain Channel balance Output power Total harmonics distortion Output noise voltage Tuner mode Interchannel crosstalk Intermode crosstalk Ripple rejection ratio RR4 Mute attenuation ATT2 BST1 Boost BST2 BST3 ICCD1 ICCD2 GV1 CB1 Po1 THD1 Vno1 CT1 CT2 RR1 RR2 ATT1 GV2 CB2 Po2 THD2 Vno2 CT3 CT4 RR3 Test Condition Standby (VDD), SW4: b Standby (VCC1, VCC2) Mute ON: Music mode (VCC1), SW3: a Mute ON: Music mode (VCC2), SW3: a Mute ON: Music mode (VCC1), SW3: a Mute ON: Music mode (VCC2), SW3: a No signal: Music mode (VCC1) No signal: Music mode (VCC2) No signal: Music mode (VCC1) No signal: Music mode (VCC2) 0.1 mW∗2ch/16 Ω (VCC1) 0.1 mW∗2ch/16 Ω (VCC2) Vo = −20dBV Vo = −20dBV THD = 10% Po = 1 mW Rg = 600 Ω, IHF-A, SW1: b Vo = −20dBV Vo = −20dBV, monitor: music fr = 100Hz, Vr = −20dBV, injected to VCC1 fr = 100Hz, Vr = −20dBV, injected to VCC2 Vo = −20dBV, SW3: b → a Vo = −20dBV Vo = −20dBV THD = 10% Po = 1 mW Rg = 600 Ω, IHF-A, SW2: b Vo = −20dBV Vo = −20dBV, monitor: tuner fr = 100 Hz, Vr = −20dBV, injected to VCC1 fr = 100 Hz, Vr = −20dBV, injected to VCC2 Vo = −20dBV f = 100 Hz, Vo = −20dBV f = 100 Hz, Vo = −30dBV f = 100 Hz, Vo = −50dBV Min ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6.5 −1.5 7 ⎯ ⎯ −32 −45 −70 −60 −100 22.5 −1.5 7 ⎯ ⎯ −27 −39 −58 −43 −95 1.5 8.5 9.5 Typ. ⎯ ⎯ 0.6 0.3 0.6 0.3 0.9 0.7 0.9 0.8 1.0 4.5 8 0 9.5 0.2 −98 −38 −51 −85 −75 −120 24 0 9.5 0.2 −90 −33 −45 −73 −58 −115 4.5 11.5 12.5 Max 5 5 1.0 0.6 1.0 0.6 1.4 1.4 1.4 1.6 ⎯ ⎯ 9.5 +1.5 ⎯ 0.5 −92 ⎯ ⎯ ⎯ ⎯ ⎯ 25.5 +1.5 ⎯ 0.5 −84 ⎯ ⎯ ⎯ ⎯ ⎯ 7.5 14.5 15.5 Unit µA µA mA mA mA mA mA mA mA mA mA mA dB dB mW % dBV dB dB dB dB dB dB dB mW % dBV dB dB dB dB dB dB dB dB 13 2006-04-19 TB2173FTG Characteristics Electronic volume Symbol Vim ∆ ATT CB3 ATT fopr VIH VIL ILI IOL IOH VBEEP V35 (ON) V35 (OFF) V34(ON) V34 (OFF) THD = 1% Vo = −10dBV Vo = −10dBV Vo = −10dBV Test Condition Min 250 −3.0 −1.5 −80 ⎯ Typ. 320 0 0 −90 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −50 ⎯ ⎯ ⎯ ⎯ Max ⎯ +3.0 +1.5 ⎯ 1 VDD VDD × 0.25 ±1 ⎯ ⎯ −45 VDD VDD × 0.2 VDD VDD × 0.2 Unit mVrms dB dB dB MHz V V µA mA mA dBV V V V V Maximum input level Attenuation error Channel balance Maximum attenuation Bus operating frequency High level CK, DATA, STB, and RESET input pins CK, DATA, STB, and RESET input pins VIH: VDD, VIL: 0 V VOL: 0.3 V VOH: VDD-0.3 V SW3: a Logic Input voltage Low level Input leakage current Port expansion driving current VDD × 0.75 0 ⎯ 1.0 −1.0 −55 VDD × 0.8 0 VDD × 0.8 0 Beep output level PW SW pin ON voltage PW SW pin OFF voltage MUTE SW pin ON voltage MUTE SW pin OFF voltage 14 2006-04-19 TB2173FTG Test Circuit Diagram Rg = 620 Ω 620 Ω Rg = 620 Ω Rg = 620 Ω 620 Ω Rg = 620 Ω 1 µF 25 IN1A 24 IN1B 1 µF 620 Ω (a) Rg = 620 Ω 50 kΩ 0.47 µF 0.47 µF 0.47 µF 1 µF VDD (a) SW3 (b) (a) SW4 (b) 33 C-SW 34 MUTE SW 32 GND 31 30 IN2A VOL OUTA 29 PRE INA 28 PRE INB 27 VOL OUTB 1 µF VDD 0.47 µF 50 kΩ 26 IN2B Rg = 620 Ω (a) (b) (b) SW2b SW2a (a) (a) (b) (b) SW1b SW1a 620 Ω 23 PRE GND MODE TC 22 0.47 µF 0.22 µF 35 PW SW MUTE TC 21 36 RESET BEEP 20 MCU 38 DATA BIAS IN 18 2.2 µF 39 STB TB2173FTG OUT ADJ 17 BIAS OUT BIAS OUT 10 µF 40 VDD 41 PRE NFA 42 PRE NFB 43 P1 RF 16 4.7 µF 10 µF 0.22 µF 2.2 µF BIAS OUT BIAS OUT 15 4.7 µF 4.7 µF LPF1 14 BST NF 13 44 P2 BEEP OUTA OUTA OUTC 1 2 3 PW GND 4 BEEP OUTB OUTB VCC2 5 6 7 10 µF BST TC 8 1 µF AGC DET 9 0.47 µF AGC IN 10 LPF2 12 0.22 µF BST OUT 11 1 µF RL RL 15 10 µF 37 CK VCC1 19 2006-04-19 TB2173FTG Example Application Circuit 1 (1.5-V OCL) Tuner IN Music IN 1 µF 1 µF 1 µF 25 IN1A VDD VDD 33 C-SW 34 MUTE SW 32 GND 31 30 IN2A VOL OUTA 29 PRE INA 28 PRE INB 27 VOL OUTB 26 IN2B 24 IN1B 1 µF 23 PRE GND MODE TC 22 0.47 µF 0.47 µF 0.47 µF 0.22 µF 35 PW SW MUTE TC 21 36 RESET BEEP 20 MCU 38 DATA BIAS IN 18 2.2 µF 39 STB TB2173FTG OUT ADJ 17 BIAS OUT BIAS OUT 10 µF 40 VDD 41 PRE NFA 42 PRE NFB 43 P1 RF 16 4.7 µF 10 µF 0.22 µF 2.2 µF BIAS OUT BIAS OUT 15 4.7 µF 4.7 µF LPF1 14 BST NF 13 44 P2 BEEP OUTA OUTA OUTC 1 2 3 PW GND 4 BEEP OUTB OUTB VCC2 5 6 7 10 µF BST TC 8 1 µF AGC DET 9 0.47 µF AGC IN 10 LPF2 12 0.22 µF BST OUT 11 1 µF RL RL 16 10 µF 37 CK VCC1 19 2006-04-19 TB2173FTG Example Application Circuit 2 (3-V output coupling, without low-frequency boost) Tuner IN Music IN 1 µF 1 µF 1 µF 25 IN1A VDD 33 C-SW 34 MUTE SW 32 GND 31 30 IN2A VOL OUTA 29 PRE INA 28 PRE INB 27 VOL OUTB 26 IN2B 24 IN1B 1 µF 23 PRE GND MODE TC 22 0.47 µF 0.47 µF 0.47 µF 0.22 µF 35 PW SW MUTE TC 21 36 RESET BEEP 20 MCU 38 DATA BIAS IN 18 2.2 µF 39 STB TB2173FTG OUT ADJ 17 BIAS OUT BIAS OUT 10 µF 40 VDD 41 PRE NFA 42 PRE NFB 43 P1 RF 16 4.7 µF 10 µF BIAS OUT 15 4.7 µF 4.7 µF LPF1 14 BIAS OUT BST NF 13 44 P2 BEEP OUTA OUTA OUTC 1 220 µF 2 3 PW GND 4 BEEP OUTB OUTB VCC2 5 6 7 220 µF 10 µF BST TC 8 AGC DET 9 AGC IN 10 LPF2 12 BST OUT 11 BIAS OUT RL RL 17 10 µF 37 CK VCC1 19 2006-04-19 TB2173FTG Package Dimensions W eight: 0.05 g (typ.) 18 2006-04-19 TB2173FTG RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 021023_D 060116EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux 19 2006-04-19