TB62214AFG/AFTG
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TB62214AFG, TB62214AFTG
BiCD Constant-Current Two-Phase Bipolar Stepping Motor Driver IC
The TB62214AFG/AFTG is a two-phase bipolar stepping motor
driver using a PWM chopper controlled by clock input.
Fabricated with the BiCD process, the TB62214AFG/AFTG is
rated at 40 V/2.0 A .
The on-chip voltage regulator allows control of a stepping motor
with a single VM power supply.
Features
• Bipolar stepping motor driver
• PWM constant-current drive
• Clock input control
• Allows two-phase, 1-2-phase and W1-2-phase excitations.
• BiCD process: Uses DMOS FETs as output power transistors.
• High voltage and current: 40 V/2.0 A (absolute maximum
•
•
TB62214AFG
HSOP28-P-0450-0.80
TB62214AFTG
ratings)
Thermal shutdown (TSD), overcurrent shutdown (ISD), and
power-on-resets (PORs)
Packages: HSOP28-P-0450-0.80
QFN48-P-0707-0.50
QFN48-P-0707-0.50
Weight
HSOP28-P-0450-0.80 : 0.79 g (typ.)
QFN48-P-0707-0.50 : 0.14 g (typ.)
© 2014 TOSHIBA Corporation
1
2014-10-01
TB62214AFG/AFTG
Pin Assignment
TB62214AFG (HSOP28)
CW/CCW
1
28
OSCM
MO_OUT
2
27
Vref_A
D_MODE_1
3
26
Vref_B
D_MODE_2
4
25
NC
CLK
5
24
NC
ENABLE
6
23
Vcc
RESET
7
22
VM
FIN(GND)
FIN(GND)
RS_A
8
21
RS_B
NC
9
20
NC
OUT_A
10
19
OUT_B
NC
11
18
NC
GND
12
17
GND
OUT_A
13
16
OUT_B
GND
14
15
GND
2
2014-10-01
TB62214AFG/AFTG
Pin Assignment
NC
VCC
NC
VM
NC
RS_B1
RS_B2
NC
OUT_B1
OUT_B2
NC
*
NC
TB62214AFTG (QFN48)
36
35
34
33
32
31
30
29
28
27
26
25
*
NC 37
24 NC
NC 38
23 NC
NC 39
22 GND
GND 40
21 OUT_B1
Vref_B 41
20 OUT_B2
Vref_A 42
19 GND
OSCM 43
18 GND
CW/CCW 44
17 OUT_A2
MO_OUT 45
16 OUT_A1
6
7
8
9
10
11
12
NC
5
OUT_A2
4
OUT_A1
3
NC
2
RS_A2
1
RS_A1
*
NC
13 NC
GND
NC 48
RESET
14 NC
ENABLE
D_MODE_2 47
CLK
15 GND
NC
D_MODE_1 46
*
*Mark PAD: It must be connected to GND
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2014-10-01
TB62214AFG/AFTG
Block Diagram
RESET
VM
CW/CCW
VMR
Detect
ENABLE
Vcc Voltage
Regulator
Step Decoder
D_MODE_1
(Input Logic)
D_MODE_2
MO_OUT
Vcc
Chopper OSC
CLK
OSCM
OSC
CR-CLK
Converter
Current Level Set
Vref
Current Feedback (×2)
VM
VRS
Output Control
(Mixed Decay Control)
RS COMP
RS
ISD
ENABLE
Output
(H-Bridge×2)
VM
TSD
VMR
Detect
Detection Circuit
Stepping
Motor
In the block diagram, part of the functional blocks or constants may be omitted or simplified for explanatory
purposes.
Note: All the grounding wires of the TB62214AFG/AFTG must run on the solder mask on the PCB and be
externally terminated at only one point. Also, a grounding method should be considered for efficient heat
dissipation.
Careful attention should be paid to the layout of the output, VDD (VM) and GND traces, to avoid short-circuits
across output pins or to the power supply or ground. If such a short-circuit occurs, the TB62214AFG/AFTG may be
permanently damaged.
Also, utmost care should be taken for pattern designing and implementation of the TB62214AFG/AFTG since it
has the power supply pins (VM, RS_A, RS_B, OUT_A, OUT_A , OUT_B, OUT_B , GND) particularly a large current
can run through. If these pins are wired incorrectly, an operation error or even worse a destruction of the
TB62214AFG/AFTG may occur.
The logic input pins must be correctly wired, too; otherwise, the TB62214AFG/AFTG may be damaged due to a
current larger than the specified current running through the IC.
Please note the above when designing and implementing IC patterns.
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2014-10-01
TB62214AFG/AFTG
Pin Function
TB62214AFG (HSOP28)
Pin No.
Pin Name
Function
1
CW/CCW
Motor rotation: forward/reverse
2
MO_OUT
Electric angle monitor
3
D_MODE_1
Excitation mode control
4
D_MODE_2
Excitation mode control
5
CLK
6
ENABLE
A-/B-channel output enable
7
RESET
Electric angle reset
8
RS_A
9
NC
10
OUT_A
11
NC
An electrical angle leads on the rising edge of the clock input. A motor rotation
count depends on the input frequency.
The sink current sensing of A-phase motor coil
No-connect
A-phase positive driver output
No-connect
12
GND
13
OUT_A
Motor power ground
14
GND
Motor power ground
15
GND
Motor power ground
16
OUT_B
17
GND
18
NC
19
OUT_B
20
NC
21
RS_B
A-phase negative driver output
B-phase negative driver output
Motor power ground
No-connect
B-phase positive driver output
No-connect
The sink current sensing of B-phase motor coil
22
VM
Power supply
23
VCC
Smoothing filter for logic power supply
24
NC
No-connect
25
NC
No-connect
26
Vref_B
Tunes the current level for B-phase motor drive.
27
Vref_A
Tunes the current level for A-phase motor drive.
28
OSCM
Oscillator pin for PWM chopper
Pin Interfaces (HSOP28)
8 21
150Ω
22
1
3
5
4
6
8kΩ
3kΩ
100kΩ
7
3kΩ
FIN
16
12
14
17
15
1kΩ
26
100kΩ
13
19
23
150Ω
2
10
1kΩ
28
27
500Ω
FIN
FIN
FIN
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for
explanatory purposes. Absolute precision of the chip internal resistance is +/-30%.
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2014-10-01
TB62214AFG/AFTG
TB62214AFTG (QFN48)
Pin
No.
Pin Name
1
NC
No-connect
2
CLK
An electrical angle leads on the rising edge of
the clock input. A motor rotation count depends 26
on the input frequency.
OUT_B2
3
ENABLE
A-/B-channel output enable
27
OUT_B1
4
RESET
Electric angle reset
28
NC
5
GND
Logic ground
29
RS_B2
6
NC
No-connect
30
RS_B1
7
RS_A1
31
NC
No-connect
8
RS_A2
Power supply of A-phase motor coil and the
sink current sensing of A-phase motor coil
32
VM
Power supply
9
NC
No-connect
33
NC
No-connect
10
OUT_A1
34
VCC
Smoothing filter for logic power supply
11
OUT_A2
35
NC
No-connect
12
NC
No-connect
36
NC
No-connect
13
NC
No-connect
37
NC
No-connect
14
NC
No-connect
38
NC
No-connect
15
GND
Motor power ground
39
NC
No-connect
16
OUT_A1
40
GND
41
Vref_B
Tunes the current level for B-phase motor
drive.
Vref_A
Tunes the current level for A-phase motor
drive.
Function
A-phase positive driver output
A-phase negative driver output
Pin
No.
Pin Name
25
NC
Function
No-connect
B-phase positive driver output
No-connect
Power supply of B-phase motor coil and the
sink current sensing of B-phase motor coil
Logic ground
17
OUT_A2
18
GND
Motor power ground
42
19
GND
Motor power ground
43
OSCM
Oscillator pin for PWM chopper
20
OUT_B2
44
CW/CCW
Motor rotation: forward/reverse
21
OUT_B1
45
MO_OUT
Electric angle monitor
22
GND
23
24
B-phase negative driver output
Motor power ground
46 D_MODE_1 Excitation mode control
NC
No-connect
47 D_MODE_2 Excitation mode control
NC
No-connect
48
NC
No-connect
Pin Interfaces (QFN48)
150Ω
8 29
2
3
4
44
46
32
100kΩ
8kΩ
3kΩ
47
3kΩ
27
21
10
16
11
17
26
20
7
40
30
15
18
22
19
34
150Ω
1kΩ
45
41
100kΩ
40
1kΩ
43
42
500Ω
40
40
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for
explanatory purposes. Absolute precision of the chip internal resistance is +/-30%.
6
2014-10-01
TB62214AFG/AFTG
CLK Function
The electrical angle leads one by one in the manner of the clocks. The clock signal is reflected to the electrical
angle on the rising edge.
CLK Input
Function
Rise
The electrical angle leads by one on the rising edge.
Fall
Remains at the same position.
ENABLE Function
The ENABLE pin controls whether or not to let the current flow through a given phase for a stepper motor drive.
This pin serves to select if the motor is stopped in Off mode or activated. The pin must be fixed to Low on the
power-on or power-down of the TB62214AFG/AFTG. During power on, once the VM voltage has reached the voltage
required to operate the motor, set this to High.
ENABLE Input
Function
H
Output transistors are enabled (normal operation mode).
L
Output transistors are disabled (high impedance state).
CW/CCW Function
The CW/CCW pin switches rotation direction of stepper motors.
The CW pin outputs the A-phase current 90° behind than the B-phase current.
The CCW pin outputs the A-phase current 90° ahead of the B-phase current.
CW/CCW Input
Function
H
Forward (CW)
L
Reverse (CCW)
Excitation Mode Select Function
D_MODE_1
D_MODE_2
Function
L
L
OSC_M, output transistors are disabled (in Standby mode)
L
H
Two-phase excitation
H
L
1-2-phase excitation
H
H
W1-2-phase excitation
RESET Function
The RESET function resets the electrical angle. Always set this to H during power on. Once the VM voltage has
reached the voltage required to operate the motor, release RESET.
RESET Input
Function
L
Normal operation mode
H
The electrical angle is reset.
The phase current while RESET is applied is shown in the table below. MO_OUT is Low at this time.
Excitation Mode
A-phase Current
B-phase Current
2 Phase
100%
100%
1 – 2 Phase
100%
100%
W1-2 Phase
71%
71%
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2014-10-01
TB62214AFG/AFTG
Detection Features
(1)
Thermal shutdown (TSD)
The thermal shutdown circuit turns off all the outputs when the junction temperature (Tj) exceeds 150°C
(typ.). The outputs retain the current states.
The TB62214AFG/AFTG exits TSD mode and resume normal operation when the TB62214AFG/AFTG is
rebooted or both the D_MODE_1 and D_MODE_2 pins are switched to Low.
(2)
Power-ON-resets (PORs) for VMR and VCCR (VM and VCC voltage monitor)
The outputs are forced off until VM and VCC reach the rated voltages.
(3)
Overcurrent shutdown (ISD)
Each phase has an overcurrent shutdown circuit, which turns off the corresponding outputs when the
output current exceeds the shutdown trip threshold (above the maximum current rating: 2.0 A minimum).
The TB62214AFG/AFTG exits ISD mode and resumes normal operation when the TB62214AFG/AFTG is
rebooted or both the D_MODE_1 and D_MODE_2 pins are switched to Low.
This circuit provides protection against a short-circuit by temporarily disabling the device. Important notes
on this feature will be provided later.
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2014-10-01
TB62214AFG/AFTG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Remarks
Motor power supply
VM
40
V
―
Motor output voltage
VOUT
40
V
―
Motor output current
IOUT
2.0
A per phase
(Note 1)
Digital input voltage
VIN
-0.5 to 6.0
V
―
Vref standard voltage
Vref
5.0
V
―
MO output voltage
VMO
6.0
V
―
MO output sink current
IMO
30.0
mA
―
PD
1.3
W
(Note 2)
Power dissipation
QFN48
PD
1.3
W
(Note 2)
Operating temperature
HSOP28
Topr
−20 to 85
°C
―
Storage temperature
Tstg
−55 to 150
°C
―
Junction temperature
Tj (MAX)
150
°C
―
Note 1: As a guide, the maximum output current should be kept below 1.4 A per phase. The maximum output current
may be further limited by thermal considerations, depending on ambient temperature and board conditions.
Note 2: Stand-alone (Ta = 25°C)
If Ta is over 25°C, derating is required at 10.4 mW/°C.
Ta: Ambient temperature
Topr: Ambient temperature while the TB62214AFG/AFTG is active
Tj: Junction temperature while the TB62214AFG/AFTG is active. The maximum junction temperature is
limited by the thermal shutdown (TSD) circuitry. It is advisable to keep the maximum current below a
certain level so that the maximum junction temperature, Tj (MAX), will not exceed 120°C.
Note: The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even
for a moment. Do not exceed any of these ratings.
Exceeding the rating (s) may cause breakdown, damage or deterioration of the device, and may result in injury by
explosion or combustion.
The value of even one parameter of the absolute maximum ratings should not be exceeded under any circumstances.
The TB62214AFG/AFTG does not have overvoltage protection. Therefore, the device is damaged if a voltage
exceeding its rated maximum is applied.
All voltage ratings including supply voltages must always be followed. The other notes and considerations described
later should also be referred to.
Operating Ranges (Ta=0 to 85°C)
Characteristics
Symbol
Min
Typ.
Max
Unit
Remarks
Motor power supply
VM
10.0
24.0
38.0
V
―
Motor output current
IOUT
―
1.4
2.0
A
Per phase (Note 1)
VIN (H)
2.0
―
5.5
V
High-level logic
VIN (L)
-0.4
―
1.0
V
Low-level logic
VMO
―
3.3
5.5
V
With a pull-up resistor
Digital input voltage
MO output voltage
Clock input frequency
fCLK
―
―
100
kHz
―
Chopper frequency
fchop
40.0
100.0
150
kHz
―
Vref reference voltage
Vref
GND
―
3.6
V
―
Voltage across the current-sensing resistor pins
VRS
0.0
±1.0
±1.5
V
Referenced to the VM pin (Note 2)
Note 1: The actual maximum current may be limited by the operating environment (operating conditions such as
excitation mode or operating duration, or by the surrounding temperature or board heat dissipation).
Determine a realistic maximum current by calculating the heat generated under the operating environment.
Note 2: The maximum VRS voltage should not exceed the maximum rated voltage.
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2014-10-01
TB62214AFG/AFTG
Electrical Characteristics 1 (Ta = 25°C, VM = 24 V, unless otherwise specified)
Characteristics
Symbol
Test
Circuit
VIN (HIS)
DC
Digital input pins
IIN (H)
Min
Typ.
Max
Unit
(Note1)
100
200
300
mV
DC
VIN = 5 V at the digital input pins under
test
35
50
75
μA
IIN (L)
DC
V IN = 0 V at the digital input pins
under test
―
―
1
μA
High
VOH (MO)
―
IOH = 24 mA when the output is High
2.4
―
―
V
Low
VOL (MO)
―
IOL = 24 mA when the output is Low
―
―
0.5
V
IM1
DC
Outputs open, In standby mode
―
2
3
mA
IM2
DC
Outputs open, ENABLE = Low
―
3.5
5
mA
IM3
DC
Outputs open (two-phase excitation)
―
5
7
mA
High-side
IOH
DC
VRS = VM = 40 V, VOUT = 0 V
―
―
1
μA
Low-side
IOL
DC
VRS = VM = VOUT = 40 V
1
―
―
μA
Channel-to-channel differential
∆IOUT1
DC
Channel-to-channel error
−5
0
5
%
Output current error relative to
the predetermined value
∆IOUT2
DC
IOUT = 1 A
−5
0
5
%
IRS
DC
VRS = VM = 24 V
0
―
10
μA
RON (D-S)
DC
IOUT = 2.0 A, Tj = 25°C
―
1.0
1.5
Ω
Input hysteresis voltage
High
Digital input current
(Note2)
Low
MO output voltage
Supply current
Output leakage
current
RS pin current
Drain-source ON-resistance of
the output transistors
(upper and lower sum)
Test Condition
(Note3)
Note1: VIN (L → H) is defined as the VIN voltage that causes the outputs (OUT_A1, OUT_A2, OUT_B1 and OUT_B2)
to change when a pin under test is gradually raised from 0 V. V IN (H → L) is defined as the V IN voltage that
causes the outputs (OUT_A1, OUT_A2, OUT_B1 and OUT_B2) to change when the pin is then gradually
lowered.
The difference between V IN (L → H) and V IN (H → L) is defined as the input hysteresis.
Note2:
The circuit design has been designed so that electromotive force or leak current from signal input does not
occur when VM voltage is not supplied, even if the logic input signal is input. Even so, regulate logic input
signals before resupply of VM voltage so that the motor does not operate when voltage is reapplied.
Note 3: If the supply voltage for internal circuitry (VCC) is split with an external resistor and used as Vref input supply
voltage, the accuracy of the output current setting will be at ±8% when the VCC output voltage accuracy and
the Vref damping ratio accuracy are combined.
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2014-10-01
TB62214AFG/AFTG
Electrical Characteristics 2 (Ta = 25°C, VM = 24 V, unless otherwise specified)
Characteristics
Vref input current
Vref decay rate
TSD threshold
(Note 1)
VM recovery voltage
Overcurrent trip threshold
(Note 2)
Supply voltage for internal circuitry
Symbol
Test
Circuit
Iref
DC
Vref (GAIN)
DC
TjTSD
DC
VMR
ISD
VCC
DC
Test Condition
Min
Typ.
Max
Unit
Vref = 3.0 V
―
0
1
μA
Vref = 2.0 V
1/4.8
1/5.0
1/5.2
―
―
140
150
170
°C
DC
―
7.0
8.0
9.0
V
DC
―
2.0
3.0
4.0
A
4.75
5.00
5.25
V
ICC = 5.0 mA
Note 1: Thermal shutdown (TSD) circuitry
When the junction temperature of the device has reached the threshold, the TSD circuitry is tripped, causing
the internal reset circuitry to turn off the output transistors.
The TSD circuitry is tripped at a temperature between 140°C (min) and 170°C (max). Once tripped, the TSD
circuitry keeps the output transistors off until both the D_MODE_1 and D_MODE_2 pins are switched to Low
or the TB62214AFG/AFTG is rebooted.
The thermal shutdown circuit is provided to turn off all the outputs when the IC is overheated. For this
reason, please avoid using TSD for other purposes.
Note 2: Overcurrent shutdown (ISD) circuitry
When the output current has reached the threshold, the ISD circuitry is tripped, causing the internal reset
circuitry to turn off the output transistors.
To prevent the ISD circuitry from being tripped due to switching noise, it has a masking time of four CR
oscillator cycles. Once tripped, it takes a maximum of four cycles to exit ISD mode and resume normal
operation.
The ISD circuitry remains active until both the D_MODE_1 and D_MODE_2 pins are switched to Low or the
TB62214AFG/AFTG is rebooted.
The TB62214AFG/AFTG remains in Standby mode while in ISD mode.
Back-EMF
While a motor is rotating, there is a timing at which power is fed back to the power supply. At that timing, the
motor current recirculates back to the power supply due to the effect of the motor back-EMF.
If the power supply does not have enough sink capability, the power supply and output pins of the device might
rise above the rated voltages. The magnitude of the motor back-EMF varies with usage conditions and motor
characteristics. It must be fully verified that there is no risk that the TB62214AFG/AFTG or other components will
be damaged or fail due to the motor back-EMF.
Cautions on Overcurrent Shutdown (ISD) and Thermal Shutdown (TSD)
The ISD and TSD circuits are only intended to provide temporary protection against irregular conditions such as an
output short-circuit; they do not necessarily guarantee the complete IC safety.
If the device is used beyond the specified operating ranges, these circuits may not operate properly: then the device
may be damaged due to an output short-circuit.
The ISD circuit is only intended to provide a temporary protection against an output short-circuit. If such a
condition persists for a long time, the device may be damaged due to overstress. Overcurrent conditions must be
removed immediately by external hardware.
IC Mounting
Do not insert devices incorrectly or in the wrong orientation. Otherwise, it may cause breakdown, damage and/or
deterioration of the device.
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2014-10-01
TB62214AFG/AFTG
AC Electrical Characteristics (Ta = 25°C, VM = 24 V, 6.8 mH/5.7Ω)
Symbol
Test
Circuit
fCLK
AC
fOSC = 1600 kHz
Minimum high pulse width of
CLK input filter
TCLK (H)
AC
Minimum low pulse width of
CLK input filter
TCLK (L)
tr
Characteristics
Clock input frequency
Output transistor switching
characteristics
Test Condition
Min
Typ.
Max
Unit
―
―
100
kHz
High time of the clock input frequency
300
―
―
ns
AC
Low time of the clock input frequency
250
―
―
ns
AC
―
100
150
200
ns
―
tf
AC
100
150
200
ns
tpLH (CLK)
AC
CLK to OUT
―
1000
―
ns
tpHL (CLK)
AC
CLK to OUT
―
1500
―
ns
tBLANK
AC
IOUT =1.0 A
200
300
500
ns
COSC = 270 pF, ROSC = 3.6 kΩ
1200
1600
2000
kHz
40
100
150
kHz
kHz
Blanking time for current spike
prevention
OSC_M oscillation frequency
fOSC
AC
Chopper frequency range
fchop(RANGE)
AC
Chopper setting frequency
fchop
AC
Output ACTIVE (lout=1.0A),
CR= 1600 kHz
−
100
−
tISD (Mask)
AC
After ISD threshold is exceeded due to
an output short-circuit to power or
ground
―
4
―
AC
After ISD threshold is exceeded due to
an output short-circuit to power or
ground.
(Note1)
4
ISD masking time
ISD on-time
tISD
VM=24V, Output ACTIVE (lout=1.0A)
―
―
8
Note1: In the output short-to-power or -ground, I counted in OSC_M number of clocks from beyond the ISD threshold.
Timing Charts of Output Transistors Switching
90%
1/fCLK
CLK
50%
50%
10%
tpLH
tpHL
VM
90%
Output voltage
90%
50%
50%
10%
10%
GND
tr
tf
Timing charts may be simplified for explanatory purposes.
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2014-10-01
TB62214AFG/AFTG
Current Waveform in Mixed-Decay Mode
Timing charts may be simplified for explanatory purposes.
Mixed-Decay mode, the purpose of which is constant-current control, starts out in Fast-Decay mode for 37.5%
of the whole period and then is followed by Slow-Decay mode for the remainder of the period.
fchop
fchop
Internal
CR CLK
IOUT
Predefined
current level
MDT
MDT
Predefined current level
NF
NF
37.5%
Mixed-decay
MDT (mixed decay timing) Point: 37.5% (6/16) Fixed
Timing Charts of CLK, Output Current and MO Output
Clock input
A phase
Two-phase
excitation
B phase
MO output
A phase
1-2-phase
excitation
B phase
MO output
A phase
W1-2 phase
excitation
B phase
MO output
Timing charts may be simplified for explanatory purposes.
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TB62214AFG/AFTG
Current Waveform in Mixed (Slow + Fast) Decay Mode
When a current value increases (Mixed-Decay point is fixed to 37.5%)
fchop
fchop
fchop
fchop
Internal
OSCM CLK
Predefined
current level
NF
NF
Slow
Fast
Predefined
current level
NF
NF
Slow
Charge
Slow
Charge
Fast
Charge
Slow
Fast
Charge
Fast
When a current value decreases (Mixed-Decay point is fixed to 37.5%)
fchop
fchop
fchop
fchop
Internal
OSCM CLK
The IC enters Charge mode for a moment at which
the internal RS comparator compares the values.
The IC immediately enters Slow-Decay mode
because of the current value exceeding the
Predefined
current level
NF
NF
Slow
Charge
Fast
Slow
Charge
Fast
Predefined
current level
NF
Charge
Slow
Fast
NF
Charge
NF
Slow
Fast
Charge
The Charge period starts as the internal oscillator clock starts counting. When the output current reaches the
predefined current level, the internal RS comparator detects the predefined current level (NF); as a result, the IC
enters Slow-Decay mode.
The TB62214AFG/AFTG transits from Slow-Decay mode to Fast-Decay mode at the point 37.5 of a PWM
frequency (one chopping frequency) remains in a whole PWM frequency period (on the rising edge of the 11th
clock of the OSCM clock).
When the OSCM pin clock counter clocks 16 times, the Fast-Decay mode ends; and at the same time, the
counter is reset, which brings the TB62214AFG/AFTG into Charge mode again.
Note: These figures are intended for illustrative purposes only. If designed more realistically, they would show
transient response curves.
Timing charts may be simplified for explanatory purposes.
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TB62214AFG/AFTG
Output Transistor Operating Modes
VM
VM
RRS
VM
RRS
RS Pin
RRS
RS Pin
RS Pin
U1
U2
U1
U2
U1
U2
ON
OFF
OFF
OFF
OFF
ON
Load
Load
Load
L1
L2
L1
L2
L1
L2
OFF
ON
ON
ON
ON
OFF
PGND
PGND
Charge Mode
A current flows into the motor
coil.
PGND
Slow-Decay Mode
A current circulates around the
motor coil and this device.
Fast-Decay Mode
The energy of the motor coil
is fed back to the power
l
Output Transistor Operating Modes
CLK
U1
U2
L1
L2
Charge
ON
OFF
OFF
ON
Slow-decay Mode
OFF
OFF
ON
ON
Fast-decay Mode
OFF
ON
ON
OFF
Note: This table shows an example of when the current flows as indicated by the arrows in the figures shown above.
If the current flows in the opposite direction, refer to the following table.
CLK
U1
U2
L1
L2
Charge
OFF
ON
ON
OFF
Slow-decay Mode
OFF
OFF
ON
ON
Fast-decay Mode
ON
OFF
OFF
ON
The TB62214AFG/AFGT switches among Charge, Slow-Decay and Fast-Decay modes automatically for
constant-current control.
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
Calculation of the Predefined Output Current
For PWM constant-current control, the TB62214AFG/AFTG uses a clock generated by the CR oscillator. The peak
output current can be set via the current-sensing resistor (RRS) and the reference voltage (Vref), as follows:
IOUT = Vref/5 ÷ RS (Ω)
where, 1/5 is the Vref decay rate, Vref (GAIN). For the value of Vref (GAIN), see the Electrical Characteristics table.
For example, when Vref = 3 V, to generate an output current (IOUT) of 0.8 A, RRS is calculated as:
RRS = (Vref /5) ÷ IOUT = (3/5) ÷ 0.8 = 0.75Ω. (≥ 0.5 W)
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TB62214AFG/AFTG
IC Power Consumption
The power consumed by the TB62214AFG/AFTG is approximately the sum of the following two: 1) the power
consumed by the output transistors, and 2) the power consumed by the digital logic and pre-drivers.
The power consumed by the output transistors is calculated, using the RON (D-S) value of 1.0Ω.
Whether in Charge, Fast Decay or Slow Decay mode, two of the four transistors comprising each H-bridge
contribute to its power consumption at a given time.
Thus the power consumed by each H-bridge is given by:
P (out) = IOUT (A) × VDS (V) = 2 × IOUT2 × RON ......................................... (1)
In two-phase excitation mode (in which two phases have a phase difference of 90°), the average
power consumption in the output transistors is calculated as follows:
RON = 1.0 Ω (@2.0 A), the sum of the high-side DMOS and low-side DMOS
IOUT (Peak) = 1.0 A
VM = 24 V
P (out) = 2Hsw × 1.02 (A) × 1.0 (Ω) = 2.0 (W) ................................................ (2)
The power consumption in the IM domain is calculated separately for normal operation and
standby modes:
Normal operation mode: I (IM3) = 5.0 mA (typ.)
Standby mode: I (IM1) = 2.0 mA (typ.)
The current consumed in the digital logic portion of the TB62214AFG/AFTG is indicated as IMx.
The digital logic operates off a voltage regulator that is internally connected to the VM power supply.
It consists of the digital logic connected to VM (24 V) and the network affected by the switching of the
output transistors. The total power consumed by IMx can be estimated as:
P (IM) = 24 (V) × 0.005 (A) = 0.12 (W) .......................................................... (3)
Hence, the total power consumption of the TB62214AFG/AFTG is:
P = P (out) + P (IM) = 2.12 (W)
The standby power consumption is given by:
P (Standby) + P (out) = 24 (V) × 0.002 (A) = 0.048 (W)
Board design should be fully verified, taking thermal dissipation into consideration.
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TB62214AFG/AFTG
OSC-Charge Delay
Since the rising level of the OSC waveform is referenced to convert it into the internal CR CLK waveform,
about up to1 us (when CR = 1600 kHz) of a delay occurs between the OSC waveform and internal CR CLK
waveform.
OSC charge delay
Internal
CR CLK
OSC fast delay
H
OSC (CR)
L
tchop
Output
voltage
OUT_A
Output
voltage
OUT _ A
H
50%
L
H
50%
50%
L
Predefined
current level
Output
current
L
Charge
Slow
Fast
Timing Waveforms of OSC and Internal CR CLK
Timing charts may be simplified for explanatory purposes.
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TB62214AFG/AFTG
Phase Sequences
Two-Phase Excitation Mode
150
100
CW
B Phase
50
−150
0
−100
−50
0
50
100
150
Initialize position
MO output: Low
−50
CCW
−100
−150
A Phase
1-2-Phase Excitation Mode
150
100
CW
B Phase
50
−150
0
−100
−50
0
50
100
150
Initialize position
MO output: Low
−50
CCW
−100
−150
A Phase
W1-2-Phase Excitation Mode
150
CW
100
B Phase
50
−150
0
−100
−50
0
50
100
−50
−100
150
Initialize position
MO output: Low
CCW
−150
A Phase
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TB62214AFG/AFTG
Overcurrent Shutdown (ISD) Circuitry
ISD Masking Time and ISD On-Time
OSC_M oscillation
(chopper waveform)
min
max
Disabled (reset state)
min
max
ISD masking time
ISD on-time
1 chopping cycle
An overcurrent starts flowing into the output transistors
The overcurrent shutdown (ISD) circuitry has a masking time to prevent current spikes during Irr and
switching from erroneously tripping the ISD circuitry. The masking time is a function of the chopper
frequency obtained by CR:
masking_time = 4 × CR_frequency
The minimum and maximum times taken to turn off the output transistors since an overcurrent flows into
them are:
Min: 4 × CR_frequency
Max: 8 × CR_frequency
It should be noted that these values assume a case in which an overcurrent condition is detected in an ideal
manner. The ISD circuitry might not work, depending on the control timing of the output transistors.
Therefore, a protection fuse must always be added to the VM power supply as a safety precaution. The
optimal fuse capacitance varies with usage conditions, and one that does not adversely affect the motor
operation or exceed the power dissipation rating of the TB62214AFG/AFTG should be selected.
Calculating OSCM Oscillating Frequency
The OSCM oscillating frequency can be approximated using the following equation:
fOSCM =
1
0.56 × C × (R 1 + 500 )
Where:
C = Capacitor capacity
R1= Resistance
Assigning C = 270 × 10−12 [F], R1= 3600 [Ω] to get:
fOSCM = 1.61 × 106 ⇒ 1.6 MHz
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TB62214AFG/AFTG
PD – Ta (Package Power Dissipation)
2 layer glass epoxy board
(Board Layer: 2 layer Cu thickness: 55 um, Board size: 85 mm × 85 mm × 1.6 mm)
Power Dissipation
PD (W)
θj-a: 38°C/W (typ.)
1.71
85
Ambient Temperature Ta (°C)
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TB62214AFG/AFTG
Example Application Circuits
TB62214AFG
0.1 μF
18
17
16
GND
19
OUT_B
20
GND
21
NC
Fin(GND)
OUT_B
0.51 Ω
0.1 μF
22
NC
23
RS_B
24
VCC
25
NC
26
NC
0.1 μF
27
Vref_B
Vref_A
OSCM
28
24 V
100 μF
3.6 kΩ
VM
270 pF
The values shown in the following figure are typical values. For input conditions, see Operating Ranges.
15
0V
5V
5V
3.3 V 3.3 V
0V
0V
5V
5V
3.3 V 3.3 V
0V
0V
11
12
13
GND
10
OUT_A
9
GND
8
NC
Fin(GND)
OUT_A
7
NC
6
RESET
5
ENABLE
4
CLK
D_MODE_2
3
0.51 Ω RS_A
5V
3.3 V
2
D_MODE_1
1
MO_OUT
50 kΩ
CW/CCW
M
14
Note: Bypass capacitors should be added as necessary.
It is recommended to use a single ground plane for the entire board whenever possible, and a grounding
method should be considered for efficient heat dissipation.
In cases where mode setting pins are controlled via switches, either pull-down or pull-up resistors should be
added to them to avoid floating states.
For a description of the input values, see the function tables.
The above application circuit example is presented only as a guide and should be fully evaluated prior to
production. Also, no intellectual property right is ceded in any way whatsoever in regard to its use.
The external components in the above diagram are used to test the electrical characteristics of the device: it is
not guaranteed that no system malfunction or failure will occur.
Careful attention should be paid to the layout of the output, VDD (VM) and GND traces to avoid short-circuits across output pins or to
the power supply or ground. If such a short-circuit occurs, the TB62214AFG/AFTG may be permanently damaged. Also, if the device is
installed in a wrong orientation, a high voltage might be applied to components with lower voltage ratings, causing them to be
damaged. The TB62214AFG/AFTG does not have an overvoltage protection circuit. Thus, if a voltage exceeding the rated maximum
voltage is applied, the TB62214AFG/AFTG will be damaged; it should be ensured that it is used within the specified operating
conditions.
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TB62214AFG/AFTG
TB62214AFTG
34
33
32
31
30
29
28
27
26
NC
OUT_B2
OUT_B1
NC
RS_B2
0.51 Ω
RS_B1
0.1 μF
NC
35
24 V
NC
100 μF
VM
NC
36
VCC
NC
0.1 μF
The values shown in the following figure are typical values. For input conditions, see the Operating Ranges.
25
NC 37
24 NC
NC 38
23 NC
NC 39
22
GND
GND
OUT_B1
40
21
41
20
Vref_A 42
3.6 kΩ OSCM
43
270 pF
19
44
17
50 kΩ
45
MO_OUT
16
46
15
47
14 NC
NC 48
13 NC
6
7
8
9
10
11
OUT_B2
GND
GND
M
OUT_A2
OUT_A1
GND
12
NC
5
OUT_A2
4
OUT_A1
3
NC
2
CLK
NC
1
RS_A2
D_MODE_2
0.51 Ω
5V
3.3 V
RS_A1
D_MODE_1
NC
0V
5V
3.3 V
GND
0V
CW/CCW
RESET
0V
5V
3.3 V
18
ENABLE
0.1 μF
Vref_B
5V
5V
3.3 V 3.3 V
0V
0V
Note: Bypass capacitors should be added as necessary.
It is recommended to use a single ground plane for the entire board whenever possible, and a grounding
method should be considered for efficient heat dissipation.
In cases where mode setting pins are controlled via switches, either pull-down or pull-up resistors should be
added to them to avoid floating states.
For a description of the input values, see the function tables.
The above application circuit example is presented only as a guide and should be fully evaluated prior to
production. Also, no intellectual property right is ceded in any way whatsoever in regard to its use.
The external components in the above diagram are used to test the electrical characteristics of the device: it is
not guaranteed that no system malfunction or failure will occur.
Careful attention should be paid to the layout of the output, VDD (VM) and GND traces to avoid short-circuits across output pins or to
the power supply or ground. If such a short-circuit occurs, the TB62214AFG/AFTG may be permanently damaged. Also, if the device is
installed in a wrong orientation, a high voltage might be applied to components with lower voltage ratings, causing them to be
damaged. The TB62214AFG/AFTG does not have an overvoltage protection circuit. Thus, if a voltage exceeding the rated maximum
voltage is applied, the TB62214AFG/AFTG will be damaged; it should be ensured that it is used within the specified operating
conditions.
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TB62214AFG/AFTG
Package Dimensions
HSOP28-P-0450-0.80
Weight: 0.79 g (typ.)
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TB62214AFG/AFTG
QFN48-P-0707-0.50
Unit: mm
Pin#1 Index Mark Area
Backside heatsink: 5.4 mm × 5.4 mm
Corner chamfers: C0.5
Chamfer radius: 3-R0.2
Weight: 0.14 g (typ.)
Land Pattern Example (double-sided board)
Surface
Bottom
White dots: 0.2-mm through holes
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TB62214AFG/AFTG
Notes on Contents
Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Timing Charts
Timing charts may be simplified for explanatory purposes.
Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is
required at the mass production design stage. Toshiba does not grant any license to any industrial property rights by
providing these examples of application circuits.
Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These components
and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment.
IC Usage Considerations
Notes on handling of ICs
(1)
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment. Do not exceed any of these ratings.Exceeding the rating(s) may cause
device breakdown, damage or deterioration, and may result in injury by explosion or combustion.
(2)
Use an appropriate power supply fuse to ensure that a large current does not continuously flow in
the case of over-current and/or IC failure. The IC will fully break down when used under conditions
that exceed its absolute maximum ratings, when the wiring is routed improperly or when an
abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow
and the breakdown can lead to smoke or ignition. To minimize the effects of the flow of a large
current in the case of breakdown, appropriate settings, such as fuse capacity, fusing time and
insertion circuit location, are required.
(3)
If your design includes an inductive load such as a motor coil, incorporate a protection circuit into
the design to prevent device malfunction or breakdown caused by the current resulting from the
inrush current at power ON or the negative current resulting from the back electromotive force at
power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs
with built-in protection functions. If the power supply is unstable, the protection function may not
operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition.
(4)
Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and
negative terminals of power supplies are connected properly. Otherwise, the current or power
consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause
device breakdown, damage or deterioration, and may result in injury by explosion or combustion. In
addition, do not use any device that has been inserted incorrectly.
(5)
Please take extra care when selecting external components (such as power amps and regulators) or external devices
(for instance, speakers). When large amounts of leak current occurs from capacitors, the DC output level may
increase. If the output is connected to devices such as speakers with low resist voltage, overcurrent or IC failure
may cause smoke or ignition. (The over-current may cause smoke or ignition from the IC itself.) In particular,
please pay attention when using a Bridge Tied Load (BTL) connection-type IC that inputs output DC voltage to a
speaker directly.
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2014-10-01
TB62214AFG/AFTG
Points to remember on handling of ICs
Over current Protection Circuit
Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs under all
circumstances. If the Over current protection circuits operate against the over current, clear the over current status
immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the over
current protection circuit to not operate properly or IC breakdown before operation. In addition, depending on the method of
use and usage conditions, if over current continues to flow for a long time after operation, the IC may generate heat
resulting in breakdown.
Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown circuits operate
against the over temperature, clear the heat generation status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal
shutdown circuit to not operate properly or IC breakdown before operation.
Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is
appropriately radiated, not to exceed the specified junction temperature (TJ) at any time and condition. These ICs generate
heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC
characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation
with peripheral components.
Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s power
supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power
supply and output pins might be exposed to conditions beyond absolute maximum ratings. To avoid this problem, take the
effect of back-EMF into consideration in system design.
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2014-10-01
TB62214AFG/AFTG
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product,
or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all
relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for
Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for
the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product
design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or
applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams,
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such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
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MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
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limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
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OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
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