TB6560AHQ/AFG
TOSHIBA BiCD Integrated Circuit
Silicon Monolithic
TB6560AHQ, TB6560AFG
PWM Chopper-Type Bipolar Driver IC for Stepping Motor Control
The TB6560AHQ/AFG is a PWM chopper-type stepping motor
driver IC designed for sinusoidal-input microstep control of
bipolar stepping motors. The TB6560AHQ/AFG can be used in
applications that require 2-phase, 1-2-phase, 2W1-2-phase and
4W1-2-phase excitation modes. The TB6560AHQ/AFG is capable
of low-vibration, high-performance forward and reverse driving of
a two-phase bipolar stepping motor using only a clock signal.
TB6560AHQ
Features
•
Single-chip motor driver for sinusoidal microstep control of
stepping motors
•
High output withstand voltage due to the use of BiCD process:
Ron (upper and lower sum) =
TB6560AFG
TB6560AHQ: 0.6 Ω (typ.)
TB6560AFG: 0.7 Ω (typ.)
•
Forward and reverse rotation
•
Selectable phase excitation modes (2, 1-2, 2W1-2 and 4W1-2)
•
High output withstand voltage: VDSS = 40 V
•
High output current: IOUT = TB6560AHQ: 3.5 A (peak)
TB6560AFG: 2.5 A (peak)
•
Packages: HZIP25-P-1.27
HQFP64-P-1010-0.50
•
Internal pull-down resistors on inputs: 100 kΩ (typ.)
•
Output monitor pin: MO current (IMO (max) = 1 mA)
•
Reset and enable pins
•
Thermal shutdown (TSD)
Weight
HZIP25-P-1.27: 9.86 g (typ.)
HQFP64-P-1010-0.50: 0.26 g (typ.)
*Solderability
1. Use of Sn-37Pb solder bath
*solder bath temperature = 230°C
*dipping time = 5 seconds
*number of times = once
*use of R-type flux
2. Use of Sn-3.0Ag-0.5Cu solder bath
*solder bath temperature = 245°C
*dipping time = 5 seconds
*the number of times = once
*use of R-type flux
*: These ICs are highly sensitive to electrostatic discharge. When handling them, ensure that the environment is
protected against electrostatic discharge. Ensure also that the ambient temperature and relative humidity are
maintained at reasonable level.
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TB6560AHQ/AFG
Block Diagram
VDD
Protect
20/30, 31
19/28
MO
VMA
17/23
18/25, 26
OUT_AP
M1 23/36
16/19, 20
PWM
Bridge
driver A
control
circuit
M2 22/35
13/10, 11
OUT_AM
CW/CCW 21/33
CLK
Thermal shutdown
circuit
3/45
14/13, 14
NFA
Input
circuit
RESET 5/48
ENABLE
8/55, 56 VMB
4/47
OUT_BP
DCY1 25/39
12/6, 7
PWM
Bridge
driver B
control
DCY2 24/38
circuit
9/61, 62
OSC
7/53
OUT_BM
OSC
11/2, 4
NFB
Maximum current
setting circuit
2/43
1/42
TQ1
TQ2
6/50, 51
15/16
SGND
PGNDA
10/64
PGNDB
TB6560AHQ/TB6560AFG
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TB6560AHQ/AFG
Pin Functions
Pin No.
TB6560
AHQ
TB6560
AFG
I/O
Symbol
Functional Description
Remarks
1
42
Input
TQ2
Torque setting input (current setting)
Internal pull-down
resistor
2
43
Input
TQ1
Torque setting input (current setting)
Internal pull-down
resistor
3
45
Input
CLK
Clock input for microstepping
Internal pull-down
resistor
4
47
Input
ENABLE
H: Enable; L: All outputs OFF
Internal pull-down
resistor
5
48
Input
RESET
L: Reset (The outputs are reset to their initial states.)
Internal pull-down
resistor
6
50/51
⎯
SGND
Signal ground (for control block)
7
53
⎯
OSC
A CR oscillation circuit is connected to this pin. Performs
output chopping.
(Note 1)
8
55/56
Input
VMB
Motor power supply pin (for phase-B driver)
(Note 1)
9
61/62
Output
OUT_BM
OUT_B output
(Note 1)
10
64 (*)
⎯
PGNDB
Power ground
11
2/4 (*)
⎯
NFB
Connection pin for a B-channel current sensing resistor
Two pins of the TB6560AFG should be short-circuited.
(Note 1)
12
6/7
Output
OUT_BP
OUT_B output
(Note 1)
13
10/11
Output
OUT_AM
OUT_A output
(Note 1)
14
13/14 (*)
⎯
NFA
Connection pin for an A-channel current sensing resistor
Two pins of the TB6560AFG should be short-circuited.
(Note 1)
15
16
⎯
PGNDA
16
19/20
Output
OUT_AP
Power ground
OUT_A output
(Note 1)
17
23
Output
MO
Initial state sensing output. This pin is enabled in the initial
state.
18
25/26
Input
VMA
Motor power supply pin (for phase-A driver)
19
28
Output
Protect
20
30/31
Input
VDD
Open drain
(Note 1)
When TSD is activated: High; when in normal state: High-Z.
Open drain
Power supply pin for control block
Rotation direction select input.
(Note 1)
Internal pull-down
resistor
21
33
Input
CW/CCW
22
35
Input
M2
Excitation mode setting input
Internal pull-down
resistor
23
36
Input
M1
Excitation mode setting input
Internal pull-down
resistor
24
38
Input
DCY2
Current decay mode setting input
Internal pull-down
resistor
25
39
Input
DCY1
Current decay mode setting input
Internal pull-down
resistor
L: Clockwise; H: Counterclockwise
(*): The pin assignment of the TB6560AFG is different from that of the TB6560FG.
TB6560AHQ: There is no no-connect (NC) pin.
TB6560AFG: Except the above pins, all pins are NC. The pin numbers of NC pins are: 1, 3, 5, 8, 9, 12, 15, 17, 18,
21, 22, 24, 27, 29, 32, 34, 37, 40, 41, 44, 46, 49, 52, 54, 57, 58, 59, 60, and 63.
Applying a voltage to NC pins does not cause any problem since they are not connected inside the IC.
All control input pins have an internal pull-down resistor of 100 kΩ (typ.)
Note 1: As for the TB6560AFG, two pins that have the same functionality should be short-circuited at a location as
close to the TB6560AFG as possible.
(The electrical characteristics provided in this document are measured when those pins are handled in this
manner.)
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TB6560AHQ/AFG
Equivalent Circuits
Input Pins
(M1, M2, CLK, CW/CCW, TQ1,TQ2,ENABLE,
RESET ,DCY1, DCY2)
Output Pins
(MO, Protect)
VDD
100 Ω
100 kΩ
100 Ω
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TB6560AHQ/AFG
Pin Assignment (top view)
RESET
ENABLE
(NC)
CLK
(NC)
TQ1
TQ2
(NC)
(NC)
DCY1
DCY2
(NC)
M1
M2
(NC)
CW/CCW
TB6560AFG
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
29
(NC)
OSC 53
28
Protect
(NC)
54
27
(NC)
VMB
55
26
VMA
VMB
56
25
VMA
(NC)
57
24
(NC)
(NC)
58
23
MO
(NC)
59
22
(NC)
(NC)
60
21
(NC)
OUT_BM
61
20
OUT_AP
OUT_BM
62
19
OUT_AP
(NC)
63
18
(NC)
PGNDB
64
17
(NC)
3
4
5
6
7
8
9
10
11
OUT_AM
2
OUT_BP
1
12
13
14
15
16
PGNDA
52
(NC)
(NC)
NFA
VDD
NFA
30
(NC)
51
OUT_AM
SGND
(NC)
VDD
(NC)
31
OUT_BP
50
(NC)
SGND
NFB
(NC)
(NC)
32
NFB
49
(NC)
(NC)
1
3
5
7
9
11
13
15
17
19
21
23
25
DCY1
DCY2
24
M1
M2
22
CW/CCW
VDD
20
Protect
VMA
18
MO
OUT_AP
16
PGNDA
NFA
14
OUT_AM
OUT_BP
12
NFB
PGNDB
10
OUT_BM
VMB
8
OSC
SGND
6
RESET
ENABLE
4
CLK
2
TQ2
TQ1
TB6560AHQ
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TB6560AHQ/AFG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Power supply voltage
Output current
(per phase)
TB6560AHQ
Peak
TB6560AFG
Rating
VDD
6
VMA/B
40
Unit
V
3.5
IO (PEAK)
MO drain current
Protect drain current
Symbol
A
2.5
I (MO)
1
mA
I (Protect)
1
mA
VIN
VDD
V
Input voltage
5 (Note 1)
TB6560AHQ
Power dissipation
43 (Note 2)
PD
1.7 (Note 3)
TB6560AFG
W
4.2 (Note 4)
Operating temperature
Topr
−30 to 85
°C
Storage temperature
Tstg
−55 to 150
°C
Note 1: Ta = 25°C, without heatsink.
Note 2: Ta = 25°C, with infinite heatsink (HZIP25).
Note 3: Ta = 25°C, with soldered leads.
Note 4: Ta = 25°C, when mounted on a board (4-layer board).
Operating Range (Ta = −30 to 85°C)
Characteristics
Power supply voltage
Output current
TB6560AHQ
TB6560AFG
Symbol
Test Condition
Min
Typ.
Max
Unit
VDD
⎯
4.5
5.0
5.5
V
VMA/B
VMA/B ≥ VDD
4.5
⎯
34
V
⎯
⎯
⎯
3
⎯
⎯
⎯
1.5
IOUT
A
Input voltage
VIN
⎯
0
⎯
5.5
V
Clock frequency
fCLK
⎯
⎯
⎯
15
kHz
OSC frequency
fOSC
⎯
⎯
⎯
600
kHz
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TB6560AHQ/AFG
Electrical Characteristics (Ta = 25°C, VDD = 5 V, VM = 24 V)
Characteristics
Input voltage
Symbol
VDD
−0.2
⎯
0.8
⎯
400
⎯
IIN (H)
M1, M2, CW/CCW, CLK,
RESET , ENABLE, DCY1, DCY2,
TQ1, TQ2
VIN = 5.0 V
Internal pull-down resistor
30
55
80
IIN (L)
VIN = 0 V
⎯
⎯
1
IDD1
Outputs: Open,
RESET : H, ENABLE: H
(2, 1-2 phase excitation)
⎯
3
5
IDD2
Outputs: Open,
RESET : H, ENABLE: H
(4W1−2, 2W1-2 phase excitation)
⎯
3
5
IDD3
RESET : L, ENABLE: L
⎯
2
5
IDD4
RESET : H, ENABLE: L
⎯
2
5
IM1
RESET : H/L, ENABLE: L
⎯
0.5
1
IM2
RESET : H/L, ENABLE: H
⎯
0.7
2
ΔVO
B/A, COSC = 330 μF
−5
⎯
5
VNFHH
TQ1 = H, TQ2 = H
10
20
30
VNFHL
TQ1 = L, TQ2 = H
45
50
55
VNFLH
TQ1 = H, TQ2 = L
70
75
80
VNFLL
TQ1 = L, TQ2 = L
⎯
⎯
100
VIN (L)
VDD supply current
VM supply current
Channel-to-channel voltage
differential
VNF voltage change according to
the torque settings
Max
⎯
Low
Input current
Typ.
2.0
VIN (H)
(Note)
Min
M1, M2, CW/CCW, CLK,
RESET , ENABLE, DCY1, DCY2,
TQ1, TQ2
High
Input hysteresis voltage
Test Condition
VINhys
Unit
V
mV
μA
mA
mA
%
%
Minimum clock pulse width
tW (CLK)
COSC= 330 pF
30
⎯
⎯
μs
MO output residual voltage
VOL MO
IOL = 1 mA
⎯
⎯
0.5
V
VOL Protect
IOL = 1 mA
⎯
⎯
0.5
V
Protect output rest voltage (Note)
TSD threshold
(Note)
TSD
⎯
⎯
170
⎯
°C
TSD hysteresis
(Note)
TSDhys
⎯
⎯
20
⎯
°C
COSC = 330 pF
60
130
200
kHz
Oscillating frequency
fOSC
Note: Not tested in production
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2011-01-18
TB6560AHQ/AFG
Electrical Characteristics (Ta = 25°C, VDD = 5 V, VM = 24 V)
Characteristics
Symbol
TB6560AHQ
Output ON-resistance
TB6560AFG
A-/B-phase chopping current (Note 1)
2W1-2phase
excitation
4W1-2phase
excitation
Test Condition
Ron U1H
Min
Typ.
Max
⎯
0.3
0.4
⎯
0.3
0.4
⎯
0.35
0.5
⎯
0.35
0.5
θ=0
⎯
100
⎯
IOUT = 1.5 A
Ron L1H
Ron U1F
IOUT = 1.5 A
Ron L1F
1-2phase excitation
⎯
⎯
θ = 1/16
⎯
100
⎯
2W1-2phase
excitation
⎯
θ = 2/16
93
98
100
⎯
⎯
θ = 3/16
91
96
100
2W1-2phase
excitation
⎯
θ = 4/16
87
92
97
⎯
⎯
θ = 5/16
83
88
93
2W1-2phase
excitation
⎯
θ = 6/16
78
83
88
⎯
⎯
θ = 7/16
72
77
82
66
71
76
2W1-2phase
excitation
1-2phase excitation
Vector
θ = 8/16
TQ1 = L, TQ2 = L
⎯
θ = 9/16
58
63
68
2W1-2phase
excitation
⎯
θ = 10/16
51
56
61
⎯
⎯
θ = 11/16
42
47
52
2W1-2phase
excitation
⎯
θ = 12/16
33
38
43
⎯
⎯
θ = 13/16
24
29
34
2W1-2phase
excitation
⎯
θ = 14/16
15
20
25
⎯
⎯
θ = 15/16
5
10
15
⎯
⎯
100
⎯
450
500
550
⎯
1
⎯
⎯
1
⎯
⎯
1
⎯
⎯
3
⎯
⎯
2
⎯
⎯
⎯
1
⎯
⎯
1
Reference voltage
TQ1, TQ2 = L (100 %)
OSC = 100 kHz
VNF
Output transistor switching characteristics
(Note 2)
tr
RL = 10 Ω, VNF = 0.5 V
tf
RESET to output
tpLH
Delay time
(Note 2)
tpLH
ENABLE to output
tpHL
Output leakage current
Upper side
ILH
Lower side
ILL
VM = 40 V
Ω
%
⎯
2-phase excitation
Unit
mV
μs
μA
Note 1: Relative to the peak current at θ = 0.
Note 2: Not tested in production.
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TB6560AHQ/AFG
Functional Descriptions
1. Excitation Mode Settings
The excitation mode can be selected from the following four modes using the M1 and M2 inputs. (The
2-phase excitation mode is selected by default since both M1 and M2 have internal pull-down resistors.)
Inputs
M2
M1
Mode
(Excitation)
L
L
2-phase
L
H
1-2-phase
H
L
4W1-2-phase
H
H
2W1-2-phase
2. Function Table (Relationship Between Inputs and Output Modes)
When the ENABLE pin is Low, outputs are off. When the RESET pin is Low, the outputs are put in the
Initial mode as shown in the table below. In this mode, the states of the CLK and CW/CCW pins are
don’t-cares.
Inputs
Output Mode
CW/CCW
RESET
ENABLE
L
H
H
CW
H
H
H
CCW
X
X
L
H
Initial mode
X
X
X
L
Z
CLK
X: Don’t care
3. Initial Mode
When RESET is asserted, phase currents in each excitation mode are as follows. At this time, the MO pin
goes Low (open-drain connection).
Excitation Mode
A-Phase Current
B-Phase Current
2-phase
100 %
−100 %
1-2-phase
100 %
0%
2W1-2-phase
100 %
0%
4W1-2-phase
100 %
0%
4. Decay Mode Settings
It takes approximately four OSC cycles for discharging a current in PWM mode. The 25 % decay mode is
created by inducing decay during the last cycle in Fast Decay mode; the 50 % Decay mode is created by
inducing decay during the last two cycles in Fast Decay mode; and the 100 % Decay mode is created by
inducing decay during all four cycles in Fast Decay mode.
Since the DCY1 and DCY2 pins have internal pull-down resistors, the Normal mode is selected when DCY1
and DCY2 are undriven.
DCY2
DCY1
Current Decay Setting
L
L
Normal 0 %
L
H
25 % Decay
H
L
50 % Decay
H
H
100 % Decay
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TB6560AHQ/AFG
5. Torque Settings (Current Value)
The ratio of the current necessary for actual operations to the predefined current adjusted by an external
resistor can be selected as follows. The Weak Excitation mode should be selected to set a torque extremely
low like when the motor is at a fixed position.
Since the TQ2 and TQ1 pins have pull-down resistors, the 100 % torque setting is selected when TQ2 and
TQ1 are undriven.
TQ2
TQ1
Current Ratio
L
L
100 %
L
H
75 %
H
L
50 %
H
H
20 %
(Weak excitation)
6. Calculation of the Predefined Output Current
To perform a constant current drive, the reference current should be adjusted by an external resistor.
Charging stops when the NFA (NFB) voltage reaches 0.5 V (when the torque setting is 100 %) so that a
current does not exceed the predefined level.
IOUT (A) = 0.5 (V) / RNF (Ω)
Example: To set the peak current to 1 A, the value of an external resistor should be 0.5 Ω.
7. Protect and MO Output Pins
These are open-drain outputs. An external pull-up resistor should be added to these pins when in use.
If the TSD circuit is activated, Protect is driven Low. When the IC enters the Initial state, MO is driven
Low.
Pin State
Protect
MO
Low
Thermal shutdown
Initial state
High-Z
Normal operation
Other than the initial state
Open-drain connection
Rest voltage of output terminal Mo and output terminal Protect reach 0.5 V (max) when IO is 1 mA.
8. Adjusting the External Capacitor Value (COSC) and Minimum Clock Pulse Width
(tW(CLK))
A triangular-wave is generated internally by CR oscillation. The capacitor is externally connected to the
OSC pin. The recommended capacitor value is between 100 pF and 1000 pF.
Approximate equation: fOSC = 1/{ COSC × 1.5 × (10/ COSC + 1)/66} × 1000 kHz
(Since this is an approximation formula, the calculation result may not be exactly equal to the actual
value.)
The approximate values are shown below.
The minimum clock pulse width (tW(CLK)) corresponds to the external capacitor (COSC ) as follows:
Capacitor
Oscillating Frequency
Minimum Clock Pulse Width tW(CLK) (Note 1)
1000 pF
44 kHz
90 μs (Note 2)
330 pF
130 kHz
30 μs
100 pF
400 kHz
10 μs (Note 2)
Note 1: When the frequency of an input clock signal is high, the COSC value should be small so that the duty cycle
of an input clock pulse does not become extremely high (should be around 50 % or lower).
Note 2: Not tested in production.
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TB6560AHQ/AFG
Relationship between the Enable and RESET and Output Signals
Example 1: ENABLE input in 1-2-phase excitation mode (M1: H, M2: L)
CW
CLK
ENABLE
RESET
MO voltage
(%)
100
71
IA (current from
0
OUT_AP to OUT_AM)
−71
−100
t0
t1
t2
t3
OFF
t7
t8
t9
t10
t11
t12
Setting the ENABLE signal Low disables only the output signals, while internal circuitry other than the
output block continues to operate in accordance with the CLK input. Therefore, when the ENABLE signal goes
High again, the output current generation is restarted as if phases proceeded with the CLK signal.
Example 2: RESET input in 1-2-phase excitation mode (M1: H, M2: L)
CW
CLK
ENABLE
RESET
MO voltage
(%)
100
71
IA (current from
OUT_AP to OUT_AM)
0
−71
−100
t0
t1
t2
t3
t2
t3
t4
t5
t6
t7
t8
Setting the RESET signal Low causes the outputs to be put in the Initial state and the MO output to be
driven Low (Initial state: A-channel output current is at its peak (100 %)).
When the RESET signal goes High again, the output current generation is restarted at the next rising edge
of CLK with the state following the Initial state.
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TB6560AHQ/AFG
2-Phase Excitation (M1: L, M2: L, CW Mode)
CW
CLK
MO
(%)
100
IA
0
−100
(%)
100
IB
0
−100
t0
t1
t2
t3
t4
t5
t6
t7
1-2-Phase Excitation (M1: H, M2: L, CW Mode)
CW
CLK
MO
(%)
100
71
IA
0
−71
−100
(%)
100
71
IB
0
−71
−100
t0
t1
t2
t3
t4
t5
t6
12
t7
t8
2011-01-18
TB6560AHQ/AFG
2W1-2-Phase Excitation (M1: H, M2: H, CW Mode)
CW
CLK
MO
(%)
100
98
92
83
71
56
38
20
IA
0
−20
−38
−56
−71
−83
−92
−98
−100
(%)
100
98
92
83
71
56
38
20
IB
0
−20
−38
−56
−71
−83
−92
−98
−100
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32
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TB6560AHQ/AFG
4W1-2-Phase Excitation (M1: L, M2: H, CW Mode)
[%]
100
98
96
92
88
83
77
71
63
56
47
38
A-phase
B-phase
29
20
10
0
−10
−20
−29
−38
−47
−56
−63
−71
−77
−83
−88
−92
−96
−98
−100
STEP
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TB6560AHQ/AFG
CK
MO
M1
M2
RESET
(%)
100
91
71.4
40
IA
0
−40
−71.4
−91
−100
1-2-phase excitation
Other excitation
It is recommended that the state of the M1 and M2 pins be changed after setting the RESET signal Low
during the Initial state (MO = Low). Even when the MO signal is Low, changing the M1 and M2 signals without
setting the RESET signal Low may cause a discontinuity in the current waveform.
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TB6560AHQ/AFG
9. Current Waveforms and Mixed Decay Mode Settings
The current decay rate of the Decay mode operation can be determined by the DCY1 and DCY2 inputs for
constant-current control.
The “NF” refers to the point at which the output current reaches its predefined current level, and the
“RNF” refers to the monitoring timing of the predefined current.
The smaller the MDT value, the smaller the current ripple amplitude. However, the current decay rate
decreases.
fchop
OSC Pin
Internal
Waveform
Predefined Current Level
Normal
Mode
NF
RNF
Charge mode → NF: Predefined current level → Slow mode →
Current monitoring → (When predefined current level > Output
current) Charge mode
Predefined Current Level
25 %
Decay
Mode
NF
MDT
RNF
Charge mode → NF: Predefined current level → Slow mode →
Mixed decay timing → Fast mode → Current monitoring → (When
predefined current level > Output current) Charge mode
Predefined Current Level
50 %
Decay
Mode
NF
MDT
Charge mode → NF: Predefined current level → Slow mode →
Mixed decay timing → Fast mode → Current monitoring → (When
predefined current level > Output current) Charge mode
RNF
Predefined Current Level
100 %
Decay
Mode
NF
Charge mode → NF: Predefined current level → Fast mode →
Current monitoring → (When predefined current level > Output
current) Charge mode
RNF
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TB6560AHQ/AFG
10. Current Control Modes (Effects of Decay Modes)
•
Increasing the current (sine wave)
Slow
Slow
Predefined
Current Level
Fast
Slow
Predefined
Current Level
•
Charge
Slow
Fast
Charge
Charge
Fast
Charge
Fast
Decreasing the current with a high decay rate (The current decay rate in Mixed Decay mode is the ratio
between the time in Fast-Decay mode (discharge time after MDT) and the remainder of the period.)
Slow
Slow
Predefined
Current Level
Since the current decays quickly, it can be
decreased to the predefined value in a short time.
Charge
Charge
Fast
Fast
Slow
Slow
Predefined
Current Level
Fast
•
Charge
Fast
Decreasing the current with a low decay rate (The current decay rate in Mixed Decay mode is the ratio
between the time in Fast-Decay mode (discharge time after MDT) and the remainder of the period.)
Since the current decays slowly, decreasing the current
to the predefined value takes a long time (or the current
cannot be properly decreased to the predefined value).
Slow
Slow
Predefined
Current Level
Fast
Charge
Charge
Fast
Slow
Fast
Slow
Fast
Predefined
Current Level
During Mixed Decay and Fast Decay modes, if the predefined current level is less than the output
current at the RNF (current monitoring point), the Charge mode in the next chopping cycle will
disappear (though the current control mode is briefly switched to Charge mode in actual operations for
current sensing) and the current is controlled in Slow and Fast Decay modes (mode switching from Slow
Decay mode to Fast Decay mode at the MDT point).
Note: The above figures are rough illustration of the output current. In actual current waveforms, transient response
curves can be observed.
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TB6560AHQ/AFG
11. Current Waveforms in Mixed Decay Mode
fchop
fchop
OSC Pin
Internal
Waveform
IOUT
Predefined
Current Level
Predefined
Current Level
NF
NF
25 % Mixed
Decay Mode
RNF
MDT (Mixed Decay Timing) Points
•
When the NF points come after Mixed Decay Timing points
Switches to Fast mode after Charge mode
fchop
fchop
IOUT
Predefined Current Level
NF
MDT (Mixed Decay Timing) Points
RNF
Predefined
Current Level
NF
25 % Mixed
Decay Mode
RNF
CLK Signal Input
•
When the output current value > predefined current level in Mixed Decay mode
fchop
fchop
Predefined
Current Level
fchop
NF
IOUT
RNF
NF
Predefined
Current Level
25 % Mixed
Decay Mode
RNF
MDT (Mixed Decay Timing) Points
CLK Signal Input
*: Even if the output current rises above the predefined current at the RNF point, the current control mode is briefly
switched to Charge mode for current sensing.
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TB6560AHQ/AFG
12. Current Waveform in Fast Decay Mode
After the output current to the load reaches the current value specified by RNF, torque or other means, the
output current to the load will be fed back to the power supply fully in Fast Decay mode.
fchop
Predefined
Current Level
IOUT
Switches to Charge mode briefly
Fast Decay
Mode (100 %
Decay Mode)
RNF
Predefined Current Level
NF
RNF
Since the predefined current level > output
current, current control mode is switched
from Charge mode → NF → Fast Decay
mode even in the next chopping cycle.
RNF
CLK Signal Input
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TB6560AHQ/AFG
13. CLK and Internal OSC Signals and Output Current Waveform
(when the CLK signal is asserted during Slow Decay mode)
25 % Mixed Decay Mode
fchop
fchop
fchop
OSC Pin Internal
Waveform
Predefined
Current Level
NF
IOUT
MDT
NF
Predefined
Current Level
RNF
MDT
RNF
Switches to Charge mode briefly
CLK Signal Input
The OSC counter is reset here.
When the CLK signal is asserted, the Chopping Counter (OSC Counter) is forced to reset at the next rising
edge of the OSC signal.
As a result, the response to input data is faster compared to methods in which the counter is not reset.
The delay time that is theoretically determined by the logic circuit is one OSC cycle = 10 μs at a 100-kHz
chopping rate.
After the OSC Counter is reset by the CLK signal input, the current control mode is invariably switched to
Charge mode briefly for current sensing.
Note: Even in Fast Decay mode, the current control mode is invariably switched to Charge mode briefly for
current sensing.
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TB6560AHQ/AFG
14. CLK and Internal OSC Signals and Output Current Waveform
(when the CLK signal is asserted during Charge mode)
25 % Mixed Decay Mode
fchop
fchop
fchop
OSC Pin Internal
Waveform
Predefined
Current Level
MDT
NF
Predefined
Current Level
MDT
IOUT
RNF
RNF
Switches to Charge mode briefly
CLK Signal Input
The OSC Counter is reset here.
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15. CLK and Internal OSC Signals and Output Current Waveform
(when the CLK signal is asserted during Fast Decay mode)
25 % Mixed Decay Mode
fchop
fchop
fchop
OSC Pin Internal
Waveform
Predefined
Current Level
IOUT
NF
MDT
NF
Predefined
Current Level
MDT
RNF
RNF
Switches to Charge mode briefly
CLK Signal Input
The OSC Counter is reset here.
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TB6560AHQ/AFG
16. Internal OSC Signal and Output Current Waveform when Predefined Current is
Changed from Positive to Negative
(when the CLK signal is input using 2-phase excitation)
25% Mixed Decay Mode
fchop
fchop
fchop
Predefined
Current Level
IOUT
0
RNF
RNF
Predefined
Current Level
NF
MDT
NF
CLK Signal Input
The OSC Counter is reset here.
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TB6560AHQ/AFG
Current Discharge Path when ENABLE is Set as Low During Operation
When all the output transistors are forced off during Slow Decay mode, the coil energy is discharged in the
following modes:
Note: Parasitic diodes are located on dotted lines. However, they are not normally used in normal Mixed Decay
mode.
VM
VM
U1
ON
Note
U2
U1
OFF
OFF
VM
Note
Load
ON
ON
L1
L2
L1
RNF
Charge Mode
OFF
OFF
L2
ON
RNF
PGND
U1
ENABLE is set as low
Load
OFF
U2
U2
OFF
Note
Load
L1
L2
OFF
OFF
RNF
PGND
Slow Mode
PGND
Forced OFF Mode
As shown in the figure above, output transistors have parasitic diodes.
Normally, when the energy of the coil is discharged, each transistor is turned on allowing the current to flow in
the reverse direction to that in normal operation; as a result, the parasitic diodes are not used. However, when all
the output transistors are forced off, the coil energy is discharged via the parasitic diodes.
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TB6560AHQ/AFG
Output Transistor Operating Modes
VM
VM
U1
U2
U1
OFF
OFF
OFF
ON
ON
L1
L2
L1
ON
Note
VM
Note
Load
U2
U1
OFF
OFF
Load
ON
L1
OFF
RNF
PGND
Charge Mode
L2
ON
RNF
PGND
ON
Note
Load
L2
RNF
U2
PGND
Slow Mode
Fast Mode
Output Transistor Operating Modes
CLK
U1
U2
L1
L2
Charge
ON
OFF
OFF
ON
Slow Decay
OFF
OFF
ON
ON
Fast Decay
OFF
ON
ON
OFF
Note: This table shows an example of when the current flows as indicated by the arrows in the above figures. If the
current flows in the opposite direction, refer to the following table:
CLK
U1
U2
L1
L2
Charge
OFF
ON
ON
OFF
Slow Decay
OFF
OFF
ON
ON
Fast Decay
ON
OFF
OFF
ON
Upon transitions of above-mentioned modes, a dead time of about 300 ns is inserted between each mode
respectively.
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TB6560AHQ/AFG
Test Points for AC Specifications
CLK
tCLK
tCLK
tpLH
VM
90%
tpHL
50%
GND
90%
50%
10%
10%
tr
tf
Figure 1 Timing Waveforms and Symbols
OSC-Charge DELAY:
The OSC waveform is converted into the internal OSC waveform by checking the level of a chopping wave.
The internal OSC signal is designed to be logic High when the OSC voltage is at 2 V or above, and to be logic
Low when the OSC voltage is at 0.5 V or below. However, there is a response delay and that there occurs a
peak-to-peak voltage variation.
2V
OSC
Waveform
0.5 V
OSC Pin
Internal
Waveform
Figure 2 Timing Waveforms (OSC Signal)
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TB6560AHQ/AFG
Power Dissipation
TB6560AHQ
TB6560AFG
PD - Ta
Power dissipation PD (W)
①With soldered leads.
②When mounted on a board (4-layer board)
Ambient temperature Ta (℃)
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TB6560AHQ/AFG
1. Power-on Sequence with Control Input Signals
Turn on VDD. Then, when the VDD voltage has stabilized, turn on VMA/B.
Hold the control input pins Low while turning on VDD and VMA/B.
(All the control input pins are internally pulled down.)
After VDD and VMA/B completely stabilizes at the rated voltages, the RESET and ENABLE pins can be
set High. If this sequence is not properly followed, the IC may not operate correctly, or the IC and the
peripheral parts may be damaged.
When RESET is released High, the CLK signal is applied and excitation is started. Only after ENABLE
is also set High, outputs are enabled. When only RESET is set High, outputs are disabled and only the
internal counter advances. Likewise, when only ENABLE is set High, the excitation will not be performed
even if the CLK signal is applied and the outputs will remain in the initial state.
An example of a control input sequence is shown below.
A power-off sequence should be the reverse of this sequence.
CLK
RESET
ENABLE
OUT
H
L
H
L
H
Z
L
Output
Internal current setting
Output current setting
Z
Internal current setting: Disabled;
Output OFF
Internal current setting: Enabled
2. Power Dissipation
The power dissipation of the IC can be calculated by the following equation:
P = VDD × IDD + IOUT × IOUT × Ron × 2 phases
The higher the ambient temperature, the smaller the power dissipation.
Examine the PD-Ta characteristic curve to determine if there is a sufficient margin in the thermal design.
3. Treatment of Heat-Radiating Fin
The heat-radiating fin pins of the TB6560AHQ/AFG (backside) are electrically connected to the backside of
the die. Thus, if a current flows to the fin, the IC may malfunction. If there is any possibility of a voltage
being generated between grounds and the fin, the fin pins should either be connected to ground or
insulated.
4. Thermal Shutdown (TSD)
When the die temperature reaches 170°C (typ.), the thermal shutdown circuit is tripped, switching the
outputs to off. There is a variation of about ±20°C in the temperature at which the thermal shutdown
circuit is tripped.
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TB6560AHQ/AFG
Application Circuit Example
Fuse
5 V
10 μF
1 μF
VDD
CLK
VMA
24 V
VMB
OUT_AP
RESET
ENABLE
1 μF
47 μF
H-SW A
OUT_AM
Logic
PWM control
circuit
M1
NFCompA
M2
OUT_BP
M
H-SW B
MCU
or
External
input
CW/CCW
DCY1
OUT_BM
Current
control
NFA
PWM control
circuit
DCY2
RNFA
NFCompB
TQ1
TQ2
NFB
Protect
RNFB
MO
R1
R2
OSC
100 pF ≈ 400 kHz
SGND
PGND
0.5 Ω: IOUT (max) = 1.0 A
Note: Capacitors for the power supply lines should be connected as close to the IC as possible.
Usage Considerations
• A large current might abruptly flow through the IC in case of a short-circuit across its outputs, a short-circuit
to power supply or a short-circuit to ground, leading to a damage of the IC. Also, the IC or peripheral parts
may be permanently damaged or emit smoke or fire resulting in injury especially if a power supply pin
(VDD, VMA, VMB) or an output pin (OUT_AP, OUT_AM, OUT_BP, OUT_BM) is short-circuited to adjacent
or any other pins. These possibilities should be fully considered in the design of the output, VDD, VM, and
ground lines.
• A fuse should be connected to the power supply line. The rated maximum current of the TB6560AHQ is
3.5 A/phase and that of the TB6560AFG is 2.5 A/phase. Considering those maximum ratings, an
appropriate fuse must be selected depending on operating conditions of a motor to be used. Toshiba
recommends that a fast-blow fuse be used.
• The power-on sequence described on page 28 must be properly followed.
• If a voltage outside the operating range specified on page 6 (4.5 ≤ VDD ≤ 5.5, 4.5 ≤ VMA/B ≤ 34,
VDD ≤ VMA/B) is applied, the IC may not operate properly or the IC and peripheral parts may be
permanently damaged. Ensure that the voltage range does not exceed the upper and lower limits of the
specified range.
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TB6560AHQ/AFG
Package Dimensions
Weight: 9.86 g (typ.)
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TB6560AHQ/AFG
Package Dimensions
Weight: 0.26 g (typ.)
Note: The size of a backside heatsink is 5.5 mm × 5.5 mm.
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough
evaluation is required, especially at the mass production design stage.
Toshiba does not grant any license to any industrial property rights by providing these examples of
application circuits.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
IC Usage Considerations
Notes on Handling of ICs
(1)
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
(2)
Use an appropriate power supply fuse to ensure that a large current does not continuously flow in
case of over current and/or IC failure. The IC will fully break down when used under conditions that
exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal
pulse noise occurs from the wiring or load, causing a large current to continuously flow and the
breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of
breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are
required.
(3)
If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current resulting from the inrush
current at power ON or the negative current resulting from the back electromotive force at power OFF.
IC breakdown may cause injury, smoke or ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable,
the protection function may not operate, causing IC breakdown. IC breakdown may cause injury,
smoke or ignition.
(4)
Do not insert devices in the wrong orientation or incorrectly.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and
exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
In addition, do not use any device that is applied the current with inserting in the wrong orientation
or incorrectly even just one time.
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Points to Remember on Handling of ICs
(1)
Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal
shutdown circuits operate against the over temperature, clear the heat generation status
immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings
can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation.
(2)
Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the
device so that heat is appropriately radiated, not to exceed the specified junction temperature (TJ) at
any time and condition. These ICs generate heat even during normal use. An inadequate IC heat
radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In
addition, please design the device taking into considerate the effect of IC heat radiation with
peripheral components.
(3)
Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to
the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power
supply is small, the device’s motor power supply and output pins might be exposed to conditions
beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in
system design.
(4)
Short-Circuits
The IC may be permanently damaged in case of a short-circuit across its outputs, a short-circuit to
power supply or a short-circuit to ground. These possibilities should be fully considered in the design
of the output, VDD, VM and ground lines.
(5)
Short-Circuits between Adjacent Pins in the TB6560AHQ
In the TB6560AHQ, the term “adjacent pin” includes a pin diagonally closest to a given pin. For
example, pin 3 has four adjacent pins: 1, 2, 4 and 5.
Depending on the specified voltage and current, a large current might abruptly flow through the
TB6560AHQ in case of a short-circuit between any adjacent pins that are listed below. If the large
current persists, it may lead to a smoke emission.
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
16)
17)
18)
19)
Pins 7 and 8
Pins 7 and 9
Pins 8 and 9
Pins 9 and 10
Pins 9 and 11
Pins 10 and 12
Pins 11 and 12
Pins 11 and 13
Pins 12 and 13
Pins 12 and 14
Pins 13 and 14
Pins 13 and 15
Pins 14 and 16
Pins 15 and 16
Pins 16 and 17
Pins 16 and 18
Pins 17 and 18
Pins 18 and 19
Pins 18 and 20
Therefore, to avoid a continuous overcurrent due to the above-described short-circuit and allow the
TB6560AHQ/AFG to be fail-safe, an appropriate fuse should be added at the right place, or
overcurrent shutdown circuitry should be added to the power supply. The rated current of a fuse may
vary depending on actual applications and its characteristics. Thus, an appropriate fuse must be
selected experimentally.
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RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product’s quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the “TOSHIBA Semiconductor Reliability Handbook” and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR
APPLICATIONS.
• Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or
reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious
public impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used
in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling
equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric
power, and equipment used in finance-related fields. Do not use Product for Unintended Use unless specifically permitted in this
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• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
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• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
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FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
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or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
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