TB6596FLG,EL

TB6596FLG TOSHIBA BiCD Integrated Circuit Silicon Monolithic TB6596FLG DC and Stepping Motor Driver IC The TB6596FLG is a DC motor driver IC using LDMOS output transistors with low ON-resistance. The TB6596FLG incorporates one PWM-constant-current H-bridge driver, four direct-PWM-controlled H-bridge drivers, and also one linear constant-current H-bridge driver. The TB6596FLG is best suited to control various lens actuators in digital still cameras. The three-wire serial interface provides control over the drivers, thus reducing the number of lines required for interfacing with the control IC. Weight: 0.08 g (typ.) Features • Motor power supply voltage: VM ≤ 6 V (max) • Control power supply voltage: VCC = 3 to 6 V • Output current: IOUT ≤ 0.8 A (max) • Complementary P- and N-channel LDMOS output transistors • Output ON-resistance: Ron (upper and lower sum) = 1.5 Ω (typ.) Channel E: DC Motor Driver • High-speed PWM control at several hundred kHz • Motor control method can be selected from the following two with the serial data inputs: • 1. Controls motor speed by using both a frequency-locked-loop (FLL) speed discriminator that compares the FG and CLK signals, and an integrator. (Typical speed = Between 250 Hz and 1750 Hz in 16 steps.) 2. Controls H-bridge by using a direct PWM input. Two power switching transistors for optical encoder Channel A and B or Channel C and D: Stepping Motor Driver • Four H-bridge drivers (channel A and B, channel C and D) for direct PWM control. (Capable of controlling up to two 2-phase bipolar stepping motors or four DC motors.) Channel F: Shutter Driver • Linear constant-current drivers • Current ramp-up rate control for improving the dependency of a current ramp-up slope on supply voltage change at startup and also for improving its reproducibility. (Increases current in up to 32 steps by using the internal CLK, which is derived by dividing CLK by 1 to 16.) Other Features • Two 6-bit DACs provide reference values for each constant-current limiters • Dedicated standby (power-save) pin • Thermal shutdown (TSD): Disables the output bias generator when the internal junction temperature exceeds 170°C. • Undervoltage lockout (UVLO): Resets and disables the internal circuitry when VCC falls below 2.2 V (typ.) • Small QON-36 package (0.5-mm lead pitch) • Compatible with Pb-free reflow soldering 1 2008-01-29 TB6596FLG Note: This product has a MOS structure and is sensitive to electrostatic discharge. When handling this product, ensure that the environment is protected against electrostatic discharge by using an earth strap, a conductive mat and an ionizer. Ensure also that the ambient temperature and relative humidity are maintained at reasonable levels. About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux 2 2008-01-29 TB6596FLG Block Diagram GND STBY 26 10 PIB1 4 VCC 6 PWMD PWMC PWMB PWMA AGND 19 18 36 1 22 PIB2 5 Standby UVLO (2.2 V) Protocol-independent switch (P/I SW) Logic 3 VM1 Predriver CK 23 DATA 24 LD 25 VCC Serial decoder + Address selector + Weight register H-Bridge A 34 PGND1 Predriver H-Bridge B 33 BO1 32 BO2 8 VM2 Predriver H-Bridge C FGIN 27 Speed discriminator 250 to 1750 Hz 16 levels/100 Hz 2 AO1 35 AO2 Charge pump ±10 to ±80 µA (8 steps) 11 CO2 12 PGND2 VCC Band gap Predriver DVO 21 Triangular wave generator 20, 40, 60, 80 kHz 9 CO1 Vref (0.3 V) PWM Start/stop control H-Bridge D 13 DO1 14 DO2 TSD 20 VM3 High-side switch E (H-SW E) control 6-bit DAC3 Predriver H-Bridge E H-SW F control PWMF 28 6-bit DAC4 29 EO2 PWM timer 30 RFE 1/N CLK 7 31 EO1 Predriver H-Bridge F (Linear) 15 FO1 17 FO2 Slope control (32 steps) 16 RFF 1/1 to 1/16 3 2008-01-29 TB6596FLG Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Supply voltage VCC 6 V VCC Motor supply voltage VM 6 V VM VOUT 6 V IOUT 0.8 ID 0.1 VIN −0.2 to 6 Output voltage H-SW Output current PI SW Tr. Input voltage Power dissipation Remarks A PIB1, PIB2 0.6 PD V W Control input pins IC only 1.04 (Note) Operating temperature Topr −20 to 85 °C Storage temperature Tstg −55 to 150 °C Note: When mounted on a glass epoxy single-sided PCB (size: 50 mm × 50 mm × 1.6 mm) with a 40% dissipating copper surface. Operating Ranges (Ta = −20 to 85°C) Characteristics Rating Symbol Unit Min Typ. Max 5.5 V V Supply voltage for small-signal circuitry VCC 3 3.3 Motor supply voltage VM 2.2 3.3 5.5 ⎯ ⎯ 600 ⎯ ⎯ 350 H-SW Output current IOUT VM = 3 to 5.5 V mA ID ⎯ ⎯ 30 PWM frequency (Channels A to E) fPWM ⎯ ⎯ 100 kHz CLK driver frequency fCLK ⎯ 1 5 MHz PI SW Transistors 4 Remarks 2.2 V ≤ VM < 3 V 2008-01-29 TB6596FLG Operating Ranges: Serial Data Controller (Ta = −20 to 85°C) Characteristics Rating Symbol Unit Min Max ⎯ ns Clock pulse width Low tCKL 200 Clock pulse width High tCKH 200 ⎯ ns Clock rise time tCr ⎯ 50 ns Clock fall time tCf ⎯ 50 ns Data setup time tDCH 30 ⎯ ns Data hold time tCHD 60 ⎯ ns CK to LD rising edge tCHL 200 ⎯ ns LD to PWM delay tLDC2 100 ⎯ ns Load pulse width High tLDH 2 ⎯ µs CK (clock pulse) frequency fCLK ⎯ 2.5 MHz tCr tCKH tCf CK tCKL tCHD DATA tDCH tCHL tLDH LD Latch tLDC2 PWM 5 2008-01-29 TB6596FLG Principle of Operation Bridge Outputs: Basic operation of channels A through E PWM Control In PWM constant-current mode, the PWM chopper circuit alternates between on (t1, t5) and short brake (t3). (To eliminate shoot-through current, a dead time (t2, t4) is inserted when the PWM is turned on and off.) OUT1 M OUT2 M OUT1 OUT2 GND GND t3 VM M OUT2 GND t2 t1 OUT1 M OUT1 VM OUT2 OUT1 M GND OUT2 GND t4 t5 VM t1 t5 Output voltage waveform (OUT1) t3 GND t2 t4 6 2008-01-29 TB6596FLG Constant-Current Bridge Driver (Channel E): PWM constant-current choppers The TB6596FLG has PWM choppers with a constant turn-off period. The turn-off period is measured by counting the number of rising edges of an internal clock signal, which is generated by dividing the external CLK signal. The turn-off period can be adjusted by changing either the CLK frequency or the number of its rising edges counted (three or five counts; the default is five counts). Turning on the power supply causes a current to flow into the motor coils. The peak current through the winding is sensed via an external current-sensing resistor. As the current increases, a voltage (VRF) develops across the resistor, which is fed back to the internal comparator. At the predetermined reference voltage (Vlimit: current limiting voltage), the comparator turns off (chops) the power supply. When high-side output transistors are turned off, the TB6596FLG, by default, counts five rising edges of the internal clock signal as a turn-off period. (The counter resets at the sixth rising edge of the clock.) Based on this turn-off period, the TB6596FLG generates a PWM signal that turns on and off the output transistors. Timing Diagram of the PWM Constant-Current Chopper Circuit with the Default Turn-Off Period 1 2 3 4 5 6 Counts 5 rising edges of internal clock Internal clock Off timer (5-bit counter) Generated PWM signal Vlimit Coil current VRF on off on Power on off on off on Power off (The upper limit of the coil current (IO peak) can be calculated as: IO = Vlimit/RNF.) 7 2008-01-29 TB6596FLG Linear Constant-Current Bridge: Channel F This bridge driver circuit is tuned on and off by setting the PEMF pin High and Low, respectively. The driver output current is converted to a voltage through the external resistor RFF and fed back to a sense amplifier, thus creating a negative feedback loop. This enables the constant-current drive using the low-side driver. The constant-current value is adjusted by changing the Vref input to the sense amplifier, which is specified by an internal 6-bit DAC (max = 0.3 V). Power on Power off PWMF VM O1 O2 0V Current limit Operating current IOUT Slope (32 steps) External CLK CLK divider 1/1 to 1/16 VM 32-step counter OFF Vref 6-bit DAC ON O2 O1 ON OFF IOUT RFF 5-bit DAC (32 steps) *Current ramp-up rate controller: To improve the dependency of a current ramp-up slope on supply voltage change at startup and its reproducibility according to the time constant of the coil, the reference voltage for the comparator is increased using a 5-bit DAC (in 32 steps) up to the current limit. This can stabilize the reproducibility of a current ramp-up slope. The current ramp-up rate is specified by dividing an external CLK. The frequency divider ratio can be selected from 16 options (1/1 to 1/16) by using 4-bit serial data inputs. 8 2008-01-29 TB6596FLG Speed Control External CLK FG signal Speed Discriminator Comparison reference speed = 250 to 1750 (Hz) (16 levels in 100-Hz steps) Charge pump variable gain PWM control amp DVO Integrator • The FLL speed discriminator compares the FG signal against the reference speed which is derived from an external CLK. • The speed discriminator has two counters that alternately count one cycle of the FG signal. It then generates error pulses (charge and discharge) according to the frequency difference. Based on these pulses, the integrator (set by an external RC) and the PWM control amplifier generates a motor drive output signal to control the motor rotational speed. • The reference speed of the speed discriminator is selectable from 16 levels between 250 and 1750 Hz in 100-Hz steps. (It is selected by serial data inputs.) • The motor rotation speed (N) is calculated by the following equation: N (rpm) = fCLK (Hz)/CT × 60/Z Z: Number of FG pulses per rotor rotation CT: Speed discriminator count FG Counter 1 Counter 2 Charge pump DVO 9 2008-01-29 TB6596FLG Charge Pump Circuit VCC VCC I1 DVO Charge signal To control amp Integrator Speed discriminator Discharge signal I1 • Consisting of CMOS transistors, this charge pump achieves a high resolution of the speed control signal. • The gain of the speed discriminator can be internally selected from eight combinations of charging and discharging current values (±10 to 80 µA). And the total control gain is determined by adjusting the charge pump current and the time constant of the external integrator. • When the motor is not rotating, this circuit remains in discharge mode (−50 µA). Thus, the amount of charge stored in a capacitor of the external integrator becomes zero resetting the analog control value. • Since the FG signal is not generated immediately after the PWME drive signal assertion due to the stationary motor, the speed control loop is not enabled at this time. Therefore, the forced commutation signal (Duty cycle = 100%) is applied as a motor driving signal for a short period of time from the rising edge of the PWME signal. • * The motor startup time can be selected from 64 options (0 to 63) in 2.048-ms steps by a 6-bit serial command. For powering off, the motor operation of a certain period of time after the falling edge of the PWM signal can be selected from the brake and the reverse-plus-brake modes. * The reverse rotation time can be selected from 64 options (0 to 63) in 2.048-ms steps by a 6-bit serial command. Input Pins: All input pins (CK, DATA, LD, PWME, PWMF, STBY, CLK) have a pull-down resistor of about 200 kΩ. The FGIN pin is pulled up to VCC via a pull-up resistor of about 200 kΩ. CK, DATA, LD, PWMA, B, C, D, PWMF, STBY, CLK VCC Input 200 kΩ GND 10 2008-01-29 TB6596FLG Serial Data Format 10-Bit Serial Data CK DATA LD Latch Last First D0 D1 D2 D3 D4 D5 D6 D7 Data D8 D9 Selector Each Resister Mode D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address 0 0 0 0 p2a p2b p1a p1b ⎯ ⎯ 0 0 0 0 1 mod2 mod1 pm2 pm1 ⎯ ⎯ 1 0 0 1 0 p4a p4b p3a p3b ⎯ ⎯ 2 0 0 1 1 mod4 mod3 pm4 pm3 ⎯ ⎯ 3 0 1 0 0 Reverse brake time(0 to 127 ms) 0 1 0 1 p5a p5b vc 0 1 1 0 mod5 pm5 If5 0 1 1 1 pms 4 sw2 sw1 Charge pump gain (3 bits) Target speed value (4 bits) Carrier frequency 5 6 7 1 0 0 0 Forced commutation time for startup (0 to 127 ms) 8 1 0 0 1 DA5 (6 bits): Sets the current level for channel E 9 1 0 1 0 p6a p6b mod6 pm6 Constant-current ramp-up rate (4 bits) If6 ⎯ ⎯ ⎯ 10 1 0 1 1 1 1 0 0 1 1 0 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 13 1 1 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 14 1 1 1 1 ⎯ ⎯ ⎯ off ⎯ ⎯ 15 DA6 (6 bits): Sets the current level for channel F 11 12 Ifx: Current control for channels E and F (0 = Enable; 1 = Disable) Pms: Channel switching of the PMW input (0 = channel E; 1 = channel F) Off: Chop-off count (0 = 5 internal clock cycles, 1 = 3 internal clock cycles) Swx: Turns on/off SW1 and SW2 (0 = off; 1 = on) Vc: Channel E control mode (0 = External PWM control; 1 = Internal FLL speed control) Reverse brake: Sets the reverse brake time to be 2.048 ms × specified value Forced commutation time for startup: Full drive for a period of 2.048 ms × specified value after startup Charge pump gain: These 3 bits specify the gain of the charge pump to one of the 8 levels between ±10 µA to ±80 µA in 10-µA steps. Career frequency: These 2 bits specify the triangular wave frequency to one of the frequencies: 20 kHz, 40 kHz, 60 kHz and 80 kHz. Speed target: These 4 bits specify the speed target value to any of the 16 speed between 250 Hz to 1750 Hz in 100-Hz steps. Constant-current ramp-up rate: Controls the current ramp-up slope for channel F by changing the number of 11 2008-01-29 TB6596FLG internal clock cycle count. (0 to 15 cycles: Steps up the DAC output voltage at every specified count.) (*) Address 15 setting (1) All register data are cleared (set to “0”) if user set all “0” at address 15. Avoid the setting all”0” at the address ,or set at other address after setting at address 15. (Chop-off count should be 5 clock cycles in default state means even without setting at this.) (2) D1 and D0 in address 15 are forbidden area. Avoid setting “1” at D1 and D0. Driver Operating Modes modx = 0, pmx = 0 pxa pxb PMx OUTxA OUTxB Driving Mode 0 0 X Z Z Stop 0 1 L L L Short brake 0 1 H L H Reverse 1 0 L L L Short brake 1 0 H H L Forward 1 1 X L L Short brake modx = 0, pmx = 1 pxa pxb PMx OUTxA OUTxB Driving Mode 0 0 X Z Z Stop 0 1 L L H Reverse 0 1 H L L Short brake 1 0 L H L Forward 1 0 H L L Short brake 1 1 X L L Short brake modx = 1, pmx = X pxa pxb PMx OUTxA OUTxB Driving Mode 0 X X Z Z STOP 1 0 L H L Forward 1 0 H L H Reverse 1 1 X L L Short brake Note: Only valid for channel E. (Reverse brake function) • When short brake mode is selected, the motor operation is controlled in the following sequence. Reverse brake → Short brake • The reverse brake time is specified by serial data. (When Reverse brake time = 0, the TB6596FLG does not enter Reverse brake mode.) • During the reverse brake operation, the operating mode cannot be changed. • When the PMx input changes during the short brake operation at modx = 0, the operating mode changes according to the spxa and pxb inputs as shown in the above table. (Direct PWM control) 12 2008-01-29 TB6596FLG Electrical Characteristics (unless otherwise specified, VCC = 3.3 V, VM = 5 V, Ta = 25°C) Characteristics Symbol Min Typ. Max Unit ⎯ 1 2.5 mA ⎯ 0.1 10 IM (STB) ⎯ 0 1 VINH VCC − 0.8 ⎯ VCC + 0.2 VINL −0.2 ⎯ 0.4 ICC Supply current Serial, STBY, PWM and CLK inputs ICC (STB) Input voltage Input current Input voltage FG input Input current Output saturation voltage (Channels A to F) VIH = 3 V 10 15 20 VIL = 0 V ⎯ ⎯ 1 VINHFG VCC − 0.8 ⎯ VCC + 0.2 VINLFG −0.2 ⎯ 0.4 IINSH VIH = 3 V ⎯ ⎯ 1 IINSL VIL = 0 V −20 −15 −10 IO = 0.2 A ⎯ 0.3 0.4 IO = 0.6 A ⎯ 0.9 1.2 ⎯ ⎯ 1 ⎯ ⎯ 1 ⎯ 1 ⎯ ⎯ 1 ⎯ −10 ⎯ 10 ⎯ 10 ⎯ ⎯ 80 ⎯ IL (L) VF (U) VF (L) Offset voltage for constant-current detection comparator Charge current Charge pump Discharge current 6-bit DAC P/I SW Transistors Speed control Comp ofs VM = 6 V IF = 0.6 A (Design value) RRF = 1 Ω, Vref = 0.1 V (including DAC) ICHG Min Max ICHG Max Step ICHG step ⎯ 10 ⎯ Min IDIS Min ⎯ −10 ⎯ Max IDIS Max Step IDIS step Nonlinearity LB VDO = 1 V (Design target only) VDO = 2 V (Design target only) Channels E and F µA V µA V µA V Min ⎯ −80 ⎯ ⎯ −10 ⎯ −3 ⎯ 3 −2 ⎯ 2 µA V mV µA LSB Differential linearity error DLB Output saturation voltage Vsat ID = 20 mA ⎯ ⎯ 0.1 V Output leakage current IDSS VDS = 6 V ⎯ ⎯ 1 µA ⎯ 250 ⎯ Minimum speed FLL Min Maximum speed FLL Max ⎯ 1750 ⎯ Speed step FLL step ⎯ 100 ⎯ Ftrig Min ⎯ 17 ⎯ Minimum speed Triangular wave Maximum speed carrier Speed step Start/Reverse Standby mode (STBY = 0 V) IINL IL (U) Output diode forward voltage All 6 channels in Forward mode IINH Vsat (U + L) Output leakage current (Channels A to F) Test Condition (Design target only) ⎯ 68 ⎯ Ftrig step ⎯ 17 ⎯ Minimum control time Tmin ⎯ 0 ⎯ Maximum control time Tmax ⎯ 129 ⎯ Control time step T step ⎯ 2.048 ⎯ TSD ⎯ 170 ⎯ ⎯ 20 ⎯ Thermal shutdown threshold Thermal shutdown hysteresis Ftrig Max ∆TSD (Design target only) (Design target only) (Design target only) 13 Hz kHz ms °C 2008-01-29 TB6596FLG C2: 0.1 µF GND 26 10 STBY 6 PIB1 4 VCC PWMD PWMC PWMB PWMA AGND 19 18 36 1 22 PIB2 5 STANBY Predriver CK MCU DATA LD FGIN DVO 23 24 25 Serial decoder + Address selector + Weight register Predriver H-Bridge C 27 Charge pump ±10 to ±80 µA (8 levels) 33 32 9 11 12 VCC Predriver B.G 21 Vref (0.3 V) PWM Start/stop control H-SW E control H-Bridge D 13 14 TSD 20 Predriver H-Bridge E 31 29 AO1 Stepping motor 1 AO2 PGND1 Motor power supply (VM) 2.2 V to 5.5 V BO1 BO2 VM2 CO1 Stepping motor 2 CO2 PGND2 DO1 DO2 VM3 EO1 DC motor EO2 to FGIN 6-bit DAC3 PWMF H-Bridge B 8 Predriver Speed discriminator 250 to 1750 Hz 16 levels/100 Hz 2 35 34 Triangular wave generator 20, 40, 60, 80 kHz CLK H-Bridge A VM1 C4: 0.1 µF 3 C3: 10 µF P/I SW Logic PWM timer 30 1/N 7 H-SW F control 28 6-bit DAC4 Predriver H-Bridge F (Linear) 15 17 Slope control (32 step) 16 1/1 to 1/16 • Bypass capacitors (C1, C2, C3, C4) should be connected as close to the IC as possible. • The Cdp capacitor of 0.01 to 0.1 µF should be connected to channel-F outputs as necessary to prevent the oscillation. R1 = 0.5 Ω RFE FO1 FO2 RFF C5 UVLO (2.2 V) 0.1 µF Control power supply (VCC) 3.0 V to 5.5 V C1: 10 µF Application Circuit Shutter coil R2 = 0.5 Ω Notes: Excessive power might be introduced into the IC in case of a short-circuit between power supply and ground, an output short-circuit to power supply, an output short-circuit to ground or a short-circuit across the load. If any of these events occur, the device may be degraded or permanently damaged. 14 2008-01-29 TB6596FLG QON Package Considerations Package Appearances (Top view) (Bottom view) Please follow the following guidelines for the QON package. Guidelines: (1) (2) The solder plated pads at the four corners of the package (shaded areas in the bottom view) should not be soldered for the purpose of improving the mechanical strength of solder joints. When using the TB6596FLG, it should be ensured that the thermal pad and solder plated pads (shaded areas in the top and bottom views) are electrically insulated (Note). Note: Care should be taken in the board design to prevent solder for through-hole joints from flowing to the solder plated pads on the bottom of the package (shaded areas in the bottom view). • When mounting or soldering this package, care must be taken to avoid electrostatic discharge or electrical overstress to the IC. (This is to avoid electrical leakage and a buildup of electrostatic charge in the end product.) • It should be ensured that no voltage is directly applied to the solder plated pads when designing the PC board. 15 2008-01-29 TB6596FLG Package Dimensions Weight: 0.08 g (typ.) 16 2008-01-29 TB6596FLG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. IC Usage Considerations Notes on Handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. (2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. (4) Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. 17 2008-01-29 TB6596FLG Points to Remember on Handling of ICs (1) Thermal Shutdown Circuit Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation. (2) Heat Radiation Design In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components. (3) Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. 18 2008-01-29 TB6596FLG RESTRICTIONS ON PRODUCT USE 070122EBA_R6 • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C • Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 060819_AF • The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E 19 2008-01-29