TB67B000AHG
TOSHIBA Bi-CMOS Power Integrated Circuit Multi-Chip Package (MCP)
TB67B000AHG
High voltage
3-Phase Full-Wave PWM Brushless Motor Driver
The TB67B000AHG is a high-voltage PWM brushless motor
driver. The product integrates a controller, which supports
sine-wave PWM drive and wide-angle commutation and a
high-voltage driver in a single package (“two-in-one”, i.e. MCP).
It is designed to change the speed of a brushless motor directly
by using a speed control analog signal from a microcontroller.
P-HDIP30-1233-1.78-001
Weight: 2.59 g (typ.)
Features
•
A Controller and a high-voltage driver integrated in a single package.
Sine-wave PWM drive or wide-angle commutation drive is selectable.
•
IGBTs are arranged in three-phase bridge unit
•
Built-in oscillator circuit (carrier frequency = fosc/252 (Hz))
•
Bootstrap circuitry: Built-in bootstrap diode
•
Built-in overcurrent protection, thermal shutdown, undervoltage lockout, and motor-lock detection.
•
Internal voltage regulator circuit (VREG = 5 V (typ.), 30 mA (max), Vrefout = 5 V (typ.), 35 mA (max))
•
•
Operating power supply voltage range: VCC = 13.5 to 16.5 V
Motor power supply operating voltage range: VBB = 50 to 450 V
© 2019
Toshiba Electronic Devices & Storage Corporation
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TB67B000AHG
Block Diagram
OSCR
5
System clock
generator
TR
6
Lock
detection
Vrefout
15
VREG
19
VCC
18
VBB
29
Voltage
Regulator
(5V)
HUP 7
Under voltage
lockout
HUM 8
HVP 9
Voltage
Regulator
(5V)
HVM 10
Under
voltage
lockout
Control circuit
LA 3
25 BSV
Voltage Regulator (5V)
27 BSW
High-side
level shift
driver
UH
Output circuit
Input/Output
circuit
VH
23 U
Thermal
UL
VSP 2
FG 1
24 BSU
Voltage Regulator (5V)
Under Under Under
voltage voltage voltage
lockout lockout lockout
HWP 11
HWM 12
Voltage Regulator (5V)
Input protection
logic
26 V
shutdown
28 W
VL
Low-side
driver
WH
FGC 13
WL
CW/CCW 17
SS 14
(Controller)
16
Idc
(Driver)
4
SGND
20
PGND
2
21
IS1
22
IS2
30
IS3
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TB67B000AHG
Pin Assignment
IS3
30
VBB
W
29
28
BSV
BSW
V
27
26
BSU
25
IS1
24
U
IS2
23
22
21
14
15
PGND
VREG
20
19
17
18
(Die pad)
1
2
FG
3
LA
VSP
4
5
6
OSCR
SGND
TR
7
8
HUP
9
10
HVP
HUM
11
12
HWP
HVM
HWM
13
FGC
16
Vrefout
SS
Idc
CW/CCW
VCC
Note: Die pad on the package surface and PGND are connected. When using the heat sink, handle it not to short to
the IC pins. When applying the different potential with GND level to the heat sink, insulate with die pad and the
heat sink.
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TB67B000AHG
Pin Description
Pin No.
Symbol
Description
Function
1
FG
FG signal output
FGC = H: FG = output 1 ppr
FGC = M: FG = output 2.4 ppr
FGC = L: FG = output 3 ppr
*ppr: one pulse per one electrical angle
2
VSP
Voltage command input
This pin has a pull-down resistor. (150 kΩ)
3
LA
Lead angle control input
This pin has a pull-down resistor. (200 kΩ)
Input voltage range: 0 to 5 V (Vrefout)
SS = H: 0 to 28° in 16 steps.
SS = L: 0 to 58° in 32 steps.
5
OSCR
Resistor for oscillation
Connect a resistor for internal clock oscillation.
6
TR
Motor lock detection
Connect a capacitor for motor lock detection oscillation or connect to GND.
7
HUP
U-phase hall input+
8
HUM
U-phase hall input-
9
HVP
V-phase hall input+
10
HVM
V-phase hall input-
11
HWP
W-phase hall input+
12
HWM
W-phase hall input-
13
FGC
FG output signal switch
15
Vrefout
14
SS
17
CW/CCW
When the hall signal inputs (UVW) are all Highs or all Lows, the gate block
protection becomes active. Built-in digital filter (≈1.6 μs)
This pin has a pull-down resistor. (100 kΩ)
H: FG = output 1 ppr.
M: FG = output 2.4 ppr.
L: FG = output 3 ppr.
*ppr: one pulse per one electrical angle
Reference voltage output 5 V (typ.), 35 mA (max), Connecting a capacitor for voltage stability.
This pin has a pull-down resistor. (100 kΩ)
Switch for commutation
H: Wide-angle commutation (150° commutation)
waveform
L: Sine-wave PWM drive (180° commutation)
Forward/Reverse
switching input
This pin has a pull-down resistor. (100 kΩ)
H: Forward
L: Reverse
Current limit input
This pin has a pull-up resistor. (200 kΩ)
DC link input
Reference potential of 0.5 V. This pin has a RC filter (≈ 1 μs) and a digital
filter (≈ 0.6 μs).
Signal ground.
Connect with PGND.
16
Idc
4
SGND
Ground pin
19
VREG
Reference voltage output 5 V (typ.), 30 mA (max). Connecting a capacitor for voltage stability.
18
VCC
20
PGND
23
U
24
BSU
Bootstrap supply
(phase U)
For connecting a bootstrap capacitor to the U-phase output.
21
IS1
U-phase IGBT emitter
For connecting a detecting resistor for motor coil current to the PGND pin.
22
IS2
V-phase IGBT emitter
For connecting a detecting resistor for motor coil current to the PGND pin.
25
BSV
Bootstrap supply
(phase V)
For connecting a bootstrap capacitor to the V-phase output.
26
V
V-phase output pin
29
VBB
High-voltage power
supply pin
Power supply pin for driving a motor.
27
BSW
Bootstrap supply
(phase W)
For connecting a bootstrap capacitor to the W-phase output.
28
W
W-phase output pin
30
IS3
W-phase IGBT emitter
Power supply pin for the
15 V (typ.)
power stage
Ground pin
Power ground
Connect with SGND.
―
U-phase output pin
―
―
For connecting a detecting resistor for motor coil current to the PGND pin.
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TB67B000AHG
Input/Output Equivalent Circuits
Equivalent circuit diagrams may be partially omitted or simplified for explanatory purposes.
Pin
Input/Output Signal
Internal Circuit
HUP
HUM
Vrefout Vrefout
Analog / Digital
HVP
HVM
Hysteresis: ±7.5 mV (typ.)
HWP
Digital filter : 1.6 μs (typ.)
HWM
Vrefout
76 kΩ
224 kΩ
Analog
VSP
Vrefout
VSP input range: 0 to 10 V
Internal pull-down resistor: 150 kΩ
Vrefout
Digital
SS
L : 0.8 V (max)
H: Vrefout - 1 V (min)
100 kΩ
CW/CCW
140 kΩ
160 kΩ
Internal pull-down resistor: 100 kΩ
Vrefout
Analog
100 kΩ
LA input range: 0 to 5 V (Vrefout)
100 kΩ
LA
Internal pull-down resistor: 200 kΩ
Vrefout Vrefout
Analog filter time constant: 1.0 μs (typ.)
Digital filter time constant: 0.6 μs (typ.)
200 kΩ
5 pF
Idc
200 kΩ
Analog
Internal pull-up resistor: 200 kΩ
Vrefout
Digital
L : 0.8 V (max)
M: 2.0 V(min) 3.0 V(max)
H: Vrefout - 1 V (min)
50 kΩ
50 kΩ
FGC
0.5 V
Internal pull-down resistor: 100 kΩ
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TB67B000AHG
Pin
Input/Output Signal
Internal Circuit
Vrefout
Digital
Vrefout
Push-pull output :±2 mA (max)
FG
FGC = H: 1 ppr
FGC = M: 2.4 ppr
FGC = L: 3 ppr
VBB
U
V
W
IS1
U
U, V, W-phase output pin
U, V, W-phase IGBT emitter pin
V
W
IS2
IS3
IS1
6
IS2
IS3
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TB67B000AHG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
VBB
600
VCC
18
Vin (1)
-0.3 to VCC (Note 1)
Vin (2)
-0.3 to Vrefout +0.3 (Note 2)
Output current (DC)
IOUT
2
A
Output current (pulse 1ms)
IOUTP
3 (Note 3)
A
VREG current
Ireg
30
mA
Vrefout current
Irefout
35
mA
Power dissipation
PD
35 (Note 4)
W
Operating temperature
Topr
-30 to 115 (Note 5)
°C
Storage temperature
Tstg
-55 to 150
°C
Power supply voltage
Input voltage
Unit
V
V
Note: Absolute maximum ratings
The maximum rating is the rating that should never be exceeded, even for a shortest of moments. If the
maximum rating is exceeded, it could result in damage and/or deterioration of the IC as well as other devices
beside the IC. Regardless of the operating conditions, please design so that the maximum rating is never
exceeded. Please use within the specified operating range.
Note 1: Vin (1) pin: VSP and LA
Note 2: Vin (2) pin: HUP, HUM, HVP, HVM, HWP, HWM, SS, FGC, CW/CCW, and Idc.
Note 3: Apply pulse
Note 4: Package thermal resistance (θj-c = 1°C/W) with an infinite heat sink at Ta = 25°C
Note 5: The operating temperature range is determined according to the PD MAX - Ta characteristics.
Operating conditions (Ta = 25°C)
Characteristics
Symbol
Min
Typ.
Max
VBB
50
280
450
VCC
13.5
15
16.5
Oscillation frequency
fOSC
3.5
5
6.4
MHz
Output current
Iout
―
―
2
A
Operating temperature
Topr
-30 (Note)
―
115 (Note)
°C
Power supply voltage
Unit
V
Note: The operating temperature range is determined according to the PD MAX - Ta characteristics.
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TB67B000AHG
Power Dissipation
PD MAX – Ta
Power dissipation PD MAX (W)
40
①
30
20
10
②
③
④
0
0
25
50
75
100
125
150
Ambient temperature Ta (°C)
① INFINITE HEAT SINK
: Rθj-c = 1°C/W
② When mounted on the board (74.2 × 114.3 × 1.6 mm, Cu20%), HEAT SINK (10 × 10 × 1 mm, Cu)
: Rθj-a = 17°C/W
③ When mounted on the board (74.2 × 114.3 × 1.6 mm, Cu20%)
: Rθj-a = 35°C/W
④ IC only
: Rθj-a = 53°C/W
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TB67B000AHG
Electrical Characteristics (Ta = 25°C)
Characteristics
Current dissipation
Current consumption of
bootstrap
Input current
Symbol
Test Condition
―
―
0.5
ICC
VCC = 15 V
―
5
10
IBS (ON)
VBS = 5 V, high-side ON
―
90
150
IBS (OFF)
VBS = 5 V, high-side OFF
―
80
140
IIN(LA)
Vin = 5 V, LA
―
25
50
IIN(VSP)
Vin = 5 V, VSP
―
35
70
IIN(Idc)
Vin = GND, Idc
―
-25
-50
Vin = 5 V, CW/CCW, FGC, SS
―
50
100
Vrefout
-1
―
Vrefout
L
0
―
0.8
H
4
―
Vrefout
VIN2
H
CW/CCW, SS
M
FGC
L
V
H
PWM ON duty 95%
SS = H
5.1
5.4
5.7
M
Refresh → Start motor operation,
SS = H
1.8
2.1
2.4
L
Turned-off → Refresh
SS = H
0.7
1.0
1.3
T
Test mode for motor shipping
SS = L
8.2
―
10
H
PWM ON duty 92%
SS = L
5.1
5.4
5.7
M
Refresh → Start motor operation,
SS = L
1.8
2.1
2.4
L
Turned-off → Refresh
SS = L
0.7
1.0
1.3
FC (20)
OSC/R = 68 kΩ
18
20
22
FC (18)
OSC/R = 75 kΩ
16.2
18
19.8
TONTR
TR = 0.01 μF Driving time
(Note )
3.33
5
8.33
s
TOFFTR
TR = 0.01 μF Turn off time
(Note )
20
30
46.15
s
TR = 0.01 μF frequency
65
100
150
Hz
LA = 0 V or open, Hall IN = 100 Hz
SS = H
―
0
―
V
V
kHz
TLAH(2.5)
LA = 2.5 V, Hall IN = 100 Hz
SS = H
11.25
15
18.75
TLAH (5)
LA = 5 V, Hall IN = 100 Hz
SS = H
26.25
28.125
―
TLAL(0)
LA = 0 V or Open, Hall IN = 100 Hz
SS = L
―
0
―
LA = 2.5 V, Hall IN = 100 Hz
SS = L
26
30
33
LA = 5 V, Hall IN = 100 Hz
SS = L
52
57
60
VS
Difference input
40
―
―
mVpp
VW
―
0.5
―
4.0
V
±1.5
±7.5
±13.5
mV
TLAL (5)
Input
hysteresis
3
1
V
10
TLAL (2.5)
In-phase
Hall device input range
―
―
μA
―
TLAH(0)
Input
sensitivity
2
0
μA
8.2
FTR
Lead angle offset
mA
Test mode for motor shipping
SS = H
VSP(L)
Lead angle offset (LA)
Unit
T
VSP(H)
Motor lock detection
Max
VBB = 450 V
VIN1
PWM oscillation frequency
(Carrier frequency)
Typ.
IBB
IIN(1)
Input voltage
Min
VH (1)
(Note)
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°
°
TB67B000AHG
H
Hall IC input
VIN4
L
Current detection
Output voltage
Output saturated voltage
Vdc
Over heat protection
Idc
Vrefout
-1
―
Vrefout
0
―
0.8
0.475
0.5
0.525
VFG (H)
IOUT = 2 mA
FG
4
―
―
VFG (L)
IOUT = -2 mA
FG
―
―
1
Vrefout1
IOUT = 15 mA
Vrefout
4.7
5.0
5.3
Vrefout2
IOUT = 35 mA
Vrefout
4.5
5.0
5.3
VREG
IOUT = 30 mA
VREG
4.5
5.0
5.5
VCC = 15 V, IC = 1 A, High side
―
2.3
3.2
VCC = 15 V, IC = 1 A, Low side
―
2.3
3.2
VFH
IF = 1 A, High side
―
2.1
3.1
VFL
IF = 1 A, Low side
―
2.1
3.1
135
―
185
―
50
―
VCEsatH
VCEsatL
Forward voltage of FRD
HUP, HVP, HWP:
HUM, HVM, HWM = Vrefout/2
TSD
(Note )
TSDhys
V
V
V
V
V
°C
VCC
Undervoltage lockout
(Driver)
VCC (H)
Undervoltage positive-going threshold
10.5
11.5
12.5
VCC (L)
Undervoltage negative-going threshold
10
11
12
VBS Undervoltage lockout
(Driver)
VBS (H)
Undervoltage positive-going threshold
2.5
3.5
4.5
VBS (L)
Undervoltage negative-going threshold
2
3
4
ton
VBB = 280 V, VCC = 15 V, IC = 1 A
―
2
3.5
toff
VBB = 280 V, VCC = 15 V, IC = 1 A
―
2
3.5
Idc (fosc = 5 MHz)
―
4.4
―
μs
VBB = 280 V, VCC = 15 V, IC = 1 A
―
150
―
ns
Output delay time
Input delay time
FRD reverse recovery time
V
V
TDC
trr
Note: No shipping inspection.
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μs
TB67B000AHG
Functional Description
1. Basic Operation
The motor is driven by 120° commutation at startup. When the hall signal detects the motor rotating at the
frequency of 1 Hz or higher, the rotor position is estimated and the motor is driven with the lead angle
based on the input voltage of the LA pin.
From start to 1 Hz: Driven by square wave (120° commutation)
1 Hz or higher: Driven by sine-wave PWM (180° commutation) or wide-angle commutation (150°
commutation)
When fosc = 5 MHz, approx. 1 Hz.
*: When f is 1 Hz or higher, the motor is driven by the command of the LA pin.
When f is 1 Hz or less or the motor is driven with reverse rotation direction (according to the timing
chart), it is driven by 120° commutation (lead angle is 0°).
Driven system (sine-wave PWM or wide-angle commutation) can be switched by the SS pin. Setting of lead
angle is different between these driving systems.
SS
Driving system
Lead angle
L
Sine-wave PWM drive
(180° commutation)
0 to 58° / 32 steps
H
Wide-angle commutation
(150° commutation)
0 to 28° / 16 steps
2. Voltage Command (VSP) Signal and Bootstrap Voltage Regulation
SS=L
(1)
Voltage command input: When VSP ≤ 1.0 V:
The commutation signal outputs are disabled (i.e., gate protection is activated).
(2)
Voltage command input: When 1.0 V < VSP ≤ 2.1 V:
The low-side transistors are turned on at a regular (PWM carrier) frequency. (ON duty: 18/fosc)
(3)
Voltage command input: When 2.1 V < VSP ≤ 7.3 V:
During sine-wave PWM drive, the commutation signals directly appear externally. During
square-wave drive, the low-side transistors are forced on at a regular (PWM carrier) frequency. (ON
duty: 18/fosc)
In stop state (Forward: 1Hz or less, Reverse: 5 Hz or less), commutation signals are outputted after
VSP (VSP > 2.1 V) is inputted and the refresh function operates for 1.5ms (typ.). In operation state
(Forward: more than 1 Hz, Reverse: more than 5 Hz), commutation signals are outputted after VSP
(VSP > 2.1 V) is inputted.
Note: In startup, low-side transistor should be turned on (1.0 V < VSP ≤ 2.1 V) for a certain period to charge
gate power supply of high-side transistors.
(4)
Voltage command input: When 8.2 V ≤ VSP ≤ 10 V (test mode for motor shipping):
The TB67B000AHG drives in sine-wave drive mode with lead angle of zero. However, it drives in
square-wave mode in detecting reverse rotation.
When VSP reaches 7.9 V (typ.), lead angle switches to zero.
The PWM duty cycle is calculated as PWM carrier period × 92% (typ.) and kept the constant value at
the following condition; 5.4 V(typ.) ≤ VSP.
PWM Duty
92%
1.0 V
(1)
2.1 V
(2)
5.4 V
(3)
11
VSP
7.3 V 8.2 V
(4)
10 V
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TB67B000AHG
SS=H
(1)
Voltage command input: When VSP ≤ 1.0 V:
The commutation signal outputs are disabled (i.e., gate protection is activated).
(2)
Voltage command input: When 1.0 V < VSP ≤ 2.1 V:
The low-side transistors are turned on at a regular frequency (PWM carrier frequency). (ON duty:
18/fosc)
(3)
Voltage command input: When 2.1 V < VSP ≤ 7.3 V:
During wide-angle commutation, the commutation signals directly appear externally. During
square-wave drive, the low-side transistors are forced on at a regular (PWM carrier) frequency. (ON
duty: 18/fosc)
In stop state (Forward: 1 Hz or less, Reverse: 5 Hz or less), commutation signals are outputted after
VSP (VSP > 2.1 V) is inputted and the refresh function operates for 1.5 ms (typ.). In operation state
(Forward: more than 1Hz, Reverse: more than 5 Hz), commutation signals are outputted after VSP
(VSP > 2.1 V) is inputted.
Note: In startup, low-side transistor should be turned on (1.0 V < VSP ≤ 2.1 V) for a certain period to charge
gate power supply of high-side transistors.
(4)
Voltage command input: When 8.2 V ≤ VSP ≤ 10 V (test mode for motor shipping):
The TB67B000AHG drives in wide-angle commutation mode with lead angle of zero. However, it
drives in square-wave mode in detecting reverse rotation.
When VSP reaches 7.9 V (typ.), lead angle switches to zero.
The PWM duty cycle is calculated as PWM carrier period × 95% (typ.) and kept the constant value at
the following condition; 5.4 V (typ.) ≤ VSP.
PWM Duty (Upper phase)
*95%
(typ.)
*2.4%
(typ.)
1.0 V
(1)
2.1 V
(2)
5.4 V
(3)
7.3 V 8.2 V
10 V
VSP
(4)
*: Maximum ON duty: Ton = 95% (typ.) when VSP = 5.4 V (typ.)
Maximum ON duty may be 100% due to the influence of the filter inside the IC.
Minimum ON duty: Ton = 2.4% (typ.) when VSP = 2.1 V (typ.).
Ex.: When fosc = 5 MHz, maximum ON time = 48 μs (typ.) (fc = 19.8 kHz)
minimum ON time = 1.2 μs (typ.) (fc = 19.8 kHz)
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TB67B000AHG
3. Dead Time Insertion (cross conduction protection)
To prevent a short-circuit between low-side and high-side power devices during sine-wave PWM drive, a
dead time is digitally inserted between the turn-on of one side and the turn-off of the other side. (The dead
time is also implemented at the full duty cycle during square-wave drive.)
Td = 9/fosc
UH
(VH, WH)
When fosc = 5 MHz, Td ≈ 1.8 μs (9/fosc)
fosc = reference clock (CR oscillation frequency)
Td
Td
UL
(VL, WL)
When input voltage (VSP) is more than 2.1 V and the hall signal frequency is 1 Hz or less, the upper
phase (UH, VH, and WH) operates PWM drives (according to VSP) with120° commutation. And the lower
phase (UL, VL, and WL) operates with 120° commutation. It refreshes in off timing. (In case of reverse
direction drive, the operation is the same as forward direction drive.)
Output waveform (Image)
UH
UL
VH
VL
WH
WL
Enhanced
WH
TSP
Td
WL
Td
Ton
TSP: Changeable by VSP. (The condition in this figure: VSP = 5.4 V (typ.)), Ton = 18/fosc, Td = 9/fosc.
*: Lead angle offset (LA pin) is not activated when hall signal frequency is 1 Hz or less. The lead angle is
also deactivated in detecting of reverse rotation.
4. Lead Angle Control
The lead angle can be adjusted between 0° and 58° according to the induced voltage level on the LA input.
SS=L
SS=H
LA analog input (0 to 5 V in 32 separate steps.)
0 V = 0°
5 V = 58° (A lead angle of 58° is assumed when the LA voltage exceeds 5 V.)
LA analog input (0 to 5 V in 16 separate steps).
0 V = 0°
5 V = 28° (A lead angle of 28° is assumed when the LA voltage exceeds 5 V.)
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TB67B000AHG
5. PWM Carrier Frequency
The triangular waveform generator provides a carrier frequency of fosc/252 necessary for PWM generation.
(The triangular wave is also used to force the switch-on of low-side commutation signal outputs during
square-wave drive.)
Carrier frequency: FC = fosc/252 (Hz), where fosc = reference clock (CR oscillator) frequency
6. Position Detecting Pin
VW is 0.5 to 4.0 V in in-phase range. Input hysteresis voltage (VH ) is 7.5 mV (typ.).
VH = 7.5 mV (typ.)
VS
VH
HUM
VH
VS = 40 mV or more
HUP
Usage conditions: HUP, HVP, and HWP = GND to Vrefout
HUM, HVM, and HWM = Vrefout / 2
7.
Rotating Pulse Output
The TB67B000AHG outputs rotating pulse based on the hall signal. FGC pin can switch one pulse per
electrical angle, 3 pulses per electrical angle, or 2.4 pulses per electrical angle. One pulse per electrical
angle is generated from the hall signal of U phase. 3 pulses per electrical angle are generated by combining
each rising and falling edge of U, V, and W phases.
When the pulse is outputted at 2.4 pulses per electrical angle (FGC=M), FG pin outputs L level under the
condition that the direction of motor rotating is forward or reverse at 1 Hz or less. It is outputted
regardless of the input voltage of VSP.
FGC
FG
H
1 pulse per electrical angle
M
2.4 pulses per electrical angle (2 pulses per 5/6 electrical angle)
L
3 pulses per electrical angle
Timing Chart of FG Signal
HUM
HUP
HVM
HVP
HWP
HWM
FGC = L
FGC = M
FGC = H
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8.
Protection-related Functions
(1)
Overcurrent protection(Idc pin)
If the DC-link current exceeds the corresponding internal reference voltage, the gate block is
activated and the commutation signals (U, V, and W) are forced off. Overcurrent protection is disabled
after every carrier period.
Reference voltage = 0.5 V (typ.)
(2)
Abnormal hall signal protection
When the hall signals (internal hall amplifier outputs) are all Highs or all Lows, or hall input signals
(HUP, HUM, HVP, HVM, HWP, and HWM) are all open, the commutation outputs (U, V, and W) are
forced off. When these inputs are then set to any other combination, the commutation outputs are
re-enabled.
(3)
Undervoltage lockout (VCC)
While the power supply voltage is outside the rated range during power-on or power-off, the
commutation outputs (U, V, and W) are forced off to stop the motor operation. The motor operation in
power recovery is not guaranteed because the state of the circuit becomes unstable by power on
sequence.
VCC: 15V(typ.)
Supply voltage 11.5 V (typ.)
11.0 V (typ.)
GND
VBB
Drive output
Output OFF
(4)
Output OFF
Output drive
Monitor for VBS bootstrap power supply
When VBS power supply falls, high-side of IGBT output is turned off.
VBS (Output-BS)
3 V (typ.)
3.5 V (typ.)
High-side IGBT
Output OFF
(5)
Output drive
Output OFF
Thermal shutdown circuit
When the IC temperature rises high abnormally because of internal or external heat generation, all
outputs of IGBT are tuned off.
TSD = 135°C (min), 185°C (max)
TSDhys = 50°C (typ.)
Recovery temperature after TSD is activated: TSD - TSDhys
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9. Motor-lock detection
When hall signal detects below state, intermitted operation (drive period: stop period = 1: 6) is repeated.
When VSP exceeds 2.1 V, the detection period starts. In this time, the counter for the motor lock detection
starts counting. When direction of the motor rotation corresponds to the pin configuration (forward direction:
sine-wave PWM mode or wide-angle commutation mode), lock detection is activated with 120° commutation
(square-wave drive) under the condition that frequency of the hall signal is about 1 Hz or less (when fosc =
5 MHz).
When direction of motor rotation is opposed against pin setting direction (reverse direction: reverse hall
input in 120° commutation mode), lock detection is activated under the condition that frequency of the hall
signal is about 5 Hz or less (when fosc = 5 MHz).
When lock detection enables, operation is turned off (output drive is OFF) during stop period.
When VSP is set 1.0 V or less, counter is reset and the stop mode is released. Then, when VSP is set 2.1 V or
more again, counter starts counting from the initial state.
Table of lock detection
VSP pin ≤ 2.1V
VSP pin > 2.1V
Direction of motor rotation
CW/CCW pin
H(CW)
L(CCW)
CW
CCW
Hall ≤ 1 Hz
(Rotating direction:
set of CW/CCW pin = motor)
Hall ≤ 5 Hz
(Rotating direction:
set of CW/CCW pin ≠ motor)
Hall ≤ 5 Hz
(Rotating direction:
set of CW/CCW pin ≠ motor)
Hall ≤ 1 Hz
(Rotating direction:
set of CW/CCW pin = motor)
―
Inactive
Inactive
Hall U
Hall V
Hall W
120° commutation →wide-angle commutation
120° commutation→sine-wave drive
(Hall > 1 Hz)
Counter reset
Counter reset
VSP < 1V
(typ.)
VSP
Counter start
VSP > 2.1V
(typ.)
Oscillation
Counter
Drive output
control
C1
TR
Open detection
by TR pin
Detection period and output-off period can be determined by an external capacitor (C1) of TR pin.
･Setting period
Drive period Ton[s] =C1 × (VH―VL) × 2 / I × 500 counts
Stop period Toff[s] =C1 × (VH―VL) × 2 / I × 3000 counts (Note 1)
•
Ex.: When C1 = 0.01μF, I = 3μA (typ.), VH= 2 V (typ.) and VL= 0.5 V (typ.), and then Ton[s] =5 s (typ.) and
Toff[s] = 30 s (typ.).
Note 1: Bootstrap capacitor does not charge (refresh) during stop period.
To charge bootstrap capacitor in recovery, VSP should be set by voltage command input as follows;
1.0 V < VSP ≤ 2.1 V.
Note 2: When TR pin is open, the operation moves to stop mode (drive output OFF) by open detection.
Note 3: Counter is not activated by applying fixed voltage (GND) to the TR pin. Then, the drive mode can be continued
because the motor lock detection is turned off.
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Timing Chart
CW/CCW
SS
Hall input (frequency)
Drive method
No.
CW (1 Hz or less)
Square-wave drive (120° commutation)
5
CW (1 Hz or higher)
Wide-angle commutation (150° commutation)
3
CCW
Square-wave drive (120° commutation)
6
CW (1 Hz or less)
Square-wave drive (120° commutation)
5
CW (1 Hz or higher)
Sine-wave PWM drive (180° commutation)
1
CCW
Square-wave drive (120° commutation)
6
CW
Square-wave drive (120° commutation)
8
CCW (1 Hz or less)
Square-wave drive (120° commutation)
7
CCW (1 Hz or higher)
Wide-angle commutation (150° commutation)
4
CW
Square-wave drive (120° commutation)
8
CCW (1 Hz or less)
Square-wave drive (120° commutation)
7
CCW (1 Hz or higher)
Sine-wave PWM drive (180° commutation)
2
H
H
L
H
L
L
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Timing Chart 1: Output waveform of sine-wave PWM drive
(CW/CCW = H, SS = L, LA = GND, Non-Inverted hall signal inputs)
(Non-inverted hall signal inputs)
HUP
HUM
HVM
HVP
HWP
HWM
Modulaed signal
Carrier frequency
Vrefout
(typ.)
U
(IC internal)
GND
Output waveform
VBB
U
GND
VBB
V
GND
VBB
W
GND
Note: The above timing chart is simplified to illustrate the function and behavior of the device.
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Timing Chart 2: Output waveform of sine-wave PWM drive
(CW/CCW = L, SS = L, LA = GND, Inverted hall signal inputs)
(Inverted hall signal inputs)
HUM
HUP
HVM
HVP
HWP
HWM
Modulaed signal
Carrier frequency
Vrefout
(typ.)
U
(IC internal)
GND
VBB
Output waveform
U
GND
VBB
V
GND
VBB
W
GND
Note: The above timing chart is simplified to illustrate the function and behavior of the device.
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Timing Chart 3: Output waveform of wide-angle commutation
(CW/CCW = H, SS = H, LA = GND, Non-Inverted hall signal inputs)
(Non-inverted hall signal inputs)
HUP
HUM
HVM
HVP
HWP
HWM
VSP input voltage
Carrier frequency
PWM generation
(IC internal)
VBB
VBB
2
GND
Output waveform
U
V
VBB
VBB
2
GND
W
VBB
VBB
2
GND
Note: The above timing chart is simplified to illustrate the function and behavior of the device.
VBB
indicates the high-impedance state.
2
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Timing Chart 4: Output waveform of wide-angle commutation
(CW/CCW = L, SS=H, LA = GND, Inverted hall signal inputs)
(Inverted hall signal inputs)
HUM
HUP
HVM
HVP
HWP
HWM
VSP input voltage
Carrier frequency
PWM generation
(IC internal)
Output waveform
U
VBB
VBB
2
GND
V
VBB
VBB
2
GND
W
VBB
VBB
2
GND
Note: The above timing chart is simplified to illustrate the function and behavior of the device.
VBB indicates the high-impedance state.
2
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Timing Chart 5: Output waveform of square-wave drive
(CW/CCW = H, LA = GND, Non-Inverted hall signal inputs)
(Non-inverted hall signal inputs)
HUP
HUM
HVM
HVP
HWP
HWM
VSP input voltage
Carrier frequency
PWM generation
(IC internal)
VBB
VBB
2
GND
Output waveform
U
V
VBB
VBB
2
GND
W
VBB
VBB
2
GND
Note: The above timing chart is simplified to illustrate the function and behavior of the device.
VBB
indicates the high-impedance state.
2
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Timing Chart 6: Output waveform of square-wave drive
(CW/CCW = H, LA = GND, Inverted hall signal inputs)
(Inverted hall signal inputs)
HUM
HUP
HVM
HVP
HWP
HWM
VSP input voltage
Carrier frequency
PWM generation
(IC internal)
Output waveform
U
VBB
VBB
2
GND
V
VBB
VBB
2
GND
W
VBB
VBB
2
GND
Note: The above timing chart is simplified to illustrate the function and behavior of the device.
VBB
indicates the high-impedance state.
2
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Timing Chart 7: Output waveform of square-wave drive
(CW/CCW = L, LA = GND, Inverted hall signal inputs)
(Inverted hall signal inputs)
HUM
HUP
HVM
HVP
HWP
HWM
VSP input voltage
Carrier frequency
PWM generation
(IC internal)
Output waveform
U
VBB
VBB
2
GND
V
VBB
VBB
2
GND
W
VBB
VBB
2
GND
Note: The above timing chart is simplified to illustrate the function and behavior of the device.
VBB
indicates the high-impedance state.
2
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Timing Chart 8: Output waveform of square-wave drive
(CW/CCW = L, LA = GND, Non-Inverted hall signal inputs)
(Non-inverted hall signal inputs)
HUP
HUM
HVM
HVP
HWP
HWM
VSP input voltage
Carrier frequency
PWM generation
(IC internal)
Output waveform
U
VBB
VBB
2
GND
V
VBB
VBB
2
GND
W
VBB
VBB
2
GND
Note: The above timing chart is simplified to illustrate the function and behavior of the device.
VBB
2
indicates the high-impedance state.
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Application Circuit Example
R1
C1
C2
5 OSCR
System clock
generator
Vrefout
HUP
HUM
HVP
HVM
HWP
HWM
Vrefout
LA
VSP
MCU
FG
Vrefout
Vrefout
FGC
CW/CCW
Vrefout
SS
6 TR
C3
C4
15 Vrefout
Lock
detection
C7
19 VREG
7
8
9
Voltage
Regulator
(5V)
10
Under
voltage
lockout
12
Control circuit
Voltage Regulator (5V)
24
Voltage Regulator (5V)
25
Voltage Regulator (5V)
27
BSU
BSV
BSW
High-side
level shift
driver
C10 C9 C8
UH
Output circuit
Input/Output
circuit
VH
23
Thermal
UL
2
1
29 VBB
Under Under Under
voltage voltage voltage
lockout lockout lockout
11
3
15 V
18 VCC
Voltage
Regulator
(5V)
Under voltage
lockout
C6
Input protection
logic
26
shutdown
28
VL
V
W
Low-side
driver
WH
13
U
WL
17
14
(Controller)
16 Idc
(Driver)
20 PGND
4 SGND
21 IS1 22 IS2 30 IS3
R2
C5
R3
Utmost care is necessary in the design of board layout since the IC may be destroyed and cause smoke or ignition by short-circuiting between outputs, air contamination faults, or faults due to
improper grounding, or by short-circuiting between contiguous pins. Specially, in the design of the output, VBB, U, V, W, IS1, IS2, IS3, BSU, BSV, BSW, and GND lines which have high voltage
and high current, utmost care is necessary. Add overcurrent protection such as a fuse not to allow large current continuing to flow in case of over current generation or IC breakdown.
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TB67B000AHG
External Parts
Symbol
Purpose
Recommended value
Note
R1
Internal clock generation
68 kΩ
(Note 1)
C1
Motor lock detection
10 V / 0.01 μF
(Note 2)
C2
Vrefout oscillation protection
10 V / 0.1 μF to 1.0 μF
(Note 3)
C3
VREG power supply stability
C4
C5
25 V / 1 μF
10 V / 1000 pF
Noise absorber
(Note 4)
R2
R3
C6
C7
C8, C9, C10
(Note 3)
25 V / 1000 pF
5.1 kΩ
Overcurrent detection
VCC power supply stability
Bootstrap capacitor
0.62 Ω ± 1% (1 W)
25 V / 10 μF
25 V / 0.1 μF
25 V / 2.2 μF
(Note 5)
(Note 3)
(Note 6)
Note 1: For carrier frequency and dead time, determine the resistor to set the oscillation frequency of 6.4 MHz or less.
Note 2: This component sets the output stop period and output drive period of motor lock detection. When this function
is not used, connect it to GND. As for detailed descriptions, please refer to the section of “Motor Lock
Detection” in this document.
Note 3: This component is used as a capacitor for power supply stability. Adjust it to the application environment as
required. In mounting, place it as close as possible to the base of the leads of this product to improve the noise
elimination.
Note 4: These components are used as a low-pass filter for noise absorption. Test to confirm noise filtering, then
determine its constant number.
Note 5: This component is used to set the value for overcurrent detection. Iout (max) = Vdc / R3 (Vdc = 0.5 V (typ.))
Note 6: The required bootstrap capacitance value varies depending on the motor drive conditions. The voltage stress
for the capacitor equals to the value of VCC.
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Package Dimensions
P-HDIP30-1233-1.78-001
Unit: mm
Weight: 2.59 g (typ.)
Note: Die pad on surface and PGND is connected. When using the heat sink, handle it not to short to the IC pins.
When applying the different potential with GND level to the heat sink, insulate with die pad and the heat sink.
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory
purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is
required, especially at the mass production design stage.
Providing these application circuit examples does not grant a license for industrial property rights.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These components and
circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment.
IC Usage Considerations
Notes on handling of ICs
[1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a
moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by
explosion or combustion.
[2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current
and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings,
when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a
large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow
of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit
location, are required.
[3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to
prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the
negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or
ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection
function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition.
[4] Do not insert devices in the wrong orientation or incorrectly.
Make sure that the positive and negative pins of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s)
may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion.
In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly
even just one time. Utmost care is necessary in the design of board layout since the IC may be destroyed and cause
smoke or ignition by short-circuiting between outputs, air contamination faults, or faults due to improper grounding,
or by short-circuiting between contiguous pins. Specially, in the design of the output, VBB, U, V, W, IS1, IS2, IS3,
BSU, BSV, BSW, and GND lines which have high voltage and high current, utmost care is necessary.
[5] Die pad on surface and PGND is connected.
When using the heat sink, handle it not to short to the IC pins. When applying the different potential with GND level
to the heat sink, insulate with die pad and the heat sink.
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Points to remember on handling of ICs
(1) Over current Protection Circuit
Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs under all
circumstances. If the over current protection circuits operate against the over current, clear the over current status
immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the
over current protection circuit to not operate properly or IC breakdown before operation. In addition, depending on
the method of use and usage conditions, if over current continues to flow for a long time after operation, the IC may
generate heat resulting in breakdown.
(2) Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown circuits
operate against the over temperature, clear the heat generation status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the
thermal shutdown circuit to not operate properly or IC breakdown before operation.
(3) Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is
appropriately radiated, not to exceed the specified junction temperature (Tj) at any time and condition. These ICs
generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life,
deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the
effect of IC heat radiation with peripheral components.
(4) Back-EMF
When a motor reverses the rotation direction, stops or slows down abruptly, a current flow back to the motor’s power
supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor
power supply and output pins might be exposed to conditions beyond absolute maximum ratings. To avoid this
problem, take the effect of back-EMF into consideration in system design.
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RESTRICTIONS ON PRODUCT USE
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