TB67B000FG
TOSHIBA Bi-CMOS Power Integrated Circuit Multi-Chip Package (MCP)
TB67B000FG
High voltage
3-Phase Full-Wave Sine-Wave PWM Brushless Motor Driver
The TB67B000FG is a high-voltage PWM brushless DC motor
driver. The product integrates a controller, which supports
sine-wave PWM drive and wide-angle commutation and a
high-voltage driver in a single package (“two-in-one”, i.e. MCP). It
is designed to change the speed of a brushless DC motor directly
by using a speed control analog signal from a microcontroller.
P-HSSOP34-0918-0.80-001
Weight: 0.74 g (typ.)
Features
•
A Controller and a high-voltage driver are integrated in a single package.
Sine-wave PWM drive or wide-angle commutation drive is selectable.
•
IGBTs are arranged in three-phase bridge unit.
•
Built-in oscillator circuit (carrier frequency = fosc/252 (Hz))
•
Bootstrap circuitry: Built-in bootstrap diode
•
Built-in overcurrent protection, thermal shutdown, undervoltage lockout, and motor-lock detection.
•
Internal voltage regulator circuit (VREG = 7 V (typ.), 30 mA (max), Vrefout = 5 V (typ.), 35 mA (max))
•
Operating power supply voltage range: VCC = 13.5 to 16.5 V
•
Motor power supply operating voltage range: VBB = 50 to 450 V
This product is fabricated by MOS FET. It is sensitive to electrostatic discharge and should be handled with care.
Electro-Static Discharge Test (Condition: Human body model, the number of samples is three.)
U, V, W, and IS2 pins are passed +2kV/-1.5kV and other pins are passed +2kV/-2kV in this test.
(Common pins: Power supply pins (VCC and VBB) or GND pins (SGND and PGND))
© 2017-2018
Toshiba Electronic Devices & Storage Corporation
1
2018-02-02
TB67B000FG
Block Diagram
OSCR
5
System clock
generator
TR
4
Vrefout
28
Lock
detection
VREG
23
VCC
25
VBB
11
Voltage
Regulator
(5V)
16 BSU
15 BSV
HUP 3
13 BSW
Under voltage
lockout
HUM 2
HVP 34
Voltage
Regulator
(7V)
HVM 33
HWP 32
Under
voltage
lockout
HWM 31
Control circuit
LA 7
High-side
level shift
driver
UH
Output circuit
Input/Output
circuit
Input protection
logic
VH
VL
WL
CW/CCW 26
14 V
shutdown
12 W
Low-side
driver
WH
FGC 30
17 U
Thermal
UL
VSP 8
FG 9
Under Under Under
voltage voltage voltage
lockout lockout lockout
SS 29
20 NC
(Controller)
21 NC
(Driver)
24 NC
27
Idc
1
EPAD
6
SGND
2
22
PGND
19
IS1
18
IS2
10
IS3
2018-02-02
TB67B000FG
Pin Assignment
EPAD
1
HUM
2
HUP
3
TR
4
OSCR
5
SGND
6
LA
7
VSP
8
FG
9
VBB
IS3
10
W
11
BSW
V
BSV
12
13
14
15
19
18
17
16
(Die pad)
34
HVP
33
HVM
32
HWP
31
HWM
30
FGC
29
SS
28
Vrefout
27
Idc
26
25
CW/CCW
VCC
24
NC
23
VREG
22
PGND
21
NC
20
NC
IS1
IS2
U
BSU
Note: Die pad on the package surface and EPAD pin (a pin number is 1.) are connected. When using the heat
sink, handle it not to short with the IC pins.
3
2018-02-02
TB67B000FG
Pin Description
Pin No.
Symbol
Description
Function
9
FG
FG signal output
FGC = H: FG = output 1 ppr
FGC = M: FG = output 2.4 ppr
FGC = L: FG = output 3 ppr
8
VSP
Voltage command input
This pin has a pull-down resistor. (150 kΩ)
Lead angle control input
This pin has a pull-down resistor. (200 kΩ)
Input voltage range: 0 to 5.0V
SS=H: 0 to 28° in 16 steps.
SS=L: 0 to 58° in 32 steps.
*ppr : one pulse per one electrical angle
7
LA
5
OSCR
Resistor for oscillation
Connect a resistor for internal clock oscillation.
4
TR
Motor lock detection
Connect a capacitor for motor lock detection oscillation or connect to GND.
3
HUP
U-phase hall input+
2
HUM
U-phase hall input-
34
HVP
V-phase hall input+
33
HVM
V-phase hall input-
32
HWP
W-phase hall input+
31
HWM
W-phase hall inputFG output signal switch
When the hall signal inputs (UVW) are all Highs or all Lows, the gate block
protection becomes active. Built-in digital filter (≈1.6 μs)
This pin has a pull-down resistor. (100 kΩ)
H: FG=output 1 ppr
M: FG=output 2.4 ppr
L: FG=output 3 ppr
*ppr : one pulse per one electrical angle
30
FGC
28
Vrefout
29
SS
26
CW/CCW
Forward/Reverse
switching input
This pin has a pull-down resistor. (100 kΩ)
H: Forward
L: Reverse
27
Idc
Current limit input
This pin has a pull-up resistor. (200 kΩ)
DC link input
Reference potential of 0.5 V. This pin has a RC filter (≈ 1 μs) and a digital
filter (≈ 0.6 μs).
6
SGND
Ground pin
Signal ground.
Connect with PGND and EPAD pin.
23
VREG
Reference voltage output 7 V (typ.), 30 mA (max). Connecting a capacitor for voltage stability.
25
VCC
22
PGND
17
U
Reference voltage output 5 V (typ.), 35 mA (max), Connecting a capacitor for voltage stability.
This pin has a pull-down resistor. (100 kΩ)
Switch for commutation
H: Wide-angle commutation (150° commutation)
waveform
L: Sine-wave PWM drive (180° commutation)
Power supply pin for the
15 V (typ.)
power stage
Ground pin
Power ground
Connect with SGND and EPAD pin.
U-phase output pin
―
16
BSU
Bootstrap supply
(phase U)
19
IS1
U-phase IGBT emitter
For connecting a detecting resistor for motor coil current to the PGND pin.
18
IS2
V-phase IGBT emitter
For connecting a detecting resistor for motor coil current to the PGND pin.
15
BSV
Bootstrap supply
(phase V)
For connecting a bootstrap capacitor to the V-phase output.
14
V
V-phase output pin
11
VBB
High-voltage power
supply pin
Power supply pin for driving a motor.
13
BSW
Bootstrap supply
(phase W)
For connecting a bootstrap capacitor to the W-phase output.
12
W
W-phase output pin
10
IS3
W-phase IGBT emitter
20/21/24
NC
Non connection pin
1
EPAD
Die pad connected pin
For connecting a bootstrap capacitor to the U-phase output.
―
―
For connecting a detecting resistor for motor coil current to the PGND pin.
―
This pin is connected with die pad on surface.
Connect with PGND and SGND.
4
2018-02-02
TB67B000FG
Input/Output Equivalent Circuits
Equivalent circuit diagrams may be partially omitted or simplified for explanatory purposes.
Pin
Input/Output Signal
Internal Circuit
HUP
HUM
Vrefout Vrefout
Analog / Digital
HVP
HVM
Hysteresis: ±7.5 mV (typ.)
HWP
Digital filter time constant: 1.6 μs (typ.)
HWM
Vrefout
76 kΩ
224 kΩ
Analog
VSP
Vrefout
VSP voltage range: 0 to 10 V
Internal pull-down resistor: 150 kΩ
Vrefout
Digital
SS
L : 0.8 V (max)
H: Vrefout - 1 V (min)
100 kΩ
CW/CCW
140 kΩ
160 kΩ
Internal pull-down resistor: 100 kΩ
Vrefout
Analog
100 kΩ
LA voltage range: 0 to 5.0 V
100 kΩ
LA
Internal pull-down resistor: 200 kΩ
Analog filter time constant: 1.0 μs (typ.)
Digital filter time constant: 0.6 μs (typ.)
200 kΩ
5 pF
Idc
Vrefout Vrefout
200 kΩ
Analog
Internal pull-up resistor: 200 kΩ
Vrefout
Digital
L : 0.8 V (max)
M: 2.0 V(min), 3.0 V(max)
H: Vrefout - 1 V (min)
50 kΩ
50 kΩ
FGC
0.5 V
Internal pull-down resistor: 100 kΩ
5
2018-02-02
TB67B000FG
Pin
Input/Output Signal
Internal Circuit
Vrefout
Digital
Vrefout
Push-pull output: ±2 mA (max)
FG
FGC=H: 1 ppr
FGC=M: 2.4 ppr
FGC=L: 3 ppr
VBB
U
V
W
IS1
U
U,V,W-phase output pin
U,V,W-phase IGBT emitter pin
V
W
IS2
IS3
IS1
6
IS2
IS3
2018-02-02
TB67B000FG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
VBB
500
VCC
18
Vin (1)
- 0.3 to VCC (Note 1)
Vin (2)
- 0.3 to Vrefout +0.3 (Note 2)
Output current (DC)
IOUT
2
A
Output current (pulse 1ms)
IOUTP
3 (Note 3)
A
VREG current
Ireg
30
mA
Vrefout current
Irefout
35
mA
Power dissipation
PD
35 (Note 4)
W
Operating temperature
Topr
- 30 to 115 (Note 5)
°C
Storage temperature
Tstg
- 55 to 150
°C
Power supply voltage
Input voltage
Unit
V
V
Note: Absolute maximum ratings
The maximum rating is the rating that should never be exceeded, even for a shortest of moments. If the
maximum rating is exceeded, it could result in damage and/or deterioration of the IC as well as other
devices beside the IC. Regardless of the operating conditions, please design so that the maximum rating
is never exceeded. Please use within the specified operating range.
Note 1: Vin (1) pin: VSP and LA
Note 2: Vin (2) pin: HUP, HUM, HVP, HVM, HWP, HWM, SS, FGC, CW/CCW, and Idc.
Note 3: Apply pulse
Note 4: Package thermal resistance (θ j-c = 1°C/W) with an infinite heat sink at Ta = 25°C
Note 5: The operating temperature range is determined according to the ‘PD MAX – Ta characteristics’.
Operating Conditions (Ta = 25°C)
Characteristics
Symbol
Min
Typ.
Max
VBB
50
280
450
VCC
13.5
15
16.5
Oscillation frequency
fosc
3.5
5
6.4
MHz
Output current
Iout
―
―
2
A
Operating temperature
Topr
―
115
(Note)
°C
Power supply voltage
- 30
(Note)
Unit
V
Note: The operating temperature range is determined according to the ‘PD MAX - Ta characteristics’.
7
2018-02-02
TB67B000FG
Power Dissipation
PD MAX – Ta
Power dissipation PD MAX (W)
40
(1)
30
20
10
(2)
(3)
(4)
0
0
25
50
75
100
125
150
Ambient temperature Ta (°C)
(1) Infinite heat sink
：Rθj-c = 1°C/W
(2) Mounting on PCB (74.2 × 114.3 × 1.6 mm, Cu20%)、heat sink (10 × 10 × 1 mm, Cu)
：Rθj-a = 21°C/W
(3) Mounting on PCB without heat sink (74.2 × 114.3 × 1.6 mm, Cu20%)
：Rθj-a = 37°C/W
(4) IC only
：Rθj-a = 68°C/W
8
2018-02-02
TB67B000FG
Electrical Characteristics (Ta = 25°C)
Characteristics
Current dissipation
Current consumption of
bootstrap
Symbol
Test Condition
VBB = 450 V
―
―
0.5
VCC = 15 V
―
5
10
IBS (ON)
VBS = 15 V, high-side ON
―
210
410
IBS (OFF)
VBS = 15 V, high-side OFF
―
180
370
Vin = 5 V, LA
―
25
50
IIN(VSP)
Vin = 5 V, VSP
―
35
70
IIN(Idc)
Vin = GND, Idc
―
-25
-50
Vin = 5 V, CW/CCW, FGC, SS
―
50
100
Vrefout
−1
―
Vrefout
L
0
―
0.8
H
4
―
Vrefout
2
―
3
VIN1
VIN2
H
M
CW/CCW, SS
FGC
L
Input
hysteresis
V
8.2
―
10
H
PWM ON duty 95%
SS=H
5.1
5.4
5.7
M
Refresh → Start motor operation,
SS=H
1.8
2.1
2.4
L
Turned-off → Refresh
SS=H
0.7
1.0
1.3
T
Test mode for motor shipping
SS=L
8.2
―
10
H
PWM ON duty 92%
SS=L
5.1
5.4
5.7
M
Refresh → Start motor operation,
SS=L
1.8
2.1
2.4
L
Turned-off → Refresh
SS=L
0.7
1.0
1.3
FC (20)
OSC/R = 68 kΩ
18
20
22
FC (18)
OSC/R = 75 kΩ
16.2
18
19.8
TONTR
TR=0.01 μF Driving time
(Note )
3.33
5
8.33
s
TOFFTR
TR=0.01 μF Turn off time
(Note )
20
30
46.15
s
TR=0.01 μF frequency
65
100
150
Hz
LA = 0 V or Open, Hall IN = 100 Hz
SS=H
―
0
―
V
V
kHz
TLAH(2.5)
LA = 2.5 V, Hall IN = 100 Hz
SS=H
11.25
15
18.75
TLAH (5)
LA = 5 V, Hall IN = 100 Hz
SS=H
26.25
28.125
―
TLAL(0)
LA = 0 V or Open, Hall IN = 100 Hz
SS=L
―
0
―
LA = 2.5 V, Hall IN = 100 Hz
SS=L
26
30
33
LA = 5 V, Hall IN = 100 Hz
SS=L
52
57
60
VS
Difference input
40
―
―
mVpp
VW
―
0.5
―
4.0
V
±1.5
±7.5
±13.5
mV
TLAL (5)
In-phase
Hall device input range
V
T
TLAL (2.5)
Input
sensitivity
μA
1
TLAH(0)
Lead angle offset
μA
―
FTR
Lead angle offset (LA)
mA
0
VSP(L)
Motor lock detection
Unit
Test mode for motor shipping
SS=H
VSP(H)
PWM oscillation frequency
(Carrier frequency)
Max
IBB
IIN(1)
Input voltage
Typ.
ICC
IIN(LA)
Input current
Min
(Note)
VH(1)
9
2018-02-02
°
°
TB67B000FG
Hall IC input
Current detection
Output voltage
Output saturated voltage
Forward voltage of FRD
Forward voltage of BSD
Thermal shutdown threshold
H
VIN4
L
Vdc
HUP, HVP, HWP:
HUM, HVM, HWM = Vrefout/2
Idc
Vrefout
−1
―
Vrefout
0
―
0.8
0.475
0.5
0.525
VFG (H)
IOUT = 2 mA
FG
4
―
―
VFG (L)
IOUT = −2 mA
FG
―
―
1
Vrefout1
IOUT = 15 mA
Vrefout
4.7
5.0
5.3
Vrefout2
IOUT = 35 mA
Vrefout
4.5
5.0
5.3
VREG
IOUT = 30 mA
VREG
6.5
7
7.5
VCEsatH
VCC = 15 V, IC = 1 A, High side
―
2.3
3.2
VCEsatL
VCC = 15 V, IC = 1 A, Low side
―
2.3
3.2
VFH
IF = 1 A, High side
―
2.1
3.1
VFL
IF = 1 A, Low side
―
2.1
3.1
VF (BSD)
IF = 500 μA
TSD
(Note )
TSDhys
―
0.9
1.2
135
―
185
―
50
―
V
V
V
V
V
V
°C
VCC Undervoltage lockout
(Driver)
VCC (H)
Undervoltage positive-going threshold
10.5
11.5
12.5
VCC (L)
Undervoltage negative-going threshold
10
11
12
VBS Undervoltage lockout
(Driver)
VBS (H)
Undervoltage positive-going threshold
8.5
9.5
10.5
VBS (L)
Undervoltage negative-going threshold
8
9
9.5
ton
VBB = 280 V, VCC = 15 V, IC = 1 A
―
1.2
3
toff
VBB = 280 V, VCC = 15 V, IC = 1 A
―
1
3
Idc (fosc = 5 MHz)
―
3.5
―
μs
VBB = 280 V, VCC = 15 V, IC = 1 A
―
150
―
ns
Output delay time
Input delay time
FRD reverse recovery time
TDC
trr
Note: No shipping inspection.
10
2018-02-02
V
V
μs
TB67B000FG
Functional Description
1.
Basic Operation
The motor is driven by 120° commutation at startup. When the hall signal detects the motor rotating at the
frequency of 1 Hz or higher, the rotor position is estimated and the motor is driven with the lead angle
based on the LA input voltage.
From start to 1 Hz: Driven by square wave (120° commutation)
1 Hz or higher:
Driven by sine-wave PWM (180° commutation) or wide-angle commutation
(150° commutation)
When fosc = 5 MHz, approx. 1 Hz.
*: When f is 1 Hz or higher, the motor is driven by the command of the LA pin.
When f is 1 Hz or less or the motor is driven with reverse rotation direction (according to the timing
chart), it is driven by 120° commutation (lead angle is 0°).
Driven system (sine-wave PWM or wide-angle commutation) can be switched by the SS pin. Setting of lead
angle is different between these driving systems.
2.
SS=L
SS
Driving system
Lead angle
L
Sine-wave PWM drive
(180° commutation)
0 to 58° / 32 steps
H
Wide-angle commutation
(150° commutation)
0 to 28° / 16 steps
Voltage Command (VSP) Signal and Bootstrap Voltage Regulation
(1)
When VSP ≤ 1.0 V:
The commutation signal outputs are disabled (i.e., gate protection is activated).
(2)
When 1.0 V < VSP ≤ 2.1 V:
The low-side transistors are turned on at a regular (PWM carrier) frequency. (ON duty: 18/fosc)
(3)
When 2.1 V < VSP ≤ 7.3 V:
During sine-wave PWM drive, the commutation signals directly appear externally. During
square-wave drive, the low-side transistors are forced on at a regular (PWM carrier) frequency. (ON
duty: 18/fosc)
In stop state (Forward: 1Hz or less, Reverse: 5 Hz or less), commutation signals are outputted after
VSP (VSP > 2.1 V) is inputted and the refresh function operates for 1.5ms (typ.). In operation state
(Forward: more than 1Hz, Reverse: more than 5 Hz), commutation signals are outputted after VSP
(VSP > 2.1 V) is inputted.
Note: In startup, low-side transistor should be turned on (1.0 V < VSP ≤ 2.1 V) for a certain period to charge
gate power supply of high-side transistors.
(4)
When 8.2 V ≤ VSP ≤ 10 V (test mode for motor shipping):
The TB67B000FG drives in sine-wave drive mode with lead angle of zero. However, it drives in
square-wave mode in detecting reverse rotation.
When VSP reaches 7.9 V (typ.), lead angle switches to zero.
The PWM duty cycle is calculated as PWM carrier period × 92% (typ.) and kept the constant value at
the following condition; 5.4 V (typ.) ≤ VSP.
PWM Duty
92%
1.0 V
(1)
2.1 V
(2)
5.4 V
(3)
11
7.3 V 8.2 V
10 V
VSP
(4)
2018-02-02
TB67B000FG
SS=H
(1)
When VSP ≤ 1.0 V:
The commutation signal outputs are disabled (i.e., gate protection is activated).
(2)
When 1.0 V < VSP ≤ 2.1 V:
The low-side transistors are turned on at a regular frequency (PWM carrier frequency). (ON duty:
18/fosc)
(3)
When 2.1 V < VSP ≤ 7.3 V:
During wide-angle commutation, the commutation signals directly appear externally. During
square-wave drive, the low-side transistors are forced on at a regular (PWM carrier) frequency. (ON
duty: 18/fosc)
In stop state (Forward: 1Hz or less, Reverse: 5 Hz or less), commutation signals are outputted after
VSP (VSP > 2.1 V) is inputted and the refresh function operates for 1.5 ms (typ.). In operation state
(Forward: more than 1Hz, Reverse: more than 5 Hz), commutation signals are outputted after VSP
(VSP > 2.1 V) is inputted.
Note: In startup, low-side transistor should be turned on (1.0 V < VSP ≤ 2.1 V) for a certain period to charge
gate power supply of high-side transistors.
(4)
When 8.2 V ≤ VSP ≤ 10 V (test mode for motor shipping):
The TB67B000FG drives in wide-angle commutation mode with lead angle of zero. However, it drives
in square-wave mode in detecting reverse rotation.
When VSP reaches 7.9 V (typ.), lead angle switches to zero.
The PWM duty cycle is calculated as PWM carrier period × 95% (typ.) and kept the constant value at
the following condition; 5.4 V (typ.) ≤ VSP.
PWM Duty (Upper phase)
*95%
(typ.)
*2.4%
(typ.)
1.0 V
(1)
2.1 V
(2)
5.4 V
(3)
7.3 V 8.2 V
10 V
VSP
(4)
*: Maximum ON duty: Ton = 95% (typ.) when VSP = 5.4 V (typ.)
Minimum ON duty: Ton = 2.4% (typ.) when VSP = 2.1 V (typ.).
Ex.: When fosc = 5 MHz, maximum ON time = 48 μs (typ.) (fc = 19.8 kHz)
minimum ON time = 1.2 μs (typ.) (fc = 19.8 kHz)
12
2018-02-02
TB67B000FG
3.
Dead Time Insertion (cross conduction protection)
To prevent a short-circuit between low-side and high-side power devices during sine-wave PWM drive, a
dead time is digitally inserted between the turn-on of one side and the turn-off of the other side. (The dead
time is also implemented at the full duty cycle during square-wave drive.)
Td = 9/fosc
When fosc = 5 MHz, Td ≈ 1.8 μs (9/fosc)
fosc = reference clock (CR oscillation frequency)
UH
(VH, WH)
Td
UL
(VL, WL)
Td
When input voltage (VSP) is more than 2.1 V and the hall signal frequency is 1 Hz or less, the upper phase
(UH, VH, and WH) operates PWM drives (according to VSP) with120° commutation. And the lower phase
(UL, VL, and WL) operates with 120° commutation. It refreshes in off timing. (In case of reverse direction
drive, the operation is the same as forward direction drive.)
Output waveform (Image)
UH
UL
VH
VL
WH
WL
Enhanced
WH
TSP
Td
WL
Td
Ton
TSP: Changeable by VSP. (The condition in this figure: VSP = 5.4 V (typ.)), Ton = 18/fosc, Td = 9/fosc.
*: Lead angle offset (LA pin) is not activated when hall signal frequency is 1 Hz or less. The lead angle is
also deactivated in detecting of reverse rotation.
4.
Lead Angle Control
The lead angle can be adjusted between 0° and 58° according to the induced voltage level on the LA input.
SS=L
SS=H
LA analog input (0 to 5 V in 32 separate steps.)
0 V = 0°
5 V = 58° (A lead angle of 58° is assumed when the LA voltage exceeds 5 V.)
LA analog input (0 to 5 V in 16 separate steps).
0 V = 0°
5 V = 28° (A lead angle of 28° is assumed when the LA voltage exceeds 5 V.)
13
2018-02-02
TB67B000FG
5.
PWM Carrier Frequency
The triangular waveform generator provides a carrier frequency of fosc/252 necessary for PWM generation.
(The triangular wave is also used to force the switch-on of low-side transistors during square-wave drive.)
Carrier frequency: FC = fosc/252 (Hz), where fosc = reference clock (CR oscillator) frequency
6.
Position Detecting Pin
VW is 0.5 to 4.0 V in in-phase range. Input hysteresis voltage (VH) is 7.5 mV (typ.).
VH = 7.5 mV (typ.)
VS
VH
HUM
VH
VS = 40 mV or more
HUP
Usage conditions: HUP, HVP, and HWP = GND to Vrefout
HUM, HVM, and HWM = Vrefout / 2
7.
Rotating Pulse Output
The TB67B000FG outputs rotating pulse based on the hall signal. FGC pin can switch one pulse per
electrical angle, 3 pulses per electrical angle, or 2.4 pulses per electrical angle. One pulse per electrical
angle is generated from the hall signal of U phase. 3 pulses per electrical angle are generated by combining
each rising and falling edge of U, V, and W phases.
When the pulse is outputted at 2.4 pulses per electrical angle (FGC=M), FG pin outputs L level under the
condition that the direction of motor rotating is forward or reverse at 1 Hz or less. It is outputted
regardless of the input voltage of VSP.
FGC
FG
H
1 pulse per electrical angle
M
2.4 pulses per electrical angle (2 pulses per 5/6 electrical angle)
L
3 pulses per electrical angle
Timing Chart of FG Signal
HUM
HUP
HVM
HVP
HWP
HWM
FGC = L
FGC = M
FGC = H
14
2018-02-02
TB67B000FG
8.
Protection-related Functions
(1)
Overcurrent protection (Idc pin)
If the DC-link current exceeds the corresponding internal reference voltage, the gate block is
activated and the commutation signals (U, V, and W) are forced off. Overcurrent protection is disabled
after every carrier period.
Reference voltage = 0.5 V (typ.)
(2)
Abnormal hall signal protection
When the hall signals (internal hall amplifier outputs) are all Highs or all Lows, or hall input signals
(HUP, HUM, HVP, HVM, HWP, and HWM) are all open, the commutation outputs (U, V, and W) are
forced off. When these inputs are then set to any other combination, the commutation outputs are
re-enabled.
(3)
Undervoltage lockout (VCC)
While the power supply voltage is outside the rated range during power-on or power-off, the
commutation outputs (U, V, and W) are forced off to stop the motor operation. The motor operation in
power recovery is not guaranteed because the state of the circuit becomes unstable by power on
sequence.
Supply voltage
11.5 V (typ.)
11.0 V (typ.)
VCC: 15V(typ.)
GND
VBB
Drive output
Output OFF
(4)
Output OFF
Output drive
Monitor for VBS bootstrap power supply
When VBS power supply falls, high-side of IGBT output is turned off.
VBS (Output-BS)
9.5 V (typ.)
9.0 V (typ.)
High-side IGBT
Output OFF
(5)
Output drive
Output OFF
Thermal shutdown circuit
When the IC temperature rises high abnormally because of internal or external heat generation, all
outputs of IGBT are tuned off.
TSD = 135°C (min), 185°C (max)
TSDhys = 50°C (typ.)
Recovery temperature after TSD is activated: TSD -TSDhys
15
2018-02-02
TB67B000FG
9.
Motor-lock Detection
When hall signal detects below state, intermitted operation (drive period: stop period = 1: 6) is repeated.
When VSP exceeds 2.1 V, the detection period starts. In this time, the counter for the motor lock detection
starts counting. When direction of the motor rotation corresponds to the pin configuration (forward direction:
sine-wave PWM mode or wide-angle commutation mode), lock detection is activated with 120° commutation
(square-wave drive) under the condition that frequency of the hall signal is about 1 Hz or less (when fosc =
5 MHz).
When direction of motor rotation is opposed against pin setting direction (reverse direction: reverse hall
input in 120° commutation mode), lock detection is activated under the condition that frequency of the hall
signal is about 5 Hz or less (when fosc = 5 MHz).
When lock detection enables, operation is turned off (output drive is OFF) during stop period.
When VSP is set 1.0 V or less, counter is reset and the stop mode is released. Then, when VSP is set 2.1 V or
more again, counter starts counting from the initial state.
Table of lock detection
VSP pin > 2.1V
Direction of motor rotation
CW/CCW pin
CW
Hall ≤ 1 Hz
(Rotating direction:
set of CW/CCW pin = motor)
Hall ≤ 5 Hz
(Rotating direction:
set of CW/CCW pin ≠ motor)
H (CW)
L (CCW)
Hall U
Hall V
Hall W
CCW
Hall ≤ 5 Hz
(Rotating direction:
set of CW/CCW pin ≠ motor)
Hall ≤ 1 Hz
(Rotating direction:
set of CW/CCW pin = motor)
120° commutation →wide-angle commutation
120° commutation→sine-wave drive
(Hall > 1 Hz)
Inactive
Inactive
Counter reset
Counter start
VSP>2.1V
(typ.)
Oscillation
Counter
Drive output
control
C1
TR
―
Counter reset
VSP
