TB67S105FTG
Toshiba BiCD process integrated circuit silicon monolithic
TB67S105FTG
8bit Serial controlled bipolar stepping motor driver
1. Outline
The TB67S105FTG is a two phase bipolar stepping motor driver
using a PWM chopper, controlled by 8-bit serial data.
Fabricated by the BiCD process, the TB67S105FTG is rated
at 50V/3.0A.
The internal voltage regulator allows to control the device
with a single VM power supply.
P-WQFN48-0707-0.50-003
Weight: 0.12g (typ.)
2. Features
BiCD process integrated monolithic IC.
Capable of controlling one bipolar stepping motor.
Low on-resistance MOSFET output stage.
High voltage and current (for specification, please refer to the absolute maximum ratings and operation ranges).
Built-in serial-parallel convert circuit (8bit shift register)
3-line (Data, Clock, Latch) serial output function for cascade connection
PWM controlled constant-current drive.
Allows full and half step operation
4 bit (16 steps) adjustable torque function (TRQ1, TRQ2, TRQ3, TRQ4).
Built-in error detection circuits (Thermal shutdown (TSD), over current shutdown (ISD), and power on reset(POR)).
Built-in VCC regulator for internal use.
Chopping frequency of a motor can be customized by external resistor and capacitor.
Package type: P-WQFN48-0707-0.50-003
Note) Please be careful about thermal conditions during use.
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TB67S105FTG
3. Pin assignment
NC
OUT_B＋
OUT_B＋
NC
RS_B
NC
RS_B
VM
NC
VCC
L_OUT
NC
(Top View)
36 35 34 33 32 31 30 29 28 27 26 25
NC
37
24 NC
C_OUT
38
23 NC
D_OUT
39
22 GND
GND
40
21 OUT_B－
VREF_B
41
20 OUT_B－
VREF_A
42
OSCM
43
18 GND
NC
44
17 OUT_A－
SI 45
16 OUT_A－
19 GND
TB67S105FTG
6
7
8
9 10 11 12
NC
GND
5
OUT_A＋
4
OUT_A＋
3
NC
2
RS_A
1
NC
13 NC
RS_A
NC 48
STANDBY
14 NC
G－
RCK 47
SCLR－
15 GND
NC
SCK 46
Please solder the four corner pins of the QFN package and the exposed pad to the GND area of the PCB.
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TB67S105FTG
4. Pin explanations
Pin No.1 to 28
Pin No.
Pin Name
Function
1
NC
2
SCLR－
3
G－
4
STANDBY
Standby pin
5
GND
Ground pin
6
NC
7
RS_A(*)
Motor Ach current sense pin
8
RS_A(*)
Motor Ach current sense pin
9
NC
10
OUT_A＋(*)
Motor Ach (+) pin
11
OUT_A＋(*)
Motor Ach (+) pin
12
NC
Non-connection pin
13
NC
Non-connection pin
14
NC
Non-connection pin
15
GND
16
OUT_A－(*)
Motor Ach (-) pin
17
OUT_A－(*)
Motor Ach (-) pin
18
GND
Ground pin
19
GND
Ground pin
20
OUT_B－(*)
Motor Bch (-) pin
21
OUT_B－(*)
Motor Bch (-) pin
22
GND
23
NC
Non-connection pin
24
NC
Non-connection pin
25
NC
Non-connection pin
26
OUT_B＋(*)
Motor Bch (+) pin
27
OUT_B＋(*)
Motor Bch (+) pin
28
NC
Non-connection pin
Serial register clear pin (low active)
Serial data select pin
(low active)
Non-connection pin
Non-connection pin
Ground pin
Ground pin
Non-connection pin
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Pin No.29 to 48
Pin No.
Pin Name
Function
29
RS_B(*)
Motor Bch current sense pin
30
RS_B(*)
Motor Bch current sense pin
31
NC
Non-connection pin
32
VM
Motor power supply pin
33
NC
Non-connection pin
34
VCC
35
L_OUT
36
NC
Non-connection pin
37
NC
Non-connection pin
38
C_OUT
Serial ‘Clock’ output pin
39
D_OUT
Shift register data output pin
40
GND
41
VREF_B
Motor Bch output current set pin
42
VREF_A
Motor Ach output current set pin
43
OSCM
44
NC
Non-connection pin
45
SI
Serial ‘Data’ input pin
46
SCK
Serial ‘Clock’ input pin
47
RCK
Serial ‘Latch’ input pin
48
NC
Internal VCC regulator monitor pin
Serial ‘Latch’ output pin
Ground pin
Oscillating circuit frequency for PWM chopping set pin
Non-connection pin
Note)
Please do not run patterns under NC pins.
(*) Please connect the pins with the same pin name.
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TB67S105FTG
5. Block diagram
SCK
C_OUT
RCK
L_OUT
SI
D_OUT
GSCLR-
8bit shift register
Serial-Parallel Interface
Oscillator (Motor)
OSCM
Internal Oscillator
STANDBY
Main control logic
TSD
ISD
POR
VCC REG
VCC
VM
Torque control
RS_A
RS Comp A
H-Bridge A
NF level set
VREF_A
H-Bridge A
Predriver
VREF Comp A
Motor H-Bridge A
(Pch+Nch MOSFET)
OUT_A+
OUT_A-
RS_B
RS Comp B
H-Bridge B
NF level set
VREF_B
H-Bridge B
Predriver
VREF Comp B
Motor H-Bridge B
(Pch+Nch MOSFET)
OUT_B+
OUT_B-
GND
Functional blocks/circuits/constants in the block diagram may be omitted or simplified for explanatory purposes.
All the grounding wires of the TB67S105FTG must run on the solder mask on the PCB, and be externally connected at a
single point. Also, the grounding method should be considered for efficient heat dissipation.
Careful attention should be paid to the layout of the output, VM and GND traces, to avoid short circuits across output pins
or to the power supply or ground. If such a short circuit occurs, the device may be permanently damaged.
Also, the utmost care should be taken for pattern designing and implementation of the device since it has power supply
pins (VM, RS_x+, RS_x-, OUT_x+, OUT_x-, GND (x=A or B)) through which a particularly large current may run. If these
pins are wired incorrectly, an operation error may occur or the device may be destroyed.
The logic input pins must also be wired correctly. Otherwise, the device may be damaged owing to a current running
through the IC that is larger than the specified current.
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Output current feedback circuit, current setting circuit
Note: Logic pins are either pulled up or pulled down internally by 100kohm resistor. Please refer to the equivalent circuit.)
Reference
Chopping circuit
Decay
Mode
Output control circuit
NF detect
Signal
Current
feedback
circuit
OSCM
Counter
Mixed
Decay
Timing
Charge start
Output stop
U1
signal
U2
Output control
L1
circuit
L2
Current
setting
circuit
Mixed
Decay
Timing
Circuit
OSC selector
Output stage
Output Stop
signal
Detection functions
Output stage
VM
VCC
ISD
circuit
VMR
circuit
Stop
Signal
Select
circuit
VCCR
circuit
TSD
circuit
ISD : Over current
detection
TSD : Over thermal
TSD(Over temperature detection)circuit: When
the temperature of the IC exceeds the
threshold, the output stage will turn OFF.
Reapplying the VM again from 0V or setting the
STANDBY to H→L→H will reset the TSD.
VMR(VM monitor)circuit: Detects H when VM is
above the threshold, and detects L when VM is
below the threshold.
VCCR: VCC monitor
VMR : VM monitor
ISD(Over current detection)circuit：When the
current exceeds the threshold, the output stage
will turn OFF. Reapplying the VM again from 0V
or setting the STANDBY to H→L→H will reset
the ISD.
Detection
Circuit
VCCR(VCC monitor)circuit: Detects H when
VCC is above the threshold, and detects L when
VCC is below the threshold.
Detection circuit
Latch clear
signal
Logic
detection
POR(Power On Reset)circuit: When both VMR
and VCCR is above the threshold the logic
becomes active. When both or either VMR or
VCCR is below the threshold, the logic is
stopped.
Functional blocks/circuits/constants in the block diagram may be omitted or simplified for explanatory purposes.
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TB67S105FTG
6. INPUT/OUTPUT equivalent circuit
Pin Name
SCLRSTANDBY
SI
SCK
RCK
Input/output equivalent circuit
SCLRSTANDBY
SI
SCK
RCK
OSCM
OSCM
VREF_A
VREF_B
VREF_A
VREF_B
GG-
L_OUT
C_OUT
D_OUT
L_OUT
C_OUT
D_OUT
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Pin Name
Input/output equivalent circuit
RS_A
RS_B
OUT_A+
OUT_AOUT_B+
OUT_BRS_A
RS_B
OUT_A+
OUT_B+
OUT_AOUT_B-
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
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7. Control mode/Function explanation
Serial control interface (8bit shift register+8bit storage register)
SCK
C_OUT
SDN
RCK
D_OUT
Qh
SCLR-
8 bit shift register
Qa
Qb
Qc
Qd
Qe
Qf
Qg
SI
D_OUT
synchronous
8 bit storage register
QH
QG
QE
QD
QB
QF
TRQ4
TRQ3
TRQ2
TRQ1
ENABLE_B
PHASE_B
PHASE_A
ENABLE_A
Logic input gate
G-
STANDBY
QC
QA
L_OUT
Motor Control Logic
The block diagram and equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
If the logic signal is not asserted, the initial status of the logic pins will be as shown below.
SCK: Low
SI: Low
SCLR-: Low (shift register and storage register are at the initial status.)
RCK: Low
G-: High (PHASE_A, ENABLE_A, PHASE_B, ENABLE_B, TRQ1, TRQ2, TRQ3, TRQ4=Disable)
STANDBY: Low (Standby mode)
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Truth table
Input
Function
SI
SCK
SCLR-
RCK
G-
X
X
X
X
H
PHASE_A, ENABLE_A, PHASE_B, ENABLE_B, TRQ1, TRQ2, TRQ3,
TRQ4=Disable
X
X
X
X
L
PHASE_A, ENABLE_A, PHASE_B, ENABLE_B, TRQ1, TRQ2, TRQ3,
X
X
L
X
X
Shift register and storage register are initialized
L
↑
H
X
X
The first data of the shift register is L, and the other register will be stored with
the data before.
H
↑
H
X
X
The first data of the shift register is H, and the other register will be stored with
the data before.
X
↓
H
X
X
The shift register data will maintain its status. The data after the shift register(Qh)
will be output from D_OUT pin.
X
X
H
↑
X
Shift register data will be stored to the storage register.
TRQ4=Enable
(The storage register data will maintain its status.)
X
X
H
↓
X
X: Don’t care
Note) To send the logic output data correctly to the next IC, please make sure to end the SCK data transfer with a
Low signal.
Function explanation
The motor current is defined as plus when the current flows from OUT_X+ to OUT_X-, and defined minus when the
current flows from OUT_X- to OUT_X+.
Signal
ENABLE_X
PHASE_X
STANDBY
H
L
OUTPUT: ON
OUTPUT: OFF
When ENABLE_X is set to L, no matter what the PHASE
status are, the corresponding output stage will be set OFF(Hiz).
OUT_X+: H
OUT_X+: L
OUT_X-: L
OUT_X-: H
When set to H, the current will flow from OUT_X+ to OUT_Xat charge status.
Motor operational
Standby mode
When STANDBY is set to L, the internal OSC circuit as well as
output stage is set OFF; therefore the motor will not operate.
(X=A or B)
Internal signal and current ratio
[Full step]
Ach
Internal signal
PHASE_A
H
L
L
H
ENABLE_A
H
H
H
H
Bch
Internal signal
PHASE_B
H
H
L
L
Output
IOUT_A
+100%
-100%
-100%
+100%
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ENABLE_B
H
H
H
H
Output
IOUT_B
+100%
+100%
-100%
-100%
2022-01-07
TB67S105FTG
[Half step]
Ach
Internal signal
PHASE_A
H
X
L
L
L
X
H
H
Bch
Internal signal
PHASE_B
H
H
H
X
L
L
L
X
Output
IOUT_A
+100%
0%
-100%
-100%
-100%
0%
+100%
+100%
ENABLE_A
H
L
H
H
H
L
H
H
ENABLE_B
H
H
H
L
H
H
H
L
Output
IOUT_B
+100%
+100%
+100%
0%
-100%
-100%
-100%
0%
X: Don’t care
TRQ function: Current Ratio
TRQ1
TRQ2
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
TRQ3
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
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TRQ4
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
11
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Current Ratio(%)
0
5
10
15
25
29
38
43
52
60
67
74
80
86
94
100
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TB67S105FTG
9．Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Motor power supply
Motor output voltage
Motor output current
Internal VCC voltage
Logic input voltage
Logic output current
VREF input voltage
Power dissipation
Operating temperature
Storage temperature
Junction temperature
Symbol
VM
VOUT
IOUT
VCC
VIH
IOH
IOL
VREF
PD
TOPR
TSTR
Tj(max)
Rating
50
50
3
6
6
-7
7
5
1.3
-20 to 85
-55 to 150
150
Unit
V
V
A
V
V
mA
mA
V
W
°C
°C
°C
Note
Note 1
Note 2
Note 3
-
Note 1: Usually the maximum current value should be controlled below 80% or less of the absolute maximum ratings for a
standard based on thermal rating. The maximum output current may be further limited due to thermal considerations,
depending on ambient temperature and board conditions.
Note 2: VCC is an internal voltage regulator and regulates 4.75V≤VCC≤5.25V in a normal condition. The above rating
shows the pin tolerance.
Note 3: Device alone. (Ta =25°C)
If the ambient temperature is above 25°C, the power dissipation must be de-rated by 10.4mW/°C.
Ta: Ambient temperature
Topr: Ambient temperature while the device is active
Tj: Junction temperature while the device is active. The maximum junction temperature is limited by the thermal
shutdown(TSD) circuitry. It is advisable to keep the maximum current below a certain level so that the maximum
junction temperature, Tj(max), will not exceed 120°C.
Caution) Absolute maximum ratings
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a
moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause device breakdown, damage or
deterioration, and may result in injury by explosion or combustion. The value of even one parameter of the absolute
maximum ratings should not be exceeded under any circumstances. The device does not have overvoltage detection
circuit. Therefore, the device is damaged if a voltage exceeding its rated maximum is applied. All voltage ratings, including
supply voltages, must always be followed. The other notes and considerations described later should also be referred to.
Operating Range (Ta=0 to 85°C)
Characteristics
Motor power supply
Motor output current
Logic input voltage
Chopping frequency set range
VREF input voltage
Symbol
VM
IOUT
VIN(H)
VIN(L)
fchop(range)
VREF
Min
10
3.0
0
40
GND
Typ.
24
1.0
100
3.0
Max
40
2.4
5.5
2.0
150
3.6
Unit
V
A
V
V
kHz
V
Note
Note
Logic H level
Logic L level
-
Note: Maximum current for actual usage may be limited by the operating circumstances such as operating conditions
(exciting mode, operating time, etc), ambient temperature, and heat conditions (board condition and so on).
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TB67S105FTG
Electrical Specifications (Ta = 25°C, VM = 24 V, unless otherwise specified)
Characteristics
Logic input voltage
Symbol
HIGH
LOW
Logic input hysteresis
Logic input current
HIGH
LOW
Logic output pin
HIGH
voltage
LOW
Power consumption
VIN(H)
VIN(L)
VIN(HYS)
IIN(H)
IIN(L)
VOH(LO)
Test conditions
Logic input pin (Note1)
Min
Typ.
Max
Unit
3.0
0
0.3
-0.41
33
-0.34
5.5
2.0
0.5
50
1
-0.27
V
V
V
μA
μA
V
0.20
-
0.25
2
0.30
3.5
V
mA
-
3.5
5.5
mA
-
5.5
7
mA
IOH
Logic input voltage:3.3V
Logic input voltage:0V
IOH(LO)=-3mA, VCC
based
IOL(LO)=3mA, GND based
Output pins=open,
STANDBY=L
Output pins=open,
STANDBY=H, ENABLE=L
Output pins=open,
(Full step)
VM=RS=50V, VOUT=0V
-
-
1
μA
IOL
VM=RS=VOUT=50V
1
-
-
μA
ΔIOUT1
Current differential between
Ach and Bch
-5
0
5
%
Motor current setting accuracy
ΔIOUT2
IOUT=1A (Note2)
-5
0
5
%
RS pin current
IRS
VM=RS=24V
0
-
10
μA
Output MOSFET
On resistance
(High+Low side)
Rds(on)
IOUT=2.4A, Tj=25°C,
Forward direction,
(High side + Low side)
-
0.6
0.8
Ω
VOL(LO)
IM1
IM2
IM3
Output leakage
current
High
side
Low
side
Motor current channel
differential
Note1: VIN (H) is defined as the VIN voltage that causes the outputs (OUT_A, OUT_B) to change when a pin under test is
gradually raised from 0 V. VIN (L) is defined as the VIN voltage that causes the outputs (OUT_A, OUT_B) to change when
the pin is then gradually lowered. The difference between VIN (H) and VIN (L) is defined as the VIN (HYS).
Note2: When using the internal VCC regulator and for VREF input voltage with a resistance divider; taking VCC accuracy
and VREF ratio into consideration, the motor current setting accuracy specification will be ±8%.
Note: When the logic signal is applied to the device whilst the VM power supply is not asserted; the device is designed not
to function, but for safe usage, please apply the logic signal after the VM power supply is asserted and the VM voltage
reaches the proper operating range.
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TB67S105FTG
Electrical Specifications (Ta=25°C, VM=24 V, unless otherwise specified)
Characteristics
VREF input voltage
VREF input current
VCC pin voltage
VCC pin current
VREF ratio
Thermal shutdown threshold
VM POR threshold
Over-current
detection
threshold
Symbol
VREF
IREF
VCC
ICC
VREF(gain)
TSD
VMR
ISD
Test conditions
VM=24V, VCC=5V
VREF=3V
ICC=5mA
VCC=5V
VREF=2V
Note 1
Note 2
Min
GND
4.75
1/5.2
140
7
3.6
Typ.
3.0
0
5
2.5
1/5
150
8
4.6
Max
3.6
1
5.25
5
1/4.8
170
9
5.6
Unit
V
μA
V
mA
°C
V
A
(Note 1) About Thermal shutdown (TSD)
When the junction temperature of the device reaches the TSD threshold, the TSD circuit is triggered; the internal
reset circuit then turns off the output transistors. Noise rejection blanking time is built-in to avoid misdetection.
Once the TSD circuit is triggered; the detect latch signal can be cleared by reasserting the VM power source, or
setting the device to standby mode. The TSD circuit is a backup function to detect a thermal error, therefore
is not recommended to be used aggressively.
(Note 2) About Over-current detection (ISD)
When the output current reaches the threshold, the ISD circuit is triggered; the internal reset circuit then turns
off the output transistors. Once the ISD circuit is triggered, the detect latch signal can be cleared by reasserting
the VM power source, or setting the device to standby mode. For fail-safe, please insert a fuse to avoid secondary
trouble.
Back-EMF
While the motor is rotating, there is a timing at which power is fed back to the power supply. At that timing, the
motor current recirculates back to the power supply due to the effect of the motor back-EMF.
If the power supply does not have enough sink capability, the power supply and output pins of the device might
rise above the rated voltages. The magnitude of the motor back-EMF varies with usage conditions and motor
characteristics. It must be fully verified that there is no risk that the device or other components will
be damaged or fail due to the motor back-EMF.
Cautions on Overcurrent Shutdown (ISD) and Thermal Shutdown (TSD)
The ISD and TSD circuits are only intended to provide temporary protection against irregular conditions such as an
output short-circuit; they do not necessarily guarantee the complete IC safety.
If the device is used beyond the specified operating ranges, these circuits may not operate properly: then the device
may be damaged due to an output short-circuit.
The ISD circuit is only intended to provide a temporary protection against an output short-circuit. If such condition
persists for a long time, the device may be damaged due to overstress. Overcurrent conditions must be removed
immediately by external hardware.
IC Mounting
Do not insert devices incorrectly or in the wrong orientation. Otherwise, it may cause breakdown, damage and/or
deterioration of the device.
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TB67S105FTG
Electrical Specification(Ta=25°C, VM=24V, 6.8mH/5.7Ωunless otherwise specified)
Characteristics
Minimum pulse width
(SCK,RCK,SI)
Minimum setup time
Minimum clock signal
cycle(SCK,RCK)
Minimum hold time
Test conditions
Min
Typ.
Max
Unit
fOSCM=1600kHz
100
-
-
ns
tw(L)
fOSCM=1600kHz
100
-
-
ns
tset1
SCLR-→SCK
50
-
-
ns
tset2
SI→SCK
50
-
-
ns
tset3
SCK→RCK
50
-
-
ns
fOSCM=1600kHz
200
-
-
ns
thold1
SCK→SI
50
-
-
ns
thold2
SCLR-→Data
50
-
-
ns
tr
Motor output
70
120
170
ns
tf
Motor output
100
150
200
ns
AtBLK
VM=24V, IOUT=1A
Analog tBLK
250
400
550
ns
COSC=270pF,
ROSC=3.6kΩ
1360
1600
1840
kHz
Output:Active(IOUT=1 A),
fOSCM= 1600 kHz
-
100
-
kHz
tcyc
Output transistor
switching time
Analog noise blanking time
OSCM frequency
fOSCM
Chopping frequency
SCLR－
Symbol
tw(H)
fchop
tset1
tw(H)
SCK
thold2
thold1
SI
tw(L)
tset2
(DATA)
RCK
tset3
Timing charts may be simplified for explanatory purpose.
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TB67S105FTG
・Application Notes
Mixed Decay Mode waveform and settings
During constant current control, the rate of the Mixed decay mode which determines the current ripple is fixed to 37.5%.
fchop
Internal
OSC
Current
threshold
NF
MDT
IOUT
Charge Mode →NF detect →Slow Mode →
Mixed Decay Timing → Fast Mode →Charge
Mode
Mixed Decay Mode waveform (Current waveform)
fchop
fchop
Internal
OSC
Current
threshold
NF
NF
IOUT
MDT (Mixed Decay Timing) : 37.5% (fixed)
Timing charts may be simplified for explanatory purpose.
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Mixed (Slow + Fast) Decay Mode current waveform
○ When the current value increases (Mixed Decay Mode is fixed to 37.5%)
fchop
fchop
fchop
fchop
Internal
OSC
NF
NF
Current
Threshold
Slow
Slow
Fast
Current
Threshold
NF
NF
Slow
Charge
Fast
Charge
Fast
Charge
Slow
Charge
Fast
○ When the current value decreases (Mixed Decay Mode is fixed to 37.5%)
fchop
fchop
fchop
fchop
Internal
OSC
Current
Threshold
NF
The IC enters Charge mode for a
moment at which the internal RS
comparator compares the values.
The IC immediately enters SlowDecay mode because of the current
value exceeding the predefined
current level.
NF
Slow
Charge
Slow
Charge
NF
Fast
Fast
Charge
Current
Threshold
Slow
NF
Fast
NF
Slow
Charge
Fast
Charge
Note: Timing charts may be simplified for explanatory purpose.
Note: These figures are intended for illustrative purposes only. If designed more realistically, they would show transient
response curves.
The Charge period starts as the internal oscillator clock starts counting. When the output current reaches the predefined
current level, the internal RS comparator detects the predefined current level (NF); as a result, the IC enters Slow-Decay
mode.
The device transits from Slow-Decay mode to Fast-Decay mode at the point 37.5% of a PWM frequency (one chopping
frequency) remains in a whole PWM frequency period (on the rising edge of the 11th clock of the OSCM clock).
When the OSCM pin clock counter clocks 16 times, the Fast-Decay mode ends; and at the same time, the counter is reset,
which brings the device into Charge mode again.
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PHASE signal and internal OSC - output current waveform (Full step mode)
Note: Timing charts may be simplified for explanatory purpose.
37.5％ MIXED DECAY MODE
fchop
fchop
fchop
Current
Threshold
IOUT
0
MDT
Current
Threshold
NF
PHASE signal
NF
The internal OSC counter is reset.
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Motor output function
VM
VM
RS
VM
RS
U1
RS
U2
U1
U2
U1
U2
OFF
OFF
OFF
OFF
ON
L1
L2
L1
OFF
ON
ON
ON
Load
Load
Load
L2
ON
PGND
L1
L2
ON
OFF
PGND
PGND
Fast mode
Recirculates the energy back
to the power supply.
Slow mode
Circulates the current
within the device and load.
Charge mode
Flows the current
into the load.
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Motor output function
Mode
U1
U2
L1
L2
CHARGE
ON
OFF
OFF
ON
SLOW
OFF
OFF
ON
ON
FAST
OFF
ON
ON
OFF
Note: The table above is an example when the current flow in the direction shown in the figure above. The table below
shows when it is in reverse.
Mode
U1
U2
L1
L2
CHARGE
OFF
ON
ON
OFF
SLOW
OFF
OFF
ON
ON
FAST
ON
OFF
OFF
ON
This device controls each mode automatically to achieve the constant current drive.
Note: The device has a dead time to avoid shoot-through current during the mode changes.
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Current threshold calculation
The peak current (current threshold) is set by current sense resistor (RS) and reference voltage (VREF).
VREF(V)
IOUT(max) = VREF(gain)
x
RS(Ω)
VREF(gain) : VREFgain is rated at 1 / 5.0 (typ.).
Example) When current ratio is 100%,
When VREF = 3.0 V, Torque = 100%, RS = 0.51Ω is applied
the current threshold (peak current) is calcculated as below;
IOUT = 3.0V / 5.0 / 0.51Ω= 1.18 A
OSCM frequency calculation
The approximation of the OSCM frequency (fOSCM) and chopping frequency (fchop) can be calculated by below.
fOSCM=1/[0.60x{Cx(R1+500)}]
R1=3.6kΩ)
………C,R1 : OSCM resistor and capacitor value (e.q. C=270pF ,
fchop = fOSCM / 16
Increasing the chopping frequency will decrease the current ripple, which will lead to a better waveform quality. But it will
also increase the gate loss, leading to an increase in heat generation.
Decreasing the chopping frequency will most likely lower the heat generation, but will also lead to an increase in the
current ripple.
Therefore, as a reference the chopping frequency should be set to 70kHz first, then be adjusted between the range of
50kHz to 100kHz, depending on each customer’s usage conditions.
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Power consumption
The power consumed within the device is mainly separated into two groups; the output power stage and the internal logic.
1. Motor output power consumption (Rds(on)= 0.6 Ω)
The power consumption of the output stage is mainly due to the H-Bridges.
The power consumption within the two H-Bridges can be calculated as below.
P (out) = 2 (H-Bridge) × IOUT (A) × VDS (V) = 2 (H-Bridge) × IOUT (A)2 × Rds(on) (Ω)....................... (1)
Controlling the motor in full step mode ideally will make the motor current to a trapezoidal waveform. In this case, the
average power consumption can be calculated as shown below.
Example:
Rds(on) = 0.6Ω, IOUT (peak: Max) = 1.0 A, VM = 24 V
P (out) = 2 (H-Bridge) × 1.0 (A)2 × 0.6(Ω)
….(2)
= 1.2 (W)
2. Internal logic power consumption
There are two states in which the internal logic power consumption can be considered.
I (IM3) = 5.5mA (typ.)
I (IM2) = 3.5mA (typ.)
: When motor is in operation.
: When motor is stopped.
The output is connected to the VM(24V); therefore, the power consumed should be multiplied by the VM and IM.
The power consumption in this case can be calculated as below.
P (IM3) = 24 (V) × 0.0055 (A) ................................................................................................................ (3)
= 0.132 (W)
The power consumption can also be calculated when the motor is not in operation.
P (IM2) = 24 (V) × 0.0035 (A) = 0.084 (W)
3. Total power consumption
As a result from (2) and (3) above, the total power consumption can be calculated as shown below.
P = P (out) + P (IM) = 1.332 (W)
Note that the calculation is just a reference and the margin for PCB design should be considered based on evaluation
and consideration under the actual usage conditions.
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OSCM-Charge DELAY:
OSCM-Fast Delay
OSCM-Charge Delay
H
OSCM
L
tchop
H
OUTPUT
Voltage B
50%
L
H
OUTPUT
Voltage A
50%
50%
L
Current
threshold
OUTPUT
Current A
L
Charge
Slow
Fast
Note: Timing charts may be simplified for explanatory purpose.
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OSCM-Charge DELAY:
When transferring the OSCM waveform into the internal OSC, there will be some delay due to the level determination of
the OSCM waveform. The maximum delay between the OSCM and the internal OSC is nearly 1µs (fOSCM = 1600 kHz).
OSCM-CR CLK DELAY
OSCM
waveform
Internal
OSC
Figure: Timing charts of the OSCM and the internal OSC waveform
Note: Timing charts may be simplified for explanatory purpose.
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Step resolution sequence
Full step resolution sequence
100%
Bch current [%]
B
A
-100%
100%
0%
C
D
-100%
Ach current [%]
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
100%
0%
IOUTA
-100%
100%
IOUTB
0%
-100%
PHASE_A
ENABLE_A
PHASE_B
H
L
H
L
H
L
ENABLE_B
H
L
Note: Timing charts may be simplified for explanatory purpose.
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Half step resolution sequence
100%
C
A
Bch current [%]
B
0%
D
-100%
E
H
100%
F
-100%
G
Ach current [%]
C D A B C D E F GH A B C D E F GHA B CD E F GH A B C DE F G
100%
IOUTA
0%
-100%
100%
IOUTB
0%
-100%
H
PHASE_A
L
H
ENABLE_A
L
H
PHASE_B
ENABLE_B
L
H
L
Note: Timing charts may be simplified for explanatory purpose.
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Step resolution sequence
Full step sequence(TRQ1/TRQ2,TRQ3,TRQ4 settings)
+100%
-100%
Bch current [%]
+100%
-100%
Ach current [%]
(Example) （TRQ1,TRQ2,TRQ3,TRQ4=H,H,H,H=100%）
Ach
Input
PHASE_A
H
L
L
H
ENABLE_A
H
H
H
H
Bch
Output
IOUT(A)
+100%
-100%
-100%
+100%
Input
PHASE_B
H
H
L
L
ENABLE_B
H
H
H
H
Output
IOUT (B)
+100%
+100%
-100%
-100%
(Example) （TRQ1,TRQ2,TRQ3,TRQ4=H,L,L,H=60%）
Ach
Input
PHASE_A
H
L
L
H
ENABLE_A
H
H
H
H
Bch
Output
IOUT(A)
+60%
-60%
-60%
+60%
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Input
PHASE_B
H
H
L
L
ENABLE_B
H
H
H
H
Output
IOUT(B)
+60%
+60%
-60%
-60%
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Step resolution sequence
Half step sequence(TRQ1/TRQ2,TRQ3,TRQ4 settings)
+100%
-100%
Bch current [%]
+100%
-100%
Ach current [%]
(Example) （TRQ1,TRQ2,TRQ3,TRQ4=H,H,H,H=100%）
Ach
Input
PHASE_A
H
X
L
L
L
X
H
H
ENABLE_A
H
L
H
H
H
L
H
H
Bch
Output
IOUT (A)
+100%
0
-100%
-100%
-100%
0
+100%
+100%
Input
PHASE_B
H
H
H
X
L
L
L
X
ENABLE_B
H
H
H
L
H
H
H
L
Output
IOUT (B)
+100%
+100%
+100%
0
-100%
-100%
-100%
0
X: Don’t care
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(Example) （TRQ1,TRQ2,TRQ3,TRQ4=L,H,L,L=25%）
Ach
Input
PHASE_A
H
X
L
L
L
X
H
H
ENABLE_A
H
L
H
H
H
L
H
H
Bch
Output
IOUT (A)
+25%
0
-25%
-25%
-25%
0
+25%
+25%
Input
PHASE_B
H
H
H
X
L
L
L
X
ENABLE_B
H
H
H
L
H
H
H
L
Output
IOUT (B)
+25%
+25%
+25%
0
-25%
-25%
-25%
0
x: Don’t care
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Blanking time for over current detection
About ISD blanking time
ISD detection flag
ISD detection signal (synced)
Internal clock (foscs)
=6.4MHz (typ.)
0
1
2
3
4
5
6
7
Note: Timing charts may be simplified for explanatory purpose.
To avoid misdetecting the ISD which may be caused by external noise or switching spikes, the ISD circuit has a blanking
time. This blanking time is counted up by the internal system clock(6.4MHz (typ.)).
※foscs=6.4MHz(typ.) internal clock
1/foscs×7 to 8clk (1.09μs to 1.25μs)
Note that this blanking time is just a designed value and only for reference. It does not guarantee that the ISD will be
detected in the ideal way when used in the actual conditions. Therefore, for safety measures, please insert a protective
fuse in the VM power line. The optimum value of the fuse will change in each customer’s usage conditions, so please
select a fuse with enough margin to operate correctly and safely.
Blanking time for over thermal detection
About TSD blanking time
TSD detection flag
TSD detection signal (synced)
Internal clock (foscs)
=6.4MHz (typ.)
1/2 foscs
0
1
2
3
4
・・・
Note: Timing charts may be simplified for explanatory purpose.
To avoid misdetecting the TSD, the TSD circuit has a blanking time. This blanking time is counted up by the internal system
clock(6.4MHz (typ.)).
※foscs=6.4MHz(typ.) internal clock
1/(foscs/2)×7 to 8clk=1/foscs×14 to 16clk (2.18μs to 2.5μs)
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(For reference) PD-Ta graph
PD-Ta
PD-Ta Graph
of graph
TB62216FTG
（１） …ＩＣ単体
Device alone
（２） …専用実装基板（Ｆｒ－４）への実装時
When mounted on a specially designed FR-4
（基板レイアウト／実装状態に依存）
(Board layout and solder condition dependant)
4.5
4.0
Power dissipation [W]
3.5
(2)
3.0
2.5
2.0
1.5
(1)
1.0
0.5
0.0
0
25
50
75
100
Ambient temperature [℃]
125
150
Operating temperature TOPR
0 to 85°C
(1)
Rth(j-a) Device alone (96°C /W)
(2)
When mounted on a specially designed FR-4 PCB (100 mm × 200 mm × 1.6 mm: 30°C /W : reference value)
Device alone(Ta = 25°C)
If the Ta exceeds above 25°C, de-rate by 10.4mW/°C
When mounted on a specially designed FR4(Ta = 25°C)
If the Ta exceeds above 25°C, de-rate by 33.3mW/°C
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TB67S105FTG application circuit
1.0Ω
100μF
[36]
[25]
[24]
[37]
0.1μF
10kΩ
270pF 3.6kΩ
10kΩ
0.1μF
0.1μF
(Values of the components are for reference.)
M
[48]
[13]
[12]
1.0Ω
[1]
Note that the shaded area shown above is either the GND pins or GND area, and shown in gray is the NC pins.
Note: Please consider adding capacitors if needed. Also make sure that the GND pattern is connected to each other.
For RS_A, RS_B, OUT_A+, OUT_A-, OUT_B-, and OUT_B+; there are two pins so please tie the same pins together when
using the device.
Note: Solder/mount the four corner pads and the exposed pad to the GND area of the board.
The application circuit above is an example; therefore, mass-production design is not guaranteed.
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Package dimensions
P-WQFN48-0707-0.50-003
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Unit: mm
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory
purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is
required, especially at the mass production design stage.
Providing these application circuit examples does not grant a license for industrial property rights.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These components and
circuits are not guaranteed to prevent malfunction of failure from occurring in the application equipment.
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IC Usage Considerations
Notes on handling of ICs
(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even
for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by
explosion or combustion.
(2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over
current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute
maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring
or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize
the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing
time and insertion circuit location, are required.
(3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to
prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or
the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury,
smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is
unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury,
smoke or ignition.
(4) Do not insert devices in the wrong orientation or incorrectly.
Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the
current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause
the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do
not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one
time.
(5) Carefully select external components (such as inputs and negative feedback capacitors) and load components
(such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as
from input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is
connected to a speaker with low input withstand voltage, overcurrent or IC failure may cause smoke or ignition.
(The overcurrent may cause smoke or ignition from the IC itself.) In particular, please pay attention when using a
Bridge Tied Load (BTL) connection-type IC that inputs output DC voltage to a speaker directly.
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Points to remember on handling of ICs
(1) Over current Protection Circuit
Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs under all
circumstances. If the Over current protection circuits operate against the over current, clear the over current
status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause
the over current protection circuit to not operate properly or IC breakdown before operation. In addition,
depending on the method of use and usage conditions, if over current continues to flow for a long time after
operation, the IC may generate heat resulting in breakdown.
(2) Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown
circuits operate against the over temperature, clear the heat generation status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause
the thermal shutdown circuit to not operate properly or IC breakdown before operation.
(3) Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the device so that
heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at any time and condition.
These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease
in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into
considerate the effect of IC heat radiation with peripheral components.
(4) Back-EMF
When a motor reverses the rotation direction, stops or slows down abruptly, a current flow back to the motor’s
power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the
device’s motor power supply and output pins might be exposed to conditions beyond absolute maximum ratings.
To avoid this problem, take the effect of back-EMF into consideration in system design.
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