TB67S128FTG
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TB67S128FTG
CLOCK-in and Serial controlled Bipolar Stepping Motor Driver
1. Outline
The TB67S128FTG is a two-phase bipolar stepping motor driver using a
PWM chopper. The clock in decoder is built in.
Fabricated with the BiCD process, output rating is 50 V/5.0 A (Motor
supply voltage = 44 V).
2. Features
P-VQFN64-0909-0.50-006
BiCD process integrated monolithic IC.
Capable of controlling 1 bipolar stepping motor.
Weight: 0.229 g (typ.)
PWM controlled constant-current drive
Low on-resistance (High + Low side = 0.25 Ω (typ.))
MOSFET output stage.
Allows full, half, quarter, 1/8, 1/16, 1/32, 1/64, 1/128 step operation.
High efficiency motor current control mechanism (ADMD: Advanced Dynamic Mixed Decay)
Built-in Anti-stall architecture (AGC: Active Gain Control)
Built-in Sense resistor less current control architecture (ACDS: Advanced Current Detection System)
High voltage and current (For specification, please refer to absolute maximum ratings and operation ranges)
Multi error detect functions (Thermal shutdown (TSD), Over current (ISD), Power-on-reset (POR), motor load open
(OPD)).
Error detection (TSD/ISD/OPD) flag output function
Built-in VCC regulator for internal circuit
Chopping frequency of a motor can be adjusted by external resistance and capacitor.
Small package with thermal pad
TB67S128FTG: P-VQFN64-0909-0.50-006
Note: Please be careful about thermal conditions during using.
© 2018
Toshiba Electronic Devices & Storage Corporation
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TB67S128FTG
3. Pin Assignment
Pin assignment in CLK mode (IF_SEL pin = L) is shown in below figure.
NC
AGC
TORQE2
TORQE1
TORQE0
MDT1
MDT0
GND
GND
GND
CP-
CP+
CPOUT
NC
VM
VM
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CW/CCW
53
28
OUT_B+
STANDBY
54
27
OUT_B+
ENABLE
55
26
OUT_B-
RESET
56
25
OUT_B-
GAIN_SEL
57
24
OUT_A-
EDG_SEL
58
23
OUT_A-
TESTI_1
59
22
OUT_A+
TESTI_2
60
21
OUT_A+
TESTI_3
61
20
NC
LO0
62
19
RS_A
LO1
63
18
RS_A
MO
64
17
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TEST_VF
NC
LTH
29
VCC
52
NC
CLK
RS_SEL
RS_B
IF_SEL
30
VREF
51
BST
MODE2
FLIM
RS_B
CLIM1
31
CLIM0
50
OSCM
MODE1
SGND
NC
TESTO_3
32
TESTO_2
49
TESTO_1
MODE0
Note: Please solder the corner pad and the rear thermal pad of the QFN package, to the GND pattern of the PCB.
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TB67S128FTG
4. Pin Description
Pin No.
Symbol
Description
CLK mode
Serial mode
1
TESTO_1 (Note1)
TESTO_1 (Note1)
TEST OUT pin No.1
2
TESTO_2 (Note1)
TESTO_2 (Note1)
TEST OUT pin No.2
3
TESTO_3 (Note1)
TESTO_3 (Note1)
TEST OUT pin No.3
4
SGND
SGND
5
OSCM
OSCM
6
CLIM0 (Note1)
NC
AGC current limiter setup pin No.0
7
CLIM1 (Note1)
NC
AGC current limiter setup pin No.1
8
FLIM (Note1)
NC
AGC frequency limiter setup pin
AGC current boost setup pin
Logic ground pin
Internal oscillator frequency monitor and setting pin
9
BST (Note1)
NC
10
VREF
VREF
11
IF_SEL
IF_SEL
Interface select pin
12
RS_SEL
NC
RS mode select pin
13
NC
NC
NC pin
Current threshold reference pin
14
VCC
VCC
15
LTH (Note1)
LTH (Note1)
Internal regulator voltage monitor pin
16
TEST_VF (Note1)
TEST_VF (Note1)
17
NC
NC
18
RS_A (Note2)
RS_A (Note2)
Ach current sense resistor connected pin /
Ach motor power ground pin
19
RS_A (Note2)
RS_A (Note2)
Ach current sense resistor connected pin /
Ach motor power ground pin
20
NC
NC
AGC threshold setup pin
TEST monitor (3VF)
NC Pin
NC pin
21
OUT_A+ (Note2)
OUT_A+ (Note2)
Ach motor output(+) pin
22
OUT_A+ (Note2)
OUT_A+ (Note2)
Ach motor output(+) pin
23
OUT_A- (Note2)
OUT_A- (Note2)
Ach motor output(-) pin
24
OUT_A- (Note2)
OUT_A- (Note2)
Ach motor output(-) pin
25
OUT_B- (Note2)
OUT_B- (Note2)
Bch motor output(-) pin
26
OUT_B- (Note2)
OUT_B- (Note2)
Bch motor output(-) pin
27
OUT_B+ (Note2)
OUT_B+ (Note2)
Bch motor output(+) pin
28
OUT_B+ (Note2)
OUT_B+ (Note2)
Bch motor output(+) pin
29
NC
NC
30
RS_B (Note2)
RS_B (Note2)
Bch current sense resistor connected pin /
Bch motor power ground pin
31
RS_B (Note2)
RS_B (Note2)
Bch current sense resistor connected pin /
Bch motor power ground pin
32
NC
NC
33
VM (Note2)
VM (Note2)
Motor power supply input pin
34
VM (Note2)
VM (Note2)
Motor power supply input pin
35
NC
NC
36
CPOUT
CPOUT
Pin for Charge pump
37
CP+
CP+
Pin for Charge pump
NC pin
NC pin
NC pin
38
CP-
CP-
Pin for Charge pump
39
GND
GND
GND
40
GND
GND
GND
41
GND
GND
GND
42
MDT0
NC
Mixed Decay/ADMD setting pin
43
MDT1
NC
Mixed Decay/ADMD setting pin
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TB67S128FTG
Pin No.
Symbol
Description
CLK mode
Serial mode
44
TORQE0
NC
Torque setting pin No.0
45
TORQE1
NC
Torque setting pin No.1
46
TORQE2
NC
Torque setting pin No.2
47
AGC
NC
Active Gain Control setup pin
48
NC
NC
NC pin
49
MODE0
NC
Excitation setting pin No.0
50
MODE1
NC
Excitation setting pin No.1
51
MODE2
NC
Excitation setting pin No.2
52
CLK
CLK
Step clock input pin / Serial clock input pin
53
CW/CCW
DATA
Current direction setup pin / Data input pin in serial interface
54
STANDBY
STANDBY
55
ENABLE
LATCH
56
RESET
BANK_EN
57
GAIN_SEL
NC
Vref Gain setting pin
58
EDG_SEL
NC
CLK edge setting pin
59
TESTI_1 (Note1)
TESTI_1 (Note1)
TEST input pin No.1
60
TESTI_2 (Note1)
TESTI_2 (Note1)
TEST input pin No.2
61
TESTI_3 (Note1)
TESTI_3 (Note1)
TEST input pin No.3
62
LO0
LO0
Error detection flag output pin No.0
63
LO1
LO1
Error detection flag output pin No.1
64
MO
NC
Electrical angle monitor pin
Standby pin
Motor output ON/OFF pin / Latch Enable input pin
Electrical angle initialize pin / BANK select pin
Note1: This pin should be opened or connected to Ground.
Note2: The same name pins should be connected with PCB pattern each other.
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5. Block Diagram
MODE0
MODE1
MODE2
CLK
ENABLE
RESET
STANDBY
CW/CCW
TORQUE0
TORQUE1
TORQUE2
EDG_SEL
MDT0
MDT1
RS_SEL
GAIN_SEL
IF_SEL
AGC
CLIM0
CLIM1
FLIM
BST
LO0
LO1
MO
CP+
CPOUT
OSCM
CP－
VM
Charge Pump
BUF_MULTI
OUT_NOD
BIAS
VREG_5
OSC_CR
BUF_HYS
BGR
OSC_6.4M
IN_FIL
TSD
To analog
VCC
To logic
IREFMR_
5U
IREF
Logic
CLOCK IN Contrpl
SIRIAL IN Control
BGR
LTH
LTH_VI
SGND
VREF
DET_COMP
GAIN_AMP
U_STEP_DAC
IOUT_VI
PREDRV
SENS_ILEVEL
OUT_A
(HSW)
VM
OUT_A+
RS_A
H_EFF_DAC
U_STEP_DAC
ISD
ISD
SENS_ISDH
SENS_ISDL
SENS_ISDH
SENS_ISDL
(S285転用)
WAVE_COMP
GAIN_AMP
DET_COMP
GND
IOUT_VI
PREDRV
SENS_ILEVEL
OUT_B
(HSW)
WAVE_COMP
OUT_A-
LVSHIFT
_6BIT
OUT_B-
RS_B
VM
OUT_B+
Note: Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purpose.
Note: All the grounding wires of the TB67S128FTG should run on the solder mask on the PCB and be externally terminated at only one point. Also, a grounding method should be
considered for efficient heat dissipation. Careful attention should be paid to the layout of the output, VM and GND traces, to avoid short circuits across output pins or to the power
supply or ground. If such a short circuit occurs, the device may be permanently damaged. Also, the utmost care should be taken for pattern designing and implementation of the
device since it has power supply pins (VM, RS line, OUT line, and GND) through which a particularly large current may run. If these pins are wired incorrectly, an operation error
may occur or the device may be destroyed. The logic input pins must also be wired correctly. Otherwise, the device may be damaged owing to a current running through the IC
that is larger than the specified current. Careful attention should be paid to design patterns and mountings.
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TB67S128FTG
6. INPUT/OUTPUT Equivalent Circuit
LO0, LO1
MO
IN/OUT signal
Equivalent circuit
1 kΩ
Logic
input
pin
Digital Input (VIH/VIL)
VIH: 2.0 V (min) to 5.5 V (max)
VIL: 0 V (min) to 0.8 V (max)
100 kΩ
Pin name
MODE0, 1, 2
CLK
ENABLE
RESET
CW/CCW
TORQE0, 1, 2
EDG_SEL
MDT0, 1
RS_SEL
GAIN_SEL
IF_SEL
STANDBY
CLIM0
AGC
GND
Logic
Output
Pin
Digital Output (VOH/VOL)
(Pullup resistance:10 k to 100 kΩ)
GND
VCC
VREF
VCC
VCC voltage range
4.75 V (min)
5.0 V (typ.)
5.25 V (max)
1 kΩ
VREF
VREF voltage range
0 V to 3.6 V
1 kΩ
OSCM
OSCM frequency setting range
0.64 MHz (min)
1.12 MHz (typ.)
2.4 MHz (max)
500 Ω
OSCM
GND
VM
OUT_A+
OUT_AOUT_B+
OUT_BRS_A
RS_B
VM power supply voltage range
6.5 V (min) to 44 V (max)
OUT_x-
OUT_x+
OUTPUT pin voltage
11.2 V (min) to 48.7 V (max)
GND
RS_x
6
X = A or B
2018-06-11
TB67S128FTG
Pin name
IN/OUT signal
CLIM1
FLIM
BST
Multi state input pin voltage
Connect to VCC
Connect to GND
Connect to VCC with 100 kΩ pull-up resistor
Connect to GND with 100 kΩ pull-down resister
(Resistor accuracy should be within ±20 %.)
LTH
Equivalent circuit
VCC
Multi state
input pin
100 kΩ
1 kΩ
100 kΩ
500 Ω
Connect to GND with 100 kΩ pull-down resistor
(Resistance accuracy should be within ±20 %.)
LTH
500 Ω
CPOUT
CP+
CP-
CPOUT
VM power supply voltage range
6.5 V (min) to 44 V (max)
CP+
OUTPUT pin voltage
11.2 V (min) to 48.7 V (max)
VM
OUTPUT
Control
CPGND
Note: The equivalent circuit diagrams may be simplified for explanatory purposes.
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TB67S128FTG
7. IF Select Function
IF can be selected from CLK type or serial type.
IF_SEL pin input
Function
L
CLK mode
H
Serial mode
8. Functional Description 1 (for CLK mode when IF_SEL pin = L)
8.1. CLK Function
Each up-edge of the CLK signal will shift the motor’s electrical angle per step.
When EDG_SEL pin = L (Single Edge)
CLK pin input
Function
Up-edge
Shifts the electrical angle per step.
Down-edge
(State of the electrical angle does not change.)
When EDG_SEL pin = H (Double Edge)
CLK pin input
Function
Up-edge
Shifts the electrical angle per step.
Down-edge
Shifts the electrical angle per step.
8.2. ENABLE Function
The ENABLE pin controls the ON and OFF of the stepping motor outputs. Motor operation starts and stops by setting
H and L to the ENABLE pin. (When ENABLE pin is set to L (OFF), all of the MOSFETs turn off and become high
impedance (hereafter, Hi-Z).)
Setting the ENABLE pin to L, and avoiding the motor to operate during VM power-on and power-off (i.e., outside of
the operating voltage range) is recommended. Then, switch the ENABLE pin to H after the VM reaches the target
voltage and becomes stable.
ENABLE pin input
Function
L
OFF (High impedance mode, later omitted Hi-Z mode later)
H
ON (Normal operation mode)
8.3. CW/CCW Function and the Output Pin Function (Output logic at the time of a
charge start)
The CW/CCW pin controls the rotation direction of the motor. When set to H, the current of OUT_A is output first,
with a phase difference of 90°. When set to L, the current of OUT_B is output first with a phase difference of 90°.
CW/CCW pin input
OUT_x+
OUT_x-
L: Counter clockwise operation (CCW)
L
H
H: Clockwise operation (CW)
H
L
Note: x = A or B
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TB67S128FTG
8.4. Step Resolution Select Function
MODE 0, MODE1, and MODE2 pins control the step resolution. Pin levels of MODE0, MODE1, and MODE2 can be
switched during operation. The following step current depends on the electrical angle.
MODE2 pin input
MODE1 pin input
MODE0 pin input
L
L
L
Full step resolution
L
L
H
Half step resolution
L
H
L
Quarter step resolution
L
H
H
1/8 step resolution
H
L
L
1/16 step resolution
H
L
H
1/32 step resolution
H
H
L
1/64 step resolution
H
H
H
1/128 step resolution
9
Function
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TB67S128FTG
8.5. Timing Chart of Step Resolution Setting and Initial Angel
[Full step resolution]
CLK
MO
H
L
H
L
+100%
Iout (A)
0%
-100%
+100%
Iout (B)
0%
-100%
CCW
CW
[Half step resolution]
CLK
MO
H
L
H
L
+100%
+71%
Iout (A)
0%
-71%
-100%
+100%
+71%
Iout (B)
0%
-71%
-100%
CCW
CW
Note: MO signal is shown in the above timing chart when MO pin is connected with a pull-up resistor to VCC.
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
[Quarter step resolution]
CLK
MO
Iout (A)
Iout (B)
H
L
H
L
+100%
+71%
+38%
0%
-38%
-71%
-100%
+100%
+71%
+38%
0%
-38%
-71%
-100%
CCW
CW
Note: MO signal is shown in the above timing chart when MO pin is connected with a pull-up resistor to VCC.
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
[1/8 step resolution]
CLK
MO
H
L
H
L
+100%
+98%
+96%
+83%
+71%
+56%
+38%
+20%
Iout (A)
0%
-20%
-38%
-56%
-71%
-83%
-96%
-98%
-100%
+100%
+98%
+96%
+83%
+71%
+56%
+38%
+20%
Iout (B)
0%
-20%
-38%
-56%
-71%
-83%
-96%
-98%
-100%
CCW
CW
Note: MO signal is shown in the above timing chart when MO pin is connected with a pull-up resistor to VCC.
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
[1/16 step resolution]
CLK
MO
H
L
H
L
+100%
+98%
+96%
+83%
+71%
+56%
+38%
+20%
Iout (A)
0%
-20%
-38%
-56%
-71%
-83%
-96%
-98%
-100%
+100%
+98%
+96%
+83%
+71%
+56%
+38%
+20%
Iout (B)
0%
-20%
-38%
-56%
-71%
-83%
-96%
-98%
-100%
CCW
CW
Note: MO signal is shown in the above timing chart when MO pin is connected with a pull-up resistor to VCC.
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
8.6. Step Setting and Current Percentage
Current (%)
Full
Half
Quarter
1/8
1/16
1/32
1/64
1/128
100%
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
Available
99%
98%
Available
97%
96%
Available
95%
94%
Available
93%
92%
Available
91%
90%
Available
Available
89%
88%
Available
87%
86%
Available
85%
Available
84%
83%
Available
Available
Available
82%
Available
Available
Available
Available
Available
Available
81%
Available
80%
Available
79%
Available
Available
Available
Available
78%
Available
77%
Available
Available
76%
Available
Available
Available
Available
75%
Available
74%
Available
Available
73%
Available
72%
71%
Available
Available
Available
Available
Available
Available
Available
Available
Available
70%
Available
69%
Available
68%
Available
Available
67%
Available
Available
66%
Available
Available
65%
Available
64%
Available
Available
63%
Available
Available
62%
Available
Available
Available
Available
61%
Available
60%
Available
Available
59%
Available
Available
58%
Available
57%
56%
Available
Available
Available
Available
Available
Available
Available
55%
Available
Available
53%
Available
52%
Available
51%
Available
Available
Available
50%
Available
Available
49%
Available
48%
Available
Available
47%
Available
46%
Available
Available
Available
Available
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TB67S128FTG
Current (%)
Full
Half
Quarter
1/8
1/16
1/32
45%
1/64
1/128
Available
Available
44%
Available
43%
Available
Available
42%
Available
41%
Available
39%
Available
Available
38%
Available
Available
Available
Available
Available
37%
Available
Available
36%
Available
35%
Available
Available
34%
Available
Available
33%
Available
Available
31%
Available
30%
Available
Available
29%
Available
Available
Available
28%
Available
Available
27%
Available
25%
Available
24%
Available
Available
Available
23%
Available
Available
22%
Available
21%
Available
Available
20%
Available
Available
Available
Available
18%
Available
Available
17%
Available
16%
Available
Available
15%
Available
Available
13%
Available
Available
12%
Available
11%
Available
Available
10%
Available
Available
Available
9%
Available
Available
7%
Available
6%
Available
Available
5%
Available
Available
4%
Available
Available
2%
Available
1%
0%
Available
Available
Available
Available
Available
Available
15
Available
Available
Available
Available
2018-06-11
TB67S128FTG
8.7. Step Resolution and Set Current
STEP
1/128
1/64
1/32
1/16
1/8
1/4
1/2
Full
—
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
θ0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
θ1
100
1
θ2
100
2
100
2
θ3
100
4
θ4
100
5
100
5
100
5
θ5
100
6
θ6
100
7
100
7
θ7
100
9
θ8
100
10
100
10
100
10
100
10
θ9
99
11
θ10
99
12
99
12
θ11
99
13
θ12
99
15
99
15
99
15
θ13
99
16
θ14
99
17
99
17
θ15
98
18
θ16
98
20
98
20
98
20
98
20
98
20
θ17
98
21
θ18
98
22
98
22
θ19
97
23
θ20
97
24
97
24
97
24
θ21
97
25
θ22
96
27
96
27
θ23
96
28
θ24
96
29
96
29
96
29
96
29
θ25
95
30
θ26
95
31
95
31
θ27
95
33
θ28
94
34
94
34
94
34
θ29
94
35
θ30
93
36
93
36
θ31
93
37
θ32
92
38
92
38
92
38
92
38
92
38
92
38
θ33
92
39
θ34
91
41
91
41
16
Ach
(%)
Bch
(%)
2018-06-11
TB67S128FTG
STEP
1/128
—
Ach
(%)
Bch
(%)
θ35
91
42
θ36
90
43
θ37
90
44
θ38
89
45
θ39
89
46
θ40
88
47
θ41
88
48
θ42
87
49
θ43
86
50
θ44
86
51
θ45
85
52
θ46
84
53
θ47
84
55
θ48
83
56
θ49
82
57
θ50
82
58
θ51
81
59
θ52
80
60
θ53
80
61
θ54
79
62
θ55
78
62
θ56
77
63
θ57
77
64
θ58
76
65
θ59
75
66
θ60
74
67
θ61
73
68
θ62
72
69
θ63
72
70
θ64
71
71
θ65
70
72
θ66
69
72
θ67
68
73
θ68
67
74
θ69
66
75
θ70
65
76
1/64
1/32
1/16
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
90
43
90
43
89
45
88
47
88
47
87
49
86
51
86
51
84
53
83
56
83
56
82
58
80
60
80
60
79
62
77
63
77
63
76
65
74
67
74
67
72
69
71
71
71
71
69
72
67
74
67
74
65
76
1/8
Ach
(%)
Bch
(%)
88
47
83
56
77
63
71
71
17
1/4
Ach
(%)
Bch
(%)
83
56
71
71
1/2
Full
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
71
71
71
71
100
100
2018-06-11
TB67S128FTG
STEP
1/128
—
Ach
(%)
Bch
(%)
θ71
64
77
θ72
63
77
θ73
62
78
θ74
62
79
θ75
61
80
θ76
60
80
θ77
59
81
θ78
58
82
θ79
57
82
θ80
56
83
θ81
55
84
θ82
53
84
θ83
52
85
θ84
51
86
θ85
50
86
θ86
49
87
θ87
48
88
θ88
47
88
θ89
46
89
θ90
45
89
θ91
44
90
θ92
43
90
θ93
42
91
θ94
41
91
θ95
39
92
θ96
38
92
θ97
37
93
θ98
36
93
θ99
35
94
θ100
34
94
θ101
33
95
θ102
31
95
θ103
30
95
θ104
29
96
θ105
28
96
θ106
27
96
1/64
1/32
1/16
1/8
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
63
77
63
77
63
77
62
79
60
80
60
80
58
82
56
83
56
83
56
83
53
84
51
86
51
86
49
87
47
88
47
88
47
88
45
89
43
90
43
90
41
91
38
92
38
92
38
92
36
93
34
94
34
94
31
95
29
96
29
96
29
96
27
96
18
1/4
Ach
(%)
Bch
(%)
56
83
38
92
1/2
Ach
(%)
Bch
(%)
38
92
Ach
(%)
Bch
(%)
Full
Ach
(%)
Bch
(%)
2018-06-11
TB67S128FTG
STEP
1/128
—
Ach
(%)
Bch
(%)
θ107
25
97
θ108
24
97
θ109
23
97
θ110
22
98
θ111
21
98
θ112
20
98
θ113
18
98
θ114
17
99
θ115
16
99
θ116
15
99
θ117
13
99
θ118
12
99
θ119
11
99
θ120
10
100
θ121
9
100
θ122
7
100
θ123
6
100
θ124
5
100
θ125
4
100
θ126
2
100
θ127
1
100
θ128
0
100
1/64
1/32
1/16
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
24
97
24
97
22
98
20
98
20
98
17
99
15
99
15
99
12
99
10
100
10
100
7
100
5
100
5
100
2
100
0
100
0
100
1/8
1/4
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
20
98
20
98
10
100
0
100
0
100
19
1/2
Full
Ach
(%)
Bch
(%)
Ach
(%)
Bch
(%)
0
100
0
100
Ach
(%)
Bch
(%)
2018-06-11
TB67S128FTG
8.8. RESET Function
The RESET pin initializes the internal electrical angle.
RESET pin input
Function
L
Normal operation mode
H
Sets the electrical angle to the initial condition.
Note: Digital filter of 0.625 μs (±20 %) is implemented to the RESET pin.
The current for each channel (while RESET pin is applied) is shown in the table below. MO pin will show L at this
time.
Step resolution setting
Ach current setting
Bch current setting
Default electrical angle
Full step
100%
100%
45°
Half step
71%
71%
45°
Quarter step
71%
71%
45°
1/8 step
71%
71%
45°
1/16 step
71%
71%
45°
1/32 step
71%
71%
45°
1/64 step
71%
71%
45°
1/128 step
71%
71%
45°
8.9. Torque Function
By using this pin it is possible to switch the motor torque setting.
TORQE2 pin input
TORQE1 pin input
TORQE0 pin input
Function
L
L
L
Set torque: 100%
L
L
H
Set torque: 85%
L
H
L
Set torque: 70%
L
H
H
Set torque: 60%
H
L
L
Set torque: 50%
H
L
H
Set torque: 40%
H
H
L
Set torque: 25%
H
H
H
Set torque: 10%
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TB67S128FTG
8.10. CLK Edge Function
CLK edge function can be selected the CLK signal's rising edge or the CLK edge's dual (up and down).
EDG_SEL pin input
Function
L
Single edge (Only Up Edge of CLK Signal)
H
Dual edge (Up and Down edge)
8.11. RS Function
RS function can be selected either ACDS mode or external sense RS resistor mode.
RS_SEL pin input
Function
L
ACDS (RS resistor less) mode
H
External sense RS resistor mode
Note: PCB board should be designed according to RS Function.
8.12. Gain Function
Gain function can be change Vref(gain). Vref(gain) can be selected either 1/5 or 1/10.
GAIN_SEL pin input
Function
L
Set Vref(gain) to 1/5
H
Set Vref(gain) to 1/10
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TB67S128FTG
8.13. Selectable Mixed Decay Function
The Selectable Mixed Decay can adjust the current regeneration amount during the period of current regeneration
(Decay) using pins.
Though the Mixed Decay is determined by controlling 2 different types of decay (Fast Decay and Slow Decay), this
function enables the user to select the ratio of the Mixed Decay using MDT0 and MDT1 pin. (2bit, 4 function)
MDT1 pin input
MDT0 pin input
Function
L
L
Fast Decay: 37.5% (Fast Decay = OSCM × 6)
L
H
Fast Decay: 50% (Fast Decay = OSCM × 8)
H
L
Fast Decay only
H
H
ADMD
fchop
OSC internal
signal
Current
setting
NF detection
Iout
(MDT0, MDT1) = (L/L): Fast Decay 37.5%
(MDT0, MDT1) = (H/L): Fast Decay 50%
(MDT0, MDT1) = (L/H): Fast Decay only
Charge Mode → NF detect → Slow Decay → Fast Decay→1 fchop cycle → Charge mode
1 fchop cycle: OSCM × 16clock
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
8.13.1. Mixed Decay Waveform (Current Waveform)
fchop
fchop
OSC internal
signal
NF detection
Current
setting
NF detection
Iout
Charge
Slow Decay
Fast Decay
Note: Timing charts may be simplified for explanatory purpose.
8.13.2. Constant Current PWM Function and Timings
OSC
internal
signal
OSC
internal
signal
MDT setting
NF detection
NF detection
Charge
Slow Decay
Fast Decay
Charge
Slow Decay
MDT setting
Fast Decay
fchop
fchop
If the NF is detected during the early timing of the
fchop cycle, the Slow Decay will be longer.
If the NF is detected during the late timing of the
fchop cycle, the Slow Decay will be shorter
The Charge period is determined by the operating status.
Therefore the NF detect timing with in the chopping cycle will change. If NF is detected in the early period of the
fchop cycle, the Slow Decay will be longer. If NF is detected in the late period of the fchop cycle, the Slow Decay will
be shorter, as shown above.
Note: The chopping cycle is determined as: fchop - (Charge + Fast decay) = Slow Decay
(Fast Decay ratio can be changed by MDT0 pin and MDT1 pin setting.)
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
8.13.3. Constant Current PWM Function and Timing
OSC internal
signal
MDT setting
NF detection
Charge
Fast Decay
fchop
If NF is detected within the MDT0 pin and MDT1
pin setting, Decay sequence will only be Fast
Decay (Slow Decay does not appear).
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
8.13.4. Mixed Decay current waveform
When the next current step is higher:
fchop
fchop
fchop
fchop
OSC internal
Signal
Current
Setting
Current
Setting
NF
NF
Fast
Charge
Slow
Fast
NF
Slow
Fast
Charge
NF Slow
Fast
Charge
Charge
Slow
When Charge Period is More Than 1 fchop Cycle:
When the Charge period is longer than fchop cycle, the Charge period extends until the motor current reaches the
NF threshold. Once the current reaches the next current step, then the sequence goes on to decay mode.
fchop
fchop
fchop
fchop
OSC internal
Signal
NF
Current
Setting
Slow
Fast
Charge
Current
Setting
NF
NF
Charge
Slow
Fast
Charge
Slow
Fast
When the Next Current Step is Lower:
fchop
fchop
fchop
fchop
OSC internal
Signal
Current
Setting
NF
Charge
Charge Mode will appear per each fchop cycle to check
the current level using RS comparator. If the current level
is already above the current set level, the sequence will be
switched to Slow Decay in a very short period.
NF
Slow
Fast
Charge
Slow
Fast
NF
Charge
Current
Setting
Slow
Fast
NF
Charge
Slow
Fast
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
8.13.5. ADMD (Advanced Dynamic Mixed Decay) Constant Current Control
(MDT0 pin = H, MDT1 pin = H)
The TB67S128FTG supports the Advanced Dynamic Mixed Decay (ADMD) which monitors both charge and
discharge current during constant current PWM.
The basic sequence of the ADMD is as shown below.
fchop
OSC internal
signal
NF detect
Setting
current value
Detect
Advanced Dynamic Mixed
Decay threshold
ADMD
threshold
Iout
Charge Mode → NF detect → Fast Decay → ADMD threshold detect → Slow Decay →fchop 1 cycle → Charge mode
fchop 1 cycle: 16 clock
Note: Timing charts may be simplified for explanatory purpose.
8.13.5.1. Auto Decay Mode Current Waveform
fchop
fchop
OSC internal
signal
Setting
current value
NF detect
NF detect
Iout
Fast Decay
Slow Decay
ADMD threshold (Advanced Dynamic Mixed Decay threshold)
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
8.13.5.2. Auto Decay Mode Current Waveform
When the Next Current Step is Higher:
fchop
fchop
fchop
fchop
OSC internal
signal
Setting
current value
NF
NF
Fast
Charge
Setting
current value
NF
Charge
Slow
NF
Fast
Charge
Fast
Slow
Fast
Slow
Charge
Slow
When Charge Period is More Than 1 fchop Cycle:
When the Charge period is longer than fchop cycle, the Charge period will be extended until the motor current reaches
the NF threshold. Once the current reaches the next current step, then the sequence will go on to decay mode.
fchop
fchop
fchop
fchop
OSC internal
signal
Setting
current value
NF
Fast
Slow
Charge
Setting
current value
NF
Charge
NF
Fast
Fast
Charge
Slow
Slow
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
When the Next Current Step is Lower:
fchop
fchop
fchop
fchop
OSC internal
signal
Setting
current value
NF
Charge
Charge Mode will appear per each fchop cycle to
check the current level using RS comparator. If the
current level is already above the current set level, the
sequence will be switched to Fast Decay in a very
short period.
NF
Fast
Charge
Fast
NF
Slow Charge
Slow
Setting
current value
Fast
Charge
Fast
Slow
Slow
When the Fast Continues Past 1 fchop Cycle
(the motor current not reaching the ADMD threshold during 1 fchop cycle)
fchop
fchop
fchop
fchop
OSC internal
signal
Setting
current value
NF
Charge
Fast
Charge Mode will appear per each fchop cycle to
check the current level using RS comparator. If the
current level is already above the current set level, the
sequence will be switched to Fast Decay in a very
short period.
NF
Slow
Charge
Fast
If the motor current is still above the ADMD threshold
after reaching 1 fchop cycle, the output stage function
will stay Fast Decay until the current reaches the
ADMD threshold.
Setting
current value
Charge
Slow
Fast
Slow
Note: Timing charts may be simplified for explanatory purpose.
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TB67S128FTG
9. Functional Description 2 (for Serial mode when IF_SEL pin = H)
When IF_SEL pin = H, the interface is serial input. It performs setting and motor control in the following 32 bit
format.
When BANK_EN pin is L, initial setting is performed. When the BANK_EN pin is H, the motor is controlled.
For the motor control, each current value is set in the serial setting, and the output is updated to the set current
value at the timing of the LATCH signal.
BANK_EN = L: Initial setting
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
0
0
AGC
CLIM
0
CLIM
1
CLIM
2
FLIM
0
FLIM
1
BST0
BST1
0
0
RS_
SEL
GAIN
_SEL
0
0
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: The data which has a same name as a pin name in CLK mode performs as same as the pin in CLK mode.
BANK_EN = H: Motor controlling
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
0
0
TOR
QE0
TOR
QE1
TOR
QE2
0
MDT
_A0
MDT
_A1
PHA
CA0
CA1
CA2
CA3
CA4
CA5
CA6
D16
D17
D18
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
CA8
CA9
D20
MDT
_B1
D21
CA7
D19
MDT
_B0
PHB
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CB8
CB9
Note: Every issuing a command, the current setting transfers by one step.
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TB67S128FTG
9.1. Registers When BANK_EN pin = H
The registers when BANK_EN pin = H are shown below.
9.1.1. PHx (x = A and B)
The polality of the output current can be selected by PHx register for each channels.
PHx register setting
Function
L
Setting the direction of the output current to minus
H
Setting the direction of the output current to plus
9.1.2. Cx0 to Cx9 (x = A or B)
The output of each channel’s DAC for current limitation can be set by Cx0 to Cx9.
The relation between Setting DAC and the output current (Iout) are shonw below.
A)
External Sense Resistor mode
Iout (max) = Vref(gain) ×
(x = A or B)
B)
Vref (V)
Cx[9: 0]
×
× Setting torque by the torque function (%)
RS (Ω)
1023
RS Resistor Less Mode (ACDS)
Vref(gain) =
1
Vref(gain) =
1
5
(typ. ) (when GAIN_SEL pin = L)
Iout (max) = 1.56 × Vref (V) ×
Cx[9:0]
× Setting torque by the torque function (%)
Iout (max) = 0.78 × Vref (V) ×
Cx[9:0]
× Setting torque by the torque function (%)
10
(x = A or B)
1023
(typ. ) (when GAIN_SEL pin= H)
1023
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TB67S128FTG
9.2. Serial setting example when driving a motor
Serial setting example for motor operation is shown below.
1.
2.
3.
Set the BANK_EN pin L. Initial setting for AGC, etc. is performed under this condition.
Then, set the BANK_EN pin H and configure the motor control to turn on the output transistors.
Transmit the 1st to 4th commands repeatedly by keeping the BANK_EN pin level H. The motor operates
with full step resolution.
1st command
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
2nd command
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
3rd command
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
4th command
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
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TB67S128FTG
10. Stepping Motor Application Features
(Anti-stall, RS resistor less PWM)
10.1. Active Gain Control (Anti-stall) Function
AGC pins will set the Active Gain Control to turn on or off. When this pins are set to H, the AGC is turned on, and
when this pins are set to L, the AGC is turned off.
When the AGC is ON, the motor current is equal or more than the value by setting the VREF pin. The TB67S128FTG
reduces gradually the motor current depending on the load torque.
When the AGC is OFF, the motor current is the value by setting the VREF pin.
AGC pin input
Function
L
AGC: OFF
H
AGC: ON
Note: Please do not change the AGC pins when the TB67S128FTG is powered on.
Note: There is a built-in digital filter of 0.625 μs (±20%) for AGC pin.
10.2. CLIM (AGC Bottom Current Limit) Function
When AGC is active, the motor current is reduced according to the load torque. The CLIM0 and CLIM1 pins set the lower
threshold of the current threshold for AGC.
The CLIM0 pin is a 2 stated logic input, and the CLIM1 pin is a 4 stated logic input.
CLIM0 pin input
L
H
CLIM1 pin input
Function
VCC short
AGC bottom current limit: Iout × 60%
VCC - 100 kΩ pull-up
AGC bottom current limit: Iout × 55%
GND - 100 kΩ pull-down
AGC bottom current limit: Iout × 50%
GND short
AGC bottom current limit: Iout × 45%
VCC short
AGC bottom current limit: Iout × 80%
VCC - 100 kΩ pull-up
AGC bottom current limit: Iout × 75%
GND - 100 kΩ pull-down
AGC bottom current limit: Iout × 70%
GND short
AGC bottom current limit: Iout × 65%
Note: Pull-up and pull-down resistor tolerance should be kept within ±20 %.
Note: There is a built-in digital filter of 0.625 μs(±20%) for CLIM0 and CLIM1 pin.
10.3. BOOST (Current Boost) Function
When AGC is active, the motor current is reduced according to the load torque. In this state, the BST pin sets the current
boost level when the load torque increases. The BST pin is a 4 stated logic input pin.
BST pin input
Function
VCC short
Takes 5 steps maximum (Design value)
VCC - 100 kΩ pull-up
Takes 7 steps maximum (Design value)
GND - 100 kΩ pull-down
Takes 9 steps maximum (Design value)
GND short
Takes 11 steps maximum (Design value)
Note: Pull-up and pull-down resistor tolerance should be kept within ±20 %.
Note: There is a built-in digital filter of 0.625 μs(±20%) for BST pin.
Note: Current boost step is largest when BST pin is tied to VCC, and smallest when tied to the GND.
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TB67S128FTG
10.4. FLIM (AGC Frequency limit) function
The FLIM pin will set the frequency limit for the AGC to be active. The FLIM function is effective when the AGC is
used to avoid the motor resonance frequency during ramp up.
The FLIM pin is a 4 stated logic input.
FLIM pin input
Function
VCC short
Frequency limit: ON, AGC is invalid when fCLK is below 675 Hz
VCC - 100 kΩ pull-up
Frequency limit: ON, AGC is invalid when fCLK is below 450 Hz
GND - 100 kΩ pull-down
Frequency limit: ON, AGC is invalid when fCLK is below 225 Hz
GND short
FLIM: OFF
Note: Pull-up and pull-down resistor tolerance should be kept within ±20 %.
Note: There is a built-in digital filter of 0.625 μs(±20%) for FLIM pin.
The frequency (fCLK) shown above is for full step resolution. The frequency limit threshold will depend on the step
resolution setting.
FLIM pin input
1/1
1/2
1/4
1/8
1/16
1/32
VCC short
675 Hz
1.35 kHz
2.7 kHz
5.4 kHz
10.8 kHz
21.6 kHz
VCC - 100 kΩ pull-up
450 Hz
900 Hz
1.8 kHz
3.6 kHz
7.2 kHz
14.4 kHz
GND - 100 kΩ pull-down
225 Hz
450 Hz
900 Hz
1.8 kHz
3.6 kHz
7.2 kHz
GND short
FLIM: OFF
Note: Pull-up and pull-down resistor tolerance should be kept within ±20 %.
10.5. LTH (AGC detection threshold) function
The LTH pin sets the AGC detection threshold. Connect a 100 kΩ pull-down resistor to GND.
LTH
Function
GND - 100 kΩ pull-down
Sensitivity of the Anti-stall detection standard setting
Note: Pull-down resistor tolerance should be kept within ±20 %.
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11. Common Function (When CLK Mode and Serial Mode)
11.1. LO (Error detect flag output) Function
When an error detection function performs, the LO function outputs an error detection as a signal from LO0 and LO1
pins to the outside of TB67S128FTG.
The LO0 and LO1 pins are open-drain output pins. The LO0 and LO1 pins need to be pulled up to VCC level via 10
k to 100 kΩ resistor.
During regular operation, the level of LO0 and LO1 pins will stay Hi-Z (the internal MOSFET is OFF, the level of
these pins are VCC level).
When the thermal shutdown (TSD), Over current (ISD), or motor load open (OPD) occurs, the LO0 and/or LO1 pins
will become L (the internal MOSFET is ON).
When the error detection is released by reasserting the VM power supply or setting the device to STANDBY mode,
the LO0 and LO1 pins show “normal status”.
Leave the LO0 and LO1 pins open when not using these functions.
Inside the IC
Outside the IC
VCC
10 kΩ
Note: This figure may be simplified for explanatory purpose.
LO0 pin output
LO1 pin output
Function
Hi-Z
Hi-Z
Normal status (Normal operation)
Hi-Z
L
Detected motor load open (OPD)
L
Hi-Z
Detected over current (ISD)
L
L
Detected thermal shutdown (TSD)
11.2. STANDBY Function
It is possible to switch to Standby mode by switching this pin.
STANDBY pin input
Function
L
Standby mode
H
Normal operation
Note: In STANDBY pin = L, an internal oscillating circuit and a motor output part are stopped. At this time, the motor cannot
be driven.
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12. Output Transistor Function Mode
VM
VM
U1
VM
U2
U1
U2
U1
U2
OFF
OFF
OFF
OFF
ON
L1
L2
L1
OFF
ON
ON
ON
Load
Load
ON
L1
Load
L2
ON
RS_x pin
RS_x pin
Charge mode
A current flow into the motor coil.
L2
OFF
RS_x pin
Fast mode
The energy of the motor coil is feed
back to the power.
Slow mode
A current circulates around the
motor coil and this device.
Note: x = A or B
Note: The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Output transistor function
MODE
U1
U2
L1
L2
CHARGE
ON
OFF
OFF
ON
SLOW
OFF
OFF
ON
ON
FAST
OFF
ON
ON
OFF
Note: This table shows an example of when the current flows as indicated by the arrows in the figures shown above.
If the current flows in the opposite direction, refer to the following table.
MODE
U1
U2
L1
L2
CHARGE
OFF
ON
ON
OFF
SLOW
OFF
OFF
ON
ON
FAST
ON
OFF
OFF
ON
This IC controls the motor current to be constant by changing 3 modes listed above automatically.
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13. Calculation of the Predefined Output Current
13.1. External Sense Resistor mode
For PWM constant-current control, this IC uses a clock generated by the OSCM oscillator.
The peak output current (Setting current value) can be set via the current-sensing resistor (RS) and the reference
voltage (Vref), as follows:
Iout (max) = Vref(gain) ×
Note: When GAIN_SEL pin = L, Vref(gain) =
For example:
1
5
Vref (V)
RS (Ω)
(typ. ). And When GAIN_SEL pin = H, Vref(gain) =
When Vref = 3.0 (V), RS = 0.22 Ω, Torque = 100% and Vref(gain) =
1
5
1
10
(typ. ).
(typ. ) (When GAIN_SEL pin = L), motor
constant current (Setting current value) will be calculated by the following expressions.
Iout (max) =
1
3 (V)
×
= 2.73 A
5
0.22 (Ω)
13.2. RS Resistor Less Mode (ACDS)
The Iout (max) will be calculated by the following expressions.
When Vref(gain) =
1
5
(typ. ) (GAIN_SEL = L)
Iout (max) = 1.56 × Vref (V)
When Vref(gain) =
1
10
(typ. ) (GAIN_SEL = H)
Iout (max) = 0.78 × Vref (V)
14. Calculation of the OSCM Oscillation Frequency
(chopper reference frequency)
An approximation of the OSCM oscillation frequency (fOSCM) and chopper frequency (fchop) can be calculated by
the following expressions.
fOSCM =
1
0.56 × {COSC × (ROSC + 500)}
fchop =
fOSCM
16
Note: COSC: Capacitor connected to OSCM pin, ROSC: Resistor connected to OSCM pin
For example:
When COSC = 270 pF and ROSC = 5.1 kΩ, fOSCM frequency will be calculated by following expressions.
fOSCM =
1
≈ 1.2 (MHz)(typ. )
0.56 × {270 pF × (5.1 kΩ + 500)}
fchop =
fOSCM
1.2 (MHz)
=
≈ 75 (kHz)
16
16
If chopping frequency is raised, Rippl of current will become small and wave-like reproducibility will improve.
However, the gate loss inside IC goes up and generation of heat becomes large.
By lowering chopping frequency, reduction in generation of heat is expectable. However, Rippl of current may become
large.
It is a standard about 70 kHz. A setup in the range of 50k to 100 kHz is recommended.
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15. Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Remarks
Motor output voltage
Vout
50
V
—
Motor power supply (non active)
Motor power supply (active)
VM
50
V
STANDBY pin = L
-0.4 to 44
V
STANDBY pin = H
(Note1)
Motor output current
Iout
5.0
A
VCPP
VM ± 6 V
V
—
Charge pump voltage
VCPM
VM ± 6 V
V
—
VCPO
50
V
—
Internal Logic power supply
Logic input voltage
VCC
6.0
V
VIN(H)
6.0
When externally applied.
V
—
VIN(L)
-0.4
V
—
MO output voltage
VMO
6.0
V
—
LO0, LO1 output voltage
VLO
6.0
—
MO Inflow current
LO0, LO1 Inflow current
IMO
ILO
6.0
6.0
V
mA
mA
—
—
Power dissipation
PD
1.2
W
Operating temperature
Topr
-40 to 85
(Note2)
°C
—
Storage temperature
Tstg
-55 to 150
°C
—
Junction temperature
Tj(max)
150
—
°C
Note1: Usually, the maximum current value at the time should use 70% or less of the absolute maximum ratings for a
standard on thermal rating. The maximum output current may be further limited in view of thermal considerations,
depending on ambient temperature and board conditions.
Note2: Device alone (Ta =25°C)
When Ta exceeds 25°C, it is necessary to do the derating with 9.6 mW/°C.
Ta: Ambient temperature
Topr: Ambient temperature while the IC is active
Tj: Junction temperature while the IC is active. The maximum junction temperature is limited by the thermal
shutdown (TSD) circuitry. It is advisable to keep the maximum current below a certain level so that the maximum
junction temperature, Tj (MAX), will not exceed 120°C.
Caution) Absolute maximum ratings
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even
for a moment. Do not exceed any of these ratings.
Exceeding the rating (s) may cause device breakdown, damage or deterioration, and may result in injury by
explosion or combustion.
The value of even one parameter of the absolute maximum ratings should not be exceeded under any
circumstances. The TB67S128FTG does not have overvoltage detection circuit. Therefore, the device is damaged
if a voltage exceeding its rated maximum is applied.
All voltage ratings, including supply voltages, must always be followed. The other notes and considerations
described later should also be referred to.
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16. Operation Ranges (Ta=-40 to 85°C)
Characteristics
Motor power supply
Motor output current
Symbol
Min
Typ.
Max
Unit
VM
6.5
24
44
V
—
Iout
—
3.0
5.0
A
(Note1)
VIN(H)
2.0
—
5.5
V
VIN(L)
0
—
0.8
V
VMO
VLO
fCLK
fchop (range)
Vref
—
—
—
40
GND
3.3
3.3
—
70
2.0
5.0
5.0
200
150
3.6
V
V
kHz
kHz
V
Remarks
Logic input H
Level
Logic input L
Level
—
—
—
—
—
Logic input voltage
MO output pin voltage
LO0, LO1 output pin voltage
Clock input frequency
Chopper frequency
Vref input voltage
Note1: Maximum current for actual usage may be limited by the operating circumstances such as operating conditions
(exciting mode, operating time, and so on), ambient temperature, and heat conditions (board condition and so on).
17. Electrical Specifications 1
(Ta = 25°C, VM = 24 V, unless specified otherwise)
Characteristics
HIGH
LOW
Logic input hysteresis voltage
HIGH
Logic input current
LOW
Logic input voltage
Symbol
Test condition
Min
Typ.
Max
Unit
VIN(H)
VIN(L)
VIN(HYS)
IIN(H)
IIN(L)
Logic input (Note1)
Logic input (Note1)
Logic input (Note1)
VIN(H) = 3.3 V
VIN(L) = 0 V
2.0
0
100
—
—
—
—
—
33
—
5.5
0.8
300
—
1
V
V
mV
A
μA
MO output pin voltage
LOW
VOL(MO)
IOL = 5 mA, output = L
—
0.2
0.5
V
LO0, LO1 output pin
voltage
LOW
VOL(LO)
IOL = 5 mA, output = L
—
0.2
0.5
V
—
1.8
3.2
mA
—
5.5
8.6
mA
—
8.2
10.4
mA
Output pins = open
Standby mode
Output pins = open
ENABLE pin = L
in releasing Standby mode
Output pins = open
Full step resolution
IM1
Current consumption
IM2
IM3
High side
IOH
VM = 44 V, Vout = 0 V
—
—
1
μA
Low side
IOL
VM = Vout = 44 V
1
—
—
μA
Motor current channel differential
ΔIout1
Current differential between Ch
-5
0
5
%
Motor current setting accuracy
RS pin current
Motor output ON resistance
(High side+Low side)
ΔIout2
IRS
Iout =3.0 A
VRS = 0 V
-5
0
0
—
5
10
%
μA
Ron(H+L)
Tj = 25°C, High side+Low side
—
0.25
0.35
Ω
Output leakage current
Note: When the logic signal is applied to the device whilst the VM power supply is not asserted; the device is designed not
to function, but for safe usage, please apply the logic signal after the VM power supply is asserted and the VM
voltage reaches the proper operating range.
Note1: VIN(H) is defined as the VIN voltage that causes the outputs (OUT_A+ pin, OUT_A- pin, OUT_B+ pin, OUT_B- pin)
to change when a pin under test is gradually raised from 0 V.VIN(L) is defined as the VIN voltage that causes the
outputs (OUT_A+ pin, OUT_A- pin, OUT_B+ pin, OUT_B- pin) to change when the pin is then gradually lowered.
The difference between VIN(H) and VIN(L) is defined as the VIN(HYS).
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18. Electrical Specifications 2
(Ta =25°C, VM = 24 V, unless specified otherwise)
Characteristics
Symbol
Test condition
Min
Typ.
Max
Unit
Vref input current
VCC voltage
VCC current
Iref
VCC
ICC
—
4.75
—
0
5
2.5
1
5.25
5
μA
V
mA
Vref gain rate
Vref(gain)
Vref = 2.0 V
ICC = 5.0 mA
VCC = 5.0 V
Vref = 2.0 V
GAIN_SEL pin = L
1/5.2
1/5
1/4.8
—
Thermal shutdown (TSD)
threshold (Note1)
VM recovery voltage
Over current detection (ISD)
threshold (Note2)
TjTSD
—
145
160
175
°C
VMR
—
5.7
6
6.3
V
ISD
—
5.7
7.2
10
A
Note1: About TSD
When the junction temperature of the device reached the TSD threshold, the TSD circuit is triggered; the internal reset
circuit then turns off the output transistors. Noise rejection blanking time is built-in to avoid misdetection. Once the TSD
circuit is triggered, the device will be set to standby mode, and can be cleared by reasserting the VM power source, or
setting the MODE pins to standby mode. The TSD circuit is a backup function to detect a thermal error, therefore is not
recommended to be used aggressively.
Note2: About ISD
When the output current reaches the threshold, the ISD circuit is triggered; the internal reset circuit then turns off the output
transistors. Once the ISD circuit is triggered, the device keeps the output off until power-on reset (POR), is reasserted or
the device is set to standby mode by MODE pins. For fail-safe, please insert a fuse to avoid secondary trouble.
Back-EMF
While a motor is rotating, there is a timing at which power is fed back to the power supply. At that timing, the motor current
recirculates back to the power supply due to the effect of the motor back-EMF.
If the power supply does not have enough sink capability, the power supply and output pins of the device might rise above
the rated voltages. The magnitude of the motor back-EMF varies with usage conditions and motor characteristics. It must
be fully verified that there is no risk that the TB67S128FTG or other components will be damaged or fail due to the motor
back-EMF.
Cautions on Overcurrent Shutdown (ISD) and Thermal Shutdown (TSD)
The ISD and TSD circuits are only intended to provide temporary protection against irregular conditions such as an output
short-circuit; they do not necessarily guarantee the complete IC safety.
If the device is used beyond the specified operating ranges, these circuits may not operate properly: then the device may
be damaged due to an output short-circuit.
The ISD circuit is only intended to provide a temporary protection against an output short-circuit. If such a condition persists
for a long time, the device may be damaged due to overstress. Overcurrent conditions must be removed immediately by
external hardware.
IC Mounting
Do not insert devices incorrectly or in the wrong orientation. Otherwise, it may cause breakdown, damage and/or
deterioration of the device.
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19. AC Electrical Specification (Ta = 25°C, VM = 24 V, 6.8 mH/5.7 Ω)
Characteristics
Symbol
Test condition
Min
Typ.
Max
Unit
Inside filter of CLK input minimum
High width
tCLK(H)
The CLK(H) minimum pulse
width
300
—
—
ns
Inside filter of CLK input minimum
Low width
tCLK(L)
The CLK(L) minimum pulse
width
250
—
—
ns
tr
—
30
80
130
ns
Output transistor
tf
—
40
90
140
ns
switching specific
tpLH(CLK)
CLK output
—
1000
—
ns
tpHL(CLK)
CLK output
—
1500
—
ns
Analog noise blanking time
AtBLK
VM = 24 V, Iout = 3.0 A
Analog tblank
250
400
550
ns
Oscillator frequency accuracy
ΔfOSCM
COSC = 270 pF,
ROSC = 5.1 kΩ
-15
—
+15
%
Oscillator reference frequency
fOSCM
Chopping frequency
fchop
COSC= 270 pF,
1020
ROSC =5.1 kΩ
Output: Active (Iout = 1.5 A),
fOSC = 1200 kHz
1200 1380
—
75
—
kHz
kHz
AC Electrical Specification Timing chart
1/fCLK
tCLK(L)
50%
50%
50%
tCLK(H)
[CLK]
tpHL(CLK)
tpLH(CLK)
90%
90%
50%
50%
[OUT]
10%
tr
tf
10%
Note: Timing charts may be simplified for explanatory purpose.
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20. Other AC Electrical Specification
(Ta = 25°C, VM = 24 V, unless specified otherwise)
Symbol
Test condition
Min
Typ.
Max
Unit
No.
in Timing Chart
Serial CLK frequency
fSCLK
1.0
—
25
MHz
—
CLK Cycle
tsCKW
VIN = 3.3 V
VIH = 3.3 V, VIL = 0 V,
tr = tf = 23 ns
46
—
—
ns
—
40
20
20
40
20
20
10
10
10
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
9
10
Characteristics
tw(CLK)
twp(CLK)
twn(CLK)
tSTROBE
Minimum STROBE pulse
tSTROBE(H)
width
tSTROBE(L)
tsuSIN - CLK
Data setup time
tsuST - CLK
thSIN - CLK
Data hold time
thST - CLK
Minimum CLK pulse
width
VIN = 3.3 V
VIN = 3.3 V
VIN = 3.3 V
VIN = 3.3 V
tw (CLK)
1
50%
CLOCK
tsuST - CLK
8
STROBE
6
7
DATA
50%
L
thST - CLK
10
50%
tSTROBE(L)
tsuSIN - CLK
H
50%
3
2
twn(CLK) twp(CLK)
H
L
tSTROBE(H)
5
thSIN - CLK tSTROBE
4
9
DATA15
DATA0
50%
DATA1
H
L
Note: The CLK whose frequency is 1MHz or less may be used if the falling time and the rising time of CLK satisfy above
condition.
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21. Application Circuit Example (RS_SEL pin = H, IF_SEL pin = L)
The application circuit shown in this document is provided for reference purposes only. The data for mass production are
not guaranteed.
Constant numbers of components (for reference only)
Part’s symbol
Component
CVM1
Electrolytic capacitor
CVM2
Ceramic capacitor
CCP
Ceramic capacitor
CCPO
Ceramic capacitor
C_VCC
Ceramic capacitor
R_OSC
Resistor
C_OSC
Ceramic capacitor
R_VREF1, R_VREF2
Resistor
C_VREF
Ceramic capacitor
R_MO
Resistor
R_LO0, R_LO1
Resistor
R_LTH
Resistor
Note: Constant numbers in above table are for reference only. Some
can be adopted depending on the usage conditions.
42
Reference constant number
100 μF (CVM1 ≥ 10 μF)
(0.1 μF)
0.022 μF
0.22 μF
0.1 μF
5.1 kΩ (1.8 kΩ to 8.2 kΩ)
270 pF
Arbitrary (10 kΩ ≤ R_VREF1 + R_VREF2 ≤ 50 kΩ)
(0.1 μF)
10 kΩ (10 kΩ to 100 kΩ)
10 kΩ (10 kΩ to 100 kΩ)
100 kΩ
components outside of the recommendation range
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TB67S128FTG
22. Package Dimensions
P-VQFN64-0909-0.50-006
Unit: mm
Weight: 0.229 g (typ.)
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only.
evaluation is required, especially at the mass production design stage.
Providing these application circuit examples does not grant a license for industrial property rights.
Thorough
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
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IC Usage Considerations
Notes on handling of ICs
(1)
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
(2)
Use an appropriate power supply fuse to ensure that a large current does not continuously flow in
case of over current and/or IC failure. The IC will fully break down when used under conditions that
exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal
pulse noise occurs from the wiring or load, causing a large current to continuously flow and the
breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of
breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are
required.
(3)
If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current resulting from the inrush
current at power ON or the negative current resulting from the back electromotive force at power
OFF. IC breakdown may cause injury, smoke or ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable,
the protection function may not operate, causing IC breakdown. IC breakdown may cause injury,
smoke or ignition.
(4)
Do not insert devices in the wrong orientation or incorrectly.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and
exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
In addition, do not use any device that is applied the current with inserting in the wrong orientation
or incorrectly even just one time.
(5) Carefully select external components (such as inputs and negative feedback capacitors) and load
components (such as speakers), for example, power amp and regulator.
If there is a large amount of leakage current such as from input or negative feedback condenser, the IC
output DC voltage will increase. If this output voltage is connected to a speaker with low input
withstand voltage, overcurrent or IC failure may cause smoke or ignition. (The overcurrent may cause
smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied
Load (BTL) connection-type IC that inputs output DC voltage to a speaker directly.
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Points to remember on handling of ICs
(1)
Over current Protection Circuit
Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs
under all circumstances. If the Over current protection circuits operate against the over current, clear
the over current status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings
can cause the over current protection circuit to not operate properly or IC breakdown before operation.
In addition, depending on the method of use and usage conditions, if over current continues to flow for
a long time after operation, the IC may generate heat resulting in breakdown.
(2)
Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal
shutdown circuits operate against the over temperature, clear the heat generation status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings
can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation.
(3)
Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the device
so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at any time
and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design
can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please
design the device taking into considerate the effect of IC heat radiation with peripheral components.
(4)
Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the
motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply
is small, the device’s motor power supply and output pins might be exposed to conditions beyond
absolute maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in
system design.
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RESTRICTIONS ON PRODUCT USE
Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”.
Hardware, software and systems described in this document are collectively referred to as “Product”.
•
TOSHIBA reserves the right to make changes to the information in this document and related Product without notice.
•
This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
•
Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software
and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life,
bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including
the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest
versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and
application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook"
and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all
aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of
this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this
document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c)
validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS'
PRODUCT DESIGN OR APPLICATIONS.
•
PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH
MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without
limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related
fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details,
please contact your TOSHIBA sales representative.
•
Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
•
Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
•
The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
•
ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF
SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES
OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION
AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS
RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
•
Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and
the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited
except in compliance with all applicable export laws and regulations.
•
Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of
Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled
substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR
LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
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