TC35273

Preliminary TOSHIBA MPEG-4 Audiovisual LSI MPEG-4 Audiovisual Codec LSI TC35273 TC35273 Tentative Technical Data Sheet MPEG-4 Audiovisual LSI Features U TC35273 is an MPEG-4 audiovisual codec LSI which supports 3GPP 3G-324M video telephony system. MPEG-4 video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T H.223 are executed concurrently at around 70MHz clock rate. U Three signal processing units, an MPEG-4 video codec, a speech codec / audio decoder, and a multiplex / demultiplex unit, are integrated on a single chip. P-FBGA201-1515-0.80A5 U A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing units. The embedded DRAM helps to reduce power consumption without performance degradation. U Each signal processing unit consists of a 16-bit RISC processor and dedicated hardware accelerators so as to bring programmability, high performance and low power consumption. Firmware programs for the RISCs are downloaded into the embedded DRAM before starting operation. Various applications are performed by choosing an appropriate firmware. General host interface are adopted in order to support various host CPU. 2.5x to 6x of PLL is integrated on the chip for easy system integration. U U U • TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. • The products described in this document are subject to foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. TOSHIBA Confidential 1/23 Version 0.90 2000-4-27 Preliminary • MPEG-4 Audiovisual Codec LSI TC35273 The circuit contained herein is presented only as a guide for the applications, and it is not guaranteed. TOSHIBA Confidential 2/23 Version 0.90 2000-4-27 Preliminary 1. Functional Specifications 1.1 MPEG-4 Video Codec U MPEG-4 Audiovisual Codec LSI TC35273 ISO MPEG-4 International Standard Simple Profile @Level 1 is supported. Encoding and decoding with QCIF (176 x 144 pixel) at 15 frames per second are executed. YCbCr 4:2:2 8bit digital camera input. A CMOS camera or an NTSC decoder is connected. Temporal filter and size conversion for pre-filter function. YCbCr 4:2:2 8bit digital display output. An NTSC encoder or an LCD controller is connected. Size conversion and de-blocking filter for post-filter function. U U U U 1.1.1. Speech Codec / Audio Decoder U U U U U U AMR Speech Codec at 8kbps with CS-ACELP.* ITU-T G.729 speech codec at 8Kbps with CS-ACELP.* ITU-T G.723.1 speech codec at 5.3kbp with ACELP, or 6.3kbps with MP-MLQ.* Stereo Twin-VQ audio decoder at 96kbps with up to 44.1-kHz sampling frequency.* ISO/IEC 13818-7 AAC LC audio decoder at 144kbps with up to 48-kHz sampling frequency.* PCM stereo or monoral sound input/output. An external microphone and a speaker are connected via DAC and ADC, respectively. 1.1.2. Multiplexer/Demultiplexer U Multiplexing and demultiplexing with ITU-T H.223 and H.223 Annex A,B protocol at 32Kbps 384Kbps.* Demultiplexing with ITU-T H.222.0 / ISO/IEC13818-1 at 32Kbps 1024Kbps.* Bitstream input/output via a network serial interface. U U * In order to run this LSI as an MEPG-4 audiovisual LSI, Specified firmware programs have to be obtained in advance TOSHIBA Confidential 3/23 Version 0.90 2000-4-27 Preliminary 1.2. System configuration. and 12-Mbit DRAM are integrated in a single chip. MPEG-4 Audiovisual Codec LSI TC35273 Fig. 1 illustrates a block diagram of this LSI. Three signal processing core, peripheral interfaces, Bitstream input/output are performed via a network interface in the Mux/Demux core. A Microphone and a speaker can be connected to a PCM interface in a speech/audio core via external DAC and ADC. TOSHIBA CMOS camera is connected to a camera interface via a camera DSP “TC90A50F” or “TC90A70F”. NTSC camera is also connected via an NTSC decoder. LCD or NTSC display is connected to an LCD interface via TOSHIBA LCD controller or an NTSC encoder, respectively. Host CPU is connected via a host interfaces. It downloads firmwares into the embedded DRAM and accesses to internal registers. Bitstream In/Out D/A A /D Network Bitstream Interface MPEG-4 Video RISC HW HW Speech/Audio RISC HW HW Mux./Demux. RISC HW HW DMA Controller DMA Controller DMA Controller Arbiter + DRAM Controller 1 2Mbit Embedded DRAM LCD I/F LCDC Cam. I/F Camera DSP Prefilter Host I/F Host CPU Fig. 1 Block Diagram TOSHIBA Confidential 4/23 Version 0.90 2000-4-27 Preliminary 2. Terminals 2.1 Pin Assignment TBD MPEG-4 Audiovisual Codec LSI TC35273 2.2 Pin Allocation TBD 2.3 I/O Pins PLLFN PLL Pins PLLDIV PLLBP PLLAVD PLLAVS VGSCLK VGSADIO /HCS /HWR Host Interface /HRD HADDR HDAT /HWAIT /HACK HINT NWCLK /NWOEN Network Interface NWDO /NWIEN NWDI NWIFS NWOFS TGCLK TSMODE TDBISTEN Test Pins TDTMB TDTCLK TREOUT TEST0-3 4 5 ADIMCLK ADOMCLK ADLRCLK ADSCLK ADSDO ADSDI ADCMD Audio ADC&DAC Control Audio PCM Interface 7 16 CAMCLK CAMHREF CAMVREF CAMFSEL 8 CAMPIXEL DISPCLK DISPHSYNC DISPYSYNC DISPBLK 8 DISPPIXEL Display Interface Camera Interface VGSBDO Video General Interface 3 /RESET STANDBY TC35273 MPEG-4 Audiovisual LSI Fig. 2 Pin Map TOSHIBA Confidential 5/23 Version 0.90 2000-4-27 Preliminary Table 1. System Control Signals Signal Name /RESET In/Out In Bit Width 1 MPEG-4 Audiovisual Codec LSI TC35273 STANDBY In 1 Description System Reset Input (Low Active). When the LSI is reset, the reset pin has to be low for more than 16 clock cycles. When power on, the LSI has to be reset after PLL locked. It takes approximately 100us until the PLL locked. System Standby Input (High Active). When it is high, power is not supplied to the internal logic, SRAM, and DRAM. “0”: Normal Operation. “1”: Standby. Table 2. PLL Control Signals Signal Name PLLFN PLLDIV[2:0] In/Out In In Bit Width 1 3 Description Reference Clock Input. It has to be 13.00MHz to 20MHz with +/- 10% duty. System clock frequency select. System Clock = PLLFN * N. “000”: N=2.5. “001”: N=3.0. “010” : N=3.5 “011”: N=4.0. “100”: N=4.5. “101”: N=5:0. “110”: N=5.5. “111”: N=6.0. Analog PLL Power (VDD). Analog PLL Ground (VSS). PLLAVD PLLAVS In In 1 1 Table 3. Host Interface Signal Name /HCS In/Out In Bit Width 1 Description Chip enable input (low active). “0” : Chip select. “1” : Non operation. Write strobe (low active). “0” : Write operation. “1” : Non operation. Read Strobe (low active). “0” : Read operation. “1” : Non operation. Address signal. Data signal. Bus wait signal (low active). “0” : Wait. “1” : Non wait. Interrupt signal (high active). “0” : Non operation. “1” : Interrupt operation. /HWR In 1 /HRD In 1 HADDR[6:0] HDAT[15:0] HWAIT In In/Out Out 7 16 1 HINT Out 1 Table 4 Video General Serial Interface Signal Name VGSCLK VGSADIO VGSBDO In/Out Out In/Out Out Bit Width 1 1 1 Description General I/F clock output. Please open unless this interface is used. Input/output of serial data on port A. Open unless this interface is used. Output of serial data on port B. Open unless this interface is used. TOSHIBA Confidential 6/23 Version 0.90 2000-4-27 Preliminary MPEG-4 Audiovisual Codec LSI TC35273 TOSHIBA Confidential 7/23 Version 0.90 2000-4-27 Preliminary Table 5 Video Camera Interface Signal Name CAMCLK CAMHREF CAMVREF CAMFSEL CAMPIXEL In/Out In In In In In Bit Width 1 1 1 1 8 MPEG-4 Audiovisual Codec LSI TC35273 Description Clock signal from camera. HREF signal from camera. VREF signal from camera. Field select signal from camera in an NTSC mode. Luminance and chrominance data from camera. Table 6 Video Display Interface Signal Name DISPCLK /DISPHSYNC /DISPVSYNC /DISPBLK DISPPIXEL In/Out In In In Out Out Bit Width 1 1 1 1 8 Description Clock signal from display. HSYNC signal from display. VSYNC signal form display. Blanking signal to display. Luminance (Y) and chrominance (Cb,Cr) signal output. Table 7 Audio ADC&DAC Interface Signal Name ADOMCLK ADIMCLK ADLRCLK ADSCLK ADSDI ADSDO In/Out Out In Out Out In Out Bit Width 1 1 1 1 1 1 Description Master clock to external ADC/DAC chips. Master clock from external ADC/DAC chips. Input/output channel clock to external ADC/DAC chips. Audio serial data clock to external ADC/DAC chips. Audio serial data input. Audio serial data output. Table 8 Audio ADC&DAC Control Interface Signal Name ADCMD[4:0] In/Out Out Bit Width 5 Description Command to external ADC/DAC chips. Table 9 Network Bit Stream Interface Signal Name NWCLK /NWOEN /NWDO /NWIEN NWDI NWIFS NWOFS NWINT In/Out In In Out In In In In In Bit Width 1 1 1 1 1 1 1 1 Description Network clock. Network bit serial output enable. Network bit serial output data. Network bit serial input enable. Network bit serial input data. Word synchronization for input data in the frame mode. Word synchronization for output data in the frame mode. Frame signal input in the frame mode. TOSHIBA Confidential 8/23 Version 0.90 2000-4-27 Preliminary Table 10 Test Control Signal Signal Name TGCLK TSMODE TDBISTEN TREOUT TDTMB TDTCLK TEST[2:0] In/Out In In In Out In In In Bit Width 1 1 1 1 1 1 3 MPEG-4 Audiovisual Codec LSI TC35273 Description Test terminal. Please connect to Vss. Test terminal. Please connect to Vss. Test terminal. Please connect to Vss. Test terminal. Please connect to open. Test terminal. Please connect to Vss. Test terminal. Please connect to Vss. Test terminal. Please connect to Vss. Table 11 Power Supply and GND Signal Name Vss Vdds Vdd2 In/Out Bit Width GND 3.3V Vdd 2.5V Vdd Description TOSHIBA Confidential 9/23 Version 0.90 2000-4-27 Preliminary 3. Interface Specifications 3.1 Host Interface MPEG-4 Audiovisual Codec LSI TC35273 An external host CPU accesses to TC35273 via a host interface. The access timing of a read, a write, and an interrupt operation are explained below. The host interface has two access modes; a handshake access mode and a synchronized access mode. 3.1.1 Handshake access mode In this mode, the host CPU has to finish an access operation after a waiting signal (/HWAIT) becomes high. Fig.3 shows the timing diagram of a read operation. A read access starts by asserting both a chip select signal (/HCS) and a read signal (/RD) (timing (a)). At this timing, /HWAIT becomes low. When the read data are ready, /HWAIT becomes high (timing (b)). The host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD (timing (c)). Fig.4 shows the timing diagram of a write operation. A write access starts by asserting both /HCS and a write signal (/WR) (timing (a)). At this timing, /HWAIT becomes low. When TC35273 gets the write data, /HWAIT becomes high (timing (b)). After that, the host CPU finishes the write operation by negating both /HCS and /HWR (timing (c)). (a) TCSS (b) (c) TCSH /HCS TADS TADH HADDR TRR /HRD TWTAD TRDH /HWAIT TWTID TDTVD TDTRS TDTID HDAT TDTOD Fig. 3 Read Operation in handshake mode TOSHIBA Confidential 10/23 Version 0.90 2000-4-27 Preliminary (a) TCSS MPEG-4 Audiovisual Codec LSI TC35273 (b) (c) TCSH /HCS TADS TADH HADDR TRR /HWR TWTAD TRDH /HWAIT TWTID TDTID HDAT TDTWS Fig. 4 Write Operation in handshake mode 3.1.2 Synchronized access mode In this mode, a host CPU accomplishes an access to TC35273 in the specified period without a handshake. However, when the host CPU accesses to the embedded DRAM in TC35273, it has to check whether the next access is available or not by checking a status register before the access. Fig.5 shows the timing diagram of a read operation. A read access starts by asserting both a chip select signal (/HCS) and a read signal (/RD) (timing (a)). After the specified cycles indicated as Tacs, the host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD (timing (b)). Fig.6 shows the timing diagram of a write operation. A write access starts by asserting both /HCS and a write signal (/WR) (timing (a)). After the specified cycles, the host CPU finishes the write operation by negating both /HCS and /HWR (timing (b)). TOSHIBA Confidential 11/23 Version 0.90 2000-4-27 Preliminary (a) TCSS MPEG-4 Audiovisual Codec LSI TC35273 (b) TCSH /HCS TADS TADH HADDR TACS TRR /HRD TWTAD TDTVD TRDH TDTRS TDTID HDAT TDTOD Fig.5 Read Operation in Synchronization mode (a) TCSS (c) TCSH /HCS TADS TADH HADDR TACS TRR /HWR TWTAD TDTID HDAT TDTWS Fig.6 Write Operation in Synchronization Mode TOSHIBA Confidential 12/23 Version 0.90 2000-4-27 Preliminary 3.1.3 Interrupt An interrupt to the external host CPU is performed as follows. (a) HINT Active MPEG-4 Audiovisual Codec LSI TC35273 When an interrupt is requested by TC35273, HINT becomes high (timing (a)). (b) Clear HINT The host CPU detects the interrupt request by HINT. The CPU also detects the interrupt causes by reading an interrupt status register in the host interface of TC35273. When the CPU reads the register at the timing (b), The CPU detects the interrupt causes occurring during the timing (a) and (b). HINT is cleared when the CPU reads the interrupt status register. (c) Multiple Interrupt Even if another interrupt is requested during the timing (b) and (c), The assertion of HINT is suspended to the timing (c). (a) (b) T RR D (c) HINT /HCS H ADDR /HRD T ACS /HW AIT HDAT Fig. 7 Interrupt Operation TOSHIBA Confidential 13/23 Version 0.90 2000-4-27 Preliminary Table 12 Host Interface Timing Parameters TCSS TCSH TADS TADH TWTAD TWTID TACS TACID TDTOD TDTVD TDTRS TDTwS tDTID TRDH TRR * TSYSCLK MPEG-4 Audiovisual Codec LSI TC35273 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Setup time of HCS. Hold time of HCS. Setup time of Address. Hold time of Address. Delay time of /HWAIT for /HRD or /HWR. Access time in handshake access mode.* Access time in synchronized access mode. Delay time of HACK Delay time of Data. Data hold time. Read data setup time. Write data setup time. Data hold time. Hold time of /HRD. Recovery time of /HRD or /HWR Min 0.0 0.0 0.0 0.0 TSYSCLK*3 TSYSCLK*3 Max 15.0 TSYSCLK*100 TSYSCLK*2 TSYSCLK*1 15.0 15.0 TSYSCLK*99 0.0 15.0 0.0 TSYSCLK*3 means the cycle time of TC35274 internal system clock. * Access to internal DRAM requires Tsysclk*100 (ns) in a worst case. As for the others accesses, it takes 3 cycles of the internal system clock. TOSHIBA Confidential 14/23 Version 0.90 2000-4-27 Preliminary 3.2 Video General Serial Interface MPEG-4 Audiovisual Codec LSI TC35273 This interface is reserved to control an external camera or an LCD. It is not supported now. 3.3 Video Camera Interface A CMOS Camera or a CCD Camera is connected via Toshiba CMOS camera DSP ”TC90A50F” or ”TC90A70F”, or an ordinary NTSC decoder LSI. Fig.6, 7, 8 shows the timing diagrams of the camera signal input. When an NTSC decoder is used, TC35273 captures either an odd field or an even field by using CAMFSEL. CAMVREF CAMHREF CAMPIXL Fig. 8 Frame Based CAMVREF Timing Diagram CAMVREF CAMHREF CAMFSEL CAMPIXL 1st Field (Even Field) 2nd Field (Odd Field) Fig. 9 Field Based (NTSC) CAMVREF Timing Diagram TOSHIBA Confidential 15/23 Version 0.90 2000-4-27 Preliminary MPEG-4 Audiovisual Codec LSI TC35273 TCYCLE CAMCLK CAMVREF TSETUP THOLD Cb0 Y0 Cr0 Y1 Y n-1 CAMHREF CAMPXL Fig. 10 Camera Interface Timing Diagram Table 13 Camera Interface Timing Parameter TCYCLE TSETUP THOLD Description Clock cycle of CAMCLK (up to 27MHz) Setup time of CAMVREF, CAMHREF, CAMPIXEL Hold time of CAMVREF, CAMHREF, CAMPIXL Min 35 (TSYSCLK*1)+ 2 2 Max Unit ns ns ns TOSHIBA Confidential 16/23 Version 0.90 2000-4-27 Preliminary 3.4 Video Display Interface LCD controller is required for the connection to an LCD or a monitor. MPEG-4 Audiovisual Codec LSI TC35273 The video display interface outputs image data with YCbCr 4:2:2 8-bit digital format. An external /DISPVSYN 1 /DISPHSYN /DISPBLNK Internal Signal L2VBUSY Vblank=3 VSize=4 VBlank=3 VSize=4 2 3 1 2 3 /DISPHSYN DISPCLK Hblank=4 HSize=2 DISPPIXEL[7:0] Cb0 Y0 Cr0 Y1 Cb0 Y0 Cr0Y1 /DISPBLNK Hblank=4 Fig. 11 Timing Diagram of Display Interface. TCYCLE DSPCLK TSETUP DSPHSYN DSPVSYN THOLD TDELAY DSPBLK DSPPXL Cb0 Y0 Cr0 Y1 Y n-1 Fig. 12 Detail Timing Diagram of Display Interface. TOSHIBA Confidential 17/23 Version 0.90 2000-4-27 Preliminary Table 14 Display Interface Timing Parameter TCYCLE TSETUP THOLD TDELAY * MPEG-4 Audiovisual Codec LSI TC35273 Description Cycle time of DISPCLK Setup time of DISPHSYN and DISPVSYN Hold time DISPHSYN and DISPVSYN Delay time of DISPBLK and DISPPXL Min 100 2 2 Max Unit ns ns ns ns (TSYSCLK*3)+15 W hen system clock is 40MHz, DSPCLK has to be less than 10MHz. 3.5 Audio ADC&DAC Interface Asani-kasei “AK4158” and “AK4323” are connected for external ADC and DAC, respectively. T MCKW ADOMCLK T SCKD T SCKW A DSCLK TSDIS T SDIH ADSDI TLCKD H T LCKD H ADLRCLK T SDOD ADSDO Fig. 13 Audio ADC&DAC Interface TOSHIBA Confidential 18/23 Version 0.90 2000-4-27 Preliminary MPEG-4 Audiovisual Codec LSI TC35273 ASCLK 16 Clock Cycles ALRCK 0 15 15 14 13 12 11 1 0 15 14 13 ASDTI ASDTO 0 14 13 12 11 1 0 15 14 13 Rch Data Lch Data Fig. 14 Audio ADC&DAC Interface (Master clock output mode). Table 15 Audio ADC&DAC Interface Timing (Master clock output mode). Parameter TMCKW TSCKW TSDIS TSDIH TLCKD TSDOD Description Clock cycle period of ADOMCLK. Duty ratio of ADOMCLK. Clock cycle period of ADSCLK. Delay time from ADOMCLK to ADKCLK. Setup time of ADSDI. Hold time of ADSDI. Delay time from ADSCLK to ADLRLCK. Delay time from ADSCLK to ADSDO. Min Max 80 50+/-10 TMCKW *8 TSYSCLK*2 TSYSCLK*1 TSYSCLK*4 TSYSCLK*1 TSYSCLK*6 Unit ns % ns ns ns ns ns ns TOSHIBA Confidential 19/23 Version 0.90 2000-4-27 Preliminary TMCKW MPEG-4 Audiovisual Codec LSI TC35273 ADIMCLK TSCKD TSCKW ADSCLK TSDIS TSDIH ADSDI TLCKDH TLCKDH ADLRCLK TSDOD ADSDO Fig. 15 Audio ADC&DAC Interface (Master clock input mode). Table 16 Audio ADC&DAC Interface Timing (Master clock input mode). Parameter TMCKW Description Cycle time of ADIMCLK. Duty ratio of ADIMCLK. Cycle time of ADSCLK. Delay time from ADIMCLK to ADSCLK. Setup time of ADSDI. Hold time of ADSDI. Delay time from ADSCLK to ADLRLCK. Delay time from ADSCLK from ADSDO. Min Max 80 50±10 TMCKW *8 TSYSCLK*3 TSYSCLK*1 TSYSCLK*4 TSYSCLK*1 TSYSCLK*6 Unit ns % ns ns ns ns ns ns TSCKW TSDIS TSDIH TLCKD TSDOD TOSHIBA Confidential 20/23 Version 0.90 2000-4-27 Preliminary 3.6 Network Bit Stream Interface MPEG-4 Audiovisual Codec LSI TC35273 The multiplexed audiovisual bitstream data are transferred to/from a baseband LSI via a network bit stream interface. This is full-dupulex interface and has two operation modes; a bit serial mode and a frame mode. (1) Bit Serial Mode Serial data are transferred when an enable signal indicates the data validity. In this mode, frame and synchronization informations are contained in the transferred data. TC35273 receives the transferred data via the NWDI pin at the negedge of the network clock “NWCLK” if the input enable signal “NWIEN” shows the data validity. (When NWIEN is low, the data are valid.) TC35273 also sends the data via the NWDO pin at the posedge of NWCLK if the output enable signal “NWOEN” is high. NWCLK /NWOEN NWDO /NWIEN D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 NWDI D0 D1 D2 D3 D4 D5 D6 D7 D8 Fig. 16 Network bit stream timing diagram (bit serial mode). (2) Frame Mode The data are transferred in accordance with both a frame signal “NWINT” and a word synchronization signal. “NWIFS” and “NWOFS” are used for the word synchronization in the data receive and the data send, respectively. After NWIFS or NWOFS becomes high, 16-bit data are transferred. When the data transfer is finished in the frame, NWIFS or NWOFS does not becomes high. In this case, the output data are fixed to low, and the input data are ignored. TOSHIBA Confidential 21/23 Version 0.90 2000-4-27 Preliminary NWCLK NWINT NWIFS NWDI NWOFS NWDO MPEG-4 Audiovisual Codec LSI TC35273 NWCLK NWIFS NWDI D15 D14 D2 D1 D0 D15 D14 D2 D1 D0 D15 NWOFS NWDO D15 D3 D2 D1 D0 D15 D3 D2 D1 D0 Fig. 17 Network bit stream timing diagram (frame mode). TOSHIBA Confidential 22/23 Version 0.90 2000-4-27 Preliminary ‚ƒ TSCKW MPEG-4 Audiovisual Codec LSI TC35273 Fig. 18 indicates the detail timing diagram of the network bitstream interface. NWCLK /NWOEN /NWIEN /NWINT NWOFS NWIFS NWDI TSDOD TENS TENH TSDIS TSDIH NWDO Fig. 18 Detailed Network Bit Stream Interface. Table 17 Network bit stream timing. Parameter Description TSCKW Cycle time of NWCLK. Duty ratio of NWCLK. TENS Setup time of /NOWEN,/NWIEN, /NWINT, NWOFS, and NWIFS TENH Hold time of /NOWEN,/NWIEN, /NWINT, NWOFS, and NWIFS TSDIS Setup time of NWDI TSDIH Hold time of NWDI Min 1000 Max Unit ns % ns 50+/-10 TSYSCLK*3 TSYSCLK*1 2 TSYSCLK*3 TSYSCLK*1 2 TSYSCLK*12 ns ns ns ns TSDOD TSYSCLKis Delay time from NWCLK to NWDO the cycle time of the internal clock in TC35273. 4. Electric Specifications 4.1 TBD. TOSHIBA Confidential 23/23 Version 0.90 2000-4-27