TC4051BF(N,F)

TC4051,4052,4053BP/BF/BFT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4051BP, TC4051BF, TC4051BFT TC4052BP, TC4052BF, TC4052BFT TC4053BP, TC4053BF, TC4053BFT TC4051B Single 8-Channel Multiplexer/Demultiplexer TC4052B Differential 4-Channel Multiplexer/Demultiplexer TC4053B Triple 2-Channel Multiplexer/Demultiplexer TC4051B, TC4052B and TC4053B are multiplexers with capabilities of selection and mixture of analog signal and digital signal. TC4051B has 8 channels configuration. TC4052B has 4 channel × 2 configuration and TC4053B has 2 channel × 3 configuration. The digital signal to the control terminal turns “ON” the corresponding switch of each channel, with large amplitude (VDD − VEE) can be switched by the control signal with small logical amplitude (VDD − VSS). For example, in the case of VDD = 5 V VSS = 0 V and VEE = −5 V, signals between −5 V and +5 V can be switched from the logical circuit with single power supply of 5 volts. As the ON-resistance of each switch is low, these can be connected to the circuits with low input impedance. TC4051BP, TC4052BP, TC4053BP TC4051BF, TC4052BF, TC4053BF TC4051BFT, TC4052BFT, TC4053BFT Weight DIP16-P-300-2.54A SOP16-P-300-1.27A TSSOP16-P-0044-0.65A : 1.00 g (typ.) : 0.18 g (typ.) : 0.06 g (typ.) Start of commercial production 1978-04 1 2016-01-15 TC4051,4052,4053BP/BF/BFT Pin Assignment (top view) TC4051B TC4052B 4 1 16 VDD 0Y 1 16 VDD 6 2 15 2 2Y 2 15 2X COM 3 14 1 Y-COM 3 14 1X 7 4 13 0 3Y 4 13 X-COM 5 5 12 3 1Y 5 12 0X INH 6 11 A INH 6 11 3X VEE 7 10 B VEE 7 10 A VSS 8 9 C VSS 8 9 B TC4053B 1Y 1 16 VDD 0Y 2 15 Y-COM 1Z 3 14 X-COM Z-COM 4 13 1X 0Z 5 12 0X INH 6 11 A VEE 7 10 B VSS 8 9 C Truth Table Control Inputs “ON” Channel Inhibit C∆ B A TC4051B TC4052B TC4053B L L L L 0 0X, 0Y 0X, 0Y, 0Z L L L H 1 1X, 1Y 1X, 0Y, 0Z L L H L 2 2X, 2Y 0X, 1Y, 0Z L L H H 3 3X, 3Y 1X, 1Y, 0Z L H L L 4 ― 0X, 0Y, 1Z L H L H 5 ― 1X, 0Y, 1Z L H H L 6 ― 0X, 1Y, 1Z L H H H 7 ― 1X, 1Y, 1Z H X X X None None None X: Don’t care Δ: Except TC4052B 2 2016-01-15 TC4051,4052,4053BP/BF/BFT Logic Diagram TC4051B VDD 16 B C INH 11 Logic Level Converter A 10 9 6 8 7 VSS VEE OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN 13 14 15 12 1 5 2 4 3 0 1 2 3 4 5 6 7 COMMON TC4052B VDD 16 B INH Logic Level Converter A 13 10 9 6 OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN 12 14 15 11 1 5 2 8 7 4 VSS VEE 3 3 X-COMMON 0X 1X 2X 3X 0Y 1Y 2Y 3Y Y-COMMON 2016-01-15 TC4051,4052,4053BP/BF/BFT TC4053B VDD 16 14 A OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN OUT c IN 12 B Logic Level Converter 11 10 C 9 INH 13 2 1 5 3 4 6 15 8 X-COMMON 0X 1X 0Y 1Y 0Z 1Z Z-COMMON Y-COMMON 7 VEE VSS Truth Table Control C Impedance between IN-OUT H 0.5 to 5 × 102 Ω L >109 Ω Note: (Note) See electrical characteristics OUT c IN Absolute Maximum Ratings (Note) Characteristics Symbol Rating Unit DC supply voltage VDD-VSS −0.5 to 20 V DC supply voltage VDD-VEE −0.5 to 20 V Control input voltage VCIN VSS − 0.5 to VDD + 0.5 V Switch I/O voltage VI/VO VEE − 0.5 to VDD + 0.5 V ICIN ±10 mA VI-VO −0.5 to 0.5 V Power dissipation PD 300 (DIP)/180 (SOP/TSSOP) mW Operating temperature range Topr −40 to 85 °C Storage temperature range Tstg −65 to 150 °C Control input current Potential difference across I/O during ON Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 4 2016-01-15 TC4051,4052,4053BP/BF/BFT Operating Ranges (Note) Characteristics Symbol Test Condition Min Typ. Max VDD-VSS ― 3 ― 18 VDD-VEE ― 3 ― 18 Control input voltage VIN ― VSS ― VDD V Input/output voltage VIN/VOUT ― VEE ― VDD V DC supply voltage Note: Unit V The operating ranges must be maintained to ensure the normal operation of the device. Unused Control inputs must be tied to either VDD or VSS. Static Electrical Characteristics −40°C Test Condition Characteristics Symbol VSS VEE VDD (V) (V) (V) VEE = VSS VIH RL = 1 kΩ to VSS VIS = VDD thru 1 kΩ Control input low voltage On-state resistance VIL RON ΔOn-state resistance between any 2 switches RON∆ Input/output leakage current IOFF Quiescent supply current Input current IIS < 2 μA on all OFF channels IDD IIN 85°C Unit Min Max Min Typ. Max Min Max 3.5 ― 3.5 2.75 ― 3.5 ― 10 7.0 ― 7.0 5.50 ― 7.0 ― 15 11.0 ― 11.0 8.25 ― 11.0 ― 5 ― 1.5 ― 2.25 1.5 ― 1.5 10 ― 3.0 ― 4.5 3.0 ― 3.0 15 ― 4.0 ― 6.75 4.0 ― 4.0 5 Control input high voltage 25°C 0 0 5 ― 850 ― 240 950 ― 1200 0 0 10 ― 210 ― 110 250 ― 300 0 0 15 ― 140 ― 80 160 ― 200 0 0 5 ― ― ― 10 ― ― ― 0 0 10 ― ― ― 6 ― ― ― 0 0 15 ― ― ― 4 ― ― ― VIN = 18 V, VOUT = 0 V 18 ― ±100 ― ±0.01 ±100 ― ±1000 VIN = 0 V, VOUT = 18 V 18 ― ±100 ― ±0.01 ±100 ― ±1000 5 ― 5.0 ― 0.005 5.0 ― 150 10 ― 10 ― 0.010 10 ― 300 15 ― 20 ― 0.015 20 ― 600 0 ≤ VIS ≤ VDD RL = 10 kΩ ― VIN = VSS, VDD (Note) V V Ω Ω nA VIH = 18 V 18 ― 0.1 ― 10−5 0.1 ― 1.0 VIL = 0 V 18 ― −0.1 ― −10−5 −0.1 ― −1.0 μA μA Input capacitance CIN ― ― ― ― ― 5 7.5 ― ― pF Switch input capacitance CIN ― ― ― ― ― 10 ― ― ― pF TC4051B 10 ― ― ― 58 ― ― ― Output capacitance COUT TC4052B 10 ― ― ― 30 ― ― ― TC4053B 10 ― ― ― 17 ― ― ― TC4051B 10 ― ― ― 0.2 ― ― ― TC4052B 10 ― ― ― 0.2 ― ― ― TC4053B 10 ― ― ― 0.2 ― ― ― Feedthrough capacitance Note: CINC-OUT pF pF All valid input combinations. 5 2016-01-15 TC4051,4052,4053BP/BF/BFT Switching Characteristics (Ta = 25°C, CL = 50 pF) Test Condition Characteristics Phase difference between input to output Symbol VSS (V) ― φI-O tpZL Propagation delay time tpZH (A, B, C, -OUT) tpLZ RL = 1 kΩ tpHZ Propagation delay time tpZL (INH-OUT) tpZH Propagation delay time tpLZ (INH-OUT) tpHZ RL = 1 kΩ RL = 1 kΩ −3dB cutoff frequency TC4051B fmax (I-O) TC4052B RL = 1 kΩ (Note 1) TC4053B Total harmonic distortion −50dB feedthrough (switch off) Crosstalk Crosstalk (control-OUT) ― VEE VDD (V) (V) f = 1 kHz (Note 2) Typ. Max 0 0 5 ― 15 45 0 0 10 ― 8 20 0 0 15 ― 6 15 0 0 5 ― 170 550 0 0 10 ― 90 240 0 0 15 ― 70 160 0 −5 5 ― 100 240 0 −7.5 7.5 ― 80 160 0 0 5 ― 120 380 0 0 10 ― 60 200 0 0 15 ― 50 160 0 −5 5 ― 80 200 0 −7.5 7.5 ― 60 160 0 0 5 ― 170 450 0 0 10 ― 90 210 0 0 15 ― 70 160 0 −5 5 ― 100 210 0 −7.5 7.5 ― 80 160 −5 −5 5 ― 20 ― −5 −5 5 ― 30 ― −5 −5 5 ― 40 ― 2.5 ― 0.15 ― 5 ― 0.03 ― 7.5 ― 0.02 ― −2.5 −2.5 RL = 10 kΩ Min −5 −5 −7.5 −7.5 Unit ns ns ns ns MHz % ― RL = 1 kΩ (Note 3) −5 −5 5 ― 500 ― kHz ― RL = 1 kΩ (Note 4) −5 −5 5 ― 1.5 ― MHz RIN = 1 kΩ 0 0 5 ― 200 ― ROUT = 10 kΩ 0 0 10 ― 400 ― CL = 15 pF 0 0 15 ― 600 ― ― Note 1: Sine wave of ±2.5 Vp-p shall be used for Vis and the frequency of 20 log 10 mV VOS = −3dB shall be fmax. Vis  V − VEE  Note 2: Vis shall be sine wave of ±  DD  p-p. 4   Note 3: Sine wave of ±2.5 Vp-p shall be used for Vis and the frequency of 20 log 10 VOS = −50dB shall be Vis feed-through. Note 4: Sine wave of ±2.5 Vp-p shall be used for Vis and the frequency of 20 log 10 VOS = −50dB shall be Vis crosstalk. 6 2016-01-15 TC4051,4052,4053BP/BF/BFT Package Dimensions Weight: 1.00 g (typ.) 7 2016-01-15 TC4051,4052,4053BP/BF/BFT Package Dimensions Weight: 0.18 g (typ.) 8 2016-01-15 TC4051,4052,4053BP/BF/BFT Package Dimensions Weight: 0.06 g (typ.) 9 2016-01-15 TC4051,4052,4053BP/BF/BFT RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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