TC55V040AFT-70

TC55V040AFT-55,-70 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55V040AFT is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5 µA standby current (at VDD = 3 V, Ta = 25°C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the TC55V040AFT can be used in environments exhibiting extreme temperature conditions. The TC55V040AFT is available in normal and reverse pinout plastic 40-pin thin-small-outline package (TSOP). FEATURES • • • • • • • Low-power dissipation Operating: 10.8 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of −40° to 85°C Standby Current (maximum): 3.6 V 3.0 V 7 µA 5 µA • Access Times (maximum): TC55V040AFT -55 Access Time CE1 Access Time CE2 Access Time OE Access Time 55 ns 55 ns 55 ns 30 ns -70 70 ns 70 ns 70 ns 35 ns • Package: TSOPⅠ40-P-1014-0.50 (AFT) (Weight: 0.32 g typ) PIN ASSIGNMENT (TOP VIEW) 40 PIN TSOP 1 40 PIN NAMES A0~A18 Address Inputs CE1 , CE2 R/W OE 20 (Normal) 21 I/O1~I/O8 VDD GND NC Chip Enable Read/Write Control Output Enable Data Inputs/Outputs Power Ground No Connection Pin No. Pin Name Pin No. Pin Name 1 A16 21 A0 2 A15 22 CE1 3 A14 23 GND 4 A13 24 OE 5 A12 25 I/O1 6 A11 26 I/O2 7 A9 27 I/O3 8 A8 28 I/O4 9 R/W 29 NC 10 CE2 30 VDD 11 NC 31 VDD 12 NC 32 I/O5 13 A18 33 I/O6 14 A7 34 I/O7 15 A6 35 I/O8 16 A5 36 A10 17 A4 37 NC 18 A3 38 NC 19 A2 39 GND 20 A1 40 A17 2003-08-06 1/11 TC55V040AFT-55,-70 BLOCK DIAGRAM CE A4 A5 A6 A7 A8 A9 A11 A12 A13 A14 A18 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 ROW ADDRESS BUFFER ROW ADDRESS REGISTER ROW ADDRESS DECODER VDD GND MEMORY CELL ARRAY 2,048 × 256 × 8 (4,194,304) 8 DATA CONTROL SENSE AMP COLUMN ADDRESS DECODER CLOCK GENERATOR COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CE A0 A1 A2 A3 A10A15A16 A17 OE R/W CE1 CE2 CE OPERATING MODE MODE Read Write Output Deselect Standby * = don't care H = logic high L = logic low CE1 L L L H * CE2 H H H * OE L * R/W H L H * * I/O1~I/O8 Output Input High-Z High-Z High-Z POWER IDDO IDDO IDDO IDDS IDDS H * * L MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE −0.3~4.6 −0.3*~4.6 −0.5~VDD + 0.5 UNIT V V V W °C °C °C 0.6 260 −55~150 −40~85 *: −3.0 V when measured at a pulse width of 50ns 2003-08-06 2/11 TC55V040AFT-55,-70 DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) 2.3 V~3.6 V SYMBOL PARAMETER MIN VDD VIH VIL VDH Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage 2.3 2.2 −0.3* UNIT TYP 3.0    MAX 3.6 VDD + 0.3 VDD × 0.22 3.6 V V V V 1.5 *: −3.0 V when measured at a pulse width of 50 ns DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current VIN = 0 V~VDD VOH = VDD − 0.5 V VOL = 0.4 V CE1 = VIH or CE2 = VIL or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE1 = VIL and CE2 = VIH and R/W = VIH and IOUT = 0 mA, Other Input = VIH/VIL Operating Current lDDO2 CE1 = 0.2 V and CE2 = VDD − 0.2 V and VDD = tcycle R/W = VDD − 0.2 V, IOUT = 0 mA, 3 V ± 10% Other Input = VDD − 0.2 V/0.2 V CE = VIH or CE2 = VIL VDD = 3 V ± 10% Standby Current CE1 = VDD − 0.2 V or CE2 = 0.2 V VDD = 1.5 V~3.6 V VDD = 3.3 V ± 0.3 V Ta = 25°C Ta = −40~85°C Ta = 25°C Ta = −40~85°C Ta = 25°C VDD = 3.0 V Ta = −40~40°C Ta = −40~85°C Note: 55 ns 70 ns 1 µs 55 ns VDD = tcycle 3 V ± 10% 70 ns 1 µs TEST CONDITION MIN  −0.5 TYP                MAX ±1.0   ±1.0 UNIT µA mA mA µA 2.1                60 50 10 55 45 5 2 0.6 6 0.7 7 0.5 1 5 µA lDDO1 mA mA IDDS1 mA IDDS2 (Note) 0.05   In standby mode with CE1 ≥ VDD − 0.2 V, these limits are assured for the condition CE2 ≥ VDD − 0.2 V or CE2 ≤ 0.2 V. CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF This parameter is periodically sampled and is not 100% tested. 2003-08-06 3/11 TC55V040AFT-55,-70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.7 to 3.6 V) READ CYCLE TC55V040AFT SYMBOL PARAMETER MIN tRC tACC tCO1 tCO2 tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 55     -55 MAX  -70 MIN 70     UNIT MAX  55 55 55 30   70 70 70 35   ns 5 0   5 0   25 25  30 30  10 10 WRITE CYCLE TC55V040AFT SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 55 45 50 0 0  -55 MAX      -70 MIN 70 50 60 0 0  UNIT MAX      ns 25    30    0 25 0 0 30 0 AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level tR, tF TEST CONDITION 30 pF + 1 TTL Gate 0.4 V, 2.4 V VDD × 0.5 VDD × 0.5 5 ns 2003-08-06 4/11 TC55V040AFT-55,-70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) READ CYCLE TC55V040AFT SYMBOL PARAMETER MIN tRC tACC tCO1 tCO2 tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 70     -55 MAX  -70 MIN 85     UNIT MAX  70 70 70 35   85 85 85 45   ns 5 0   5 0   30 30  35 35  10 10 WRITE CYCLE TC55V040AFT SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 70 50 60 0 0  -55 MAX      -70 MIN 85 55 70 0 0  UNIT MAX      ns 30    35    0 30 0 0 35 0 AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level tR, tF TEST CONDITION 30 pF + 1 TTL Gate VDD − 0.2 V, 0.2 V VDD × 0.5 VDD × 0.5 5 ns 2003-08-06 5/11 TC55V040AFT-55,-70 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address tACC tCO1 CE1 tCO2 CE2 tOE OE tOEE DOUT Hi-Z tCOE INDETERMINATE tODO VALID DATA OUT Hi-Z tOD tOH WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address tAS R/W tCW CE1 tCW CE2 tODW DOUT (See Note 2) Hi-Z tDS DIN (See Note 5) tDH (See Note 5) tOEW (See Note 3) tWP tWR VALID DATA IN 2003-08-06 6/11 TC55V040AFT-55,-70 WRITE CYCLE 2 ( CE1 CONTROLLED) (See Note 4) tWC Address tAS R/W tCW CE1 tCW CE2 tCOE DOUT Hi-Z tDS DIN (See Note 5) tDH tODW Hi-Z tWP tWR VALID DATA IN WRITE CYCLE 3 (CE2 CONTROLLED) (See Note 4) tWC Address tAS R/W tCW CE1 tCW CE2 tCOE DOUT Hi-Z tDS DIN (See Note 5) tDH tODW Hi-Z tWP tWR VALID DATA IN 2003-08-06 7/11 TC55V040AFT-55,-70 Note: (1) (2) (3) (4) (5) R/W remains HIGH for the read cycle. If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL VDH PARAMETER Data Retention Supply Voltage VDH = 3.0 V IDDS2 Standby Current Ta = −40~40°C Ta = −40~85°C MIN 1.5    TYP       MAX 3.6 1 5 7   UNIT V µA VDH = 3.6 V Ta = −40~85°C tCDR tR Note: Chip Deselect to Data Retention Mode Time Recovery Time Read cycle time tRC 0 (See Note) ns ns CE1 CONTROLLED DATA RETENTION MODE VDD (See Note 1) VDD 2.7 V DATA RETENTION MODE (See Note 2) VIH CE1 tCDR VDD − 0.2 V (See Note 2) TR GND CE2 CONTROLLED DATA RETENTION MODE VDD (See Note 3) VDD 2.7 V CE2 VIH VIL GND DATA RETENTION MODE tCDR 0.2 V tR 2003-08-06 8/11 TC55V040AFT-55,-70 Note: (1) (2) (3) In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V or CE2 ≥ VDD − 0.2 V. When CE1 is operating at the VIH level (2.2V), the operating current is given by IDDS1 during the transition of VDD from 3.6 to 2.4V. In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V. 2003-08-06 9/11 TC55V040AFT-55,-70 PACKAGE DIMENSIONS Weight: 0.32 g (typ) 2003-08-06 10/11 TC55V040AFT-55,-70 RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 030619EBA • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 2003-08-06 11/11