TC55VBM416AFTN55

TC55VBM416AFTN55 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1,048,576-WORD BY 16-BIT/2,097,152-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55VBM416AFTN is a 16,777,216-bit static random access memory (SRAM) organized as 1,048,576 words by 16 bits/2,097,152 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.9 µA standby current (at VDD = 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the TC55VBM416AFTN can be used in environments exhibiting extreme temperature conditions. The TC55VBM416AFTN is available in a plastic 48-pin thin-small-outline package (TSOP). FEATURES • • • • • • • Low-power dissipation Operating: 9 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of −40° to 85°C Standby Current (maximum): 3.6 V 3.0 V 15 µA 8 µA • Access Times (maximum): Access Time CE1 Access Time 55 ns 55 ns 55 ns 30 ns CE2 OE Access Time Access Time • Package: TSOPⅠ48-P-1220-0.50 (Weight:0.51 g typ) PIN ASSIGNMENT (TOP VIEW) 48 PIN TSOP PIN NAMES A0~A19 1 48 A-1~A19 CE1 , CE2 Address Inputs (Word Mode) Address Inputs (Byte Mode) Chip Enable Read/Write Control Output Enable Data Byte Control Data Inputs/Outputs Byte (×8 mode) Enable Power Ground No Connection Option R/W OE LB , UB 24 (Normal) 25 I/O1~I/O16 BYTE VDD GND NC OP* *: OP pin must be open or connected to GND. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 A15 17 A17 33 I/O3 2 A14 18 A7 34 I/O11 3 A13 19 A6 35 I/O4 4 A12 20 A5 36 I/O12 5 A11 21 A4 37 VDD 6 A10 22 A3 38 I/O5 7 A9 23 A2 39 8 A8 24 A1 40 9 A19 25 A0 41 10 NC 26 CE1 11 R/W 27 GND 43 12 CE2 28 OE 13 OP 29 I/O1 14 UB 15 LB 31 I/O2 16 A18 32 I/O10 48 A16 30 I/O9 42 44 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 45 46 47 I/O16 GND BYTE /A-1 2002-08-29 1/14 TC55VBM416AFTN55 BLOCK DIAGRAM CE A0 A8 A9 A10 A11 A12 A13 A14 A15 A16 A18 A19 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 VDD GND MEMORY CELL ARRAY 4,096 × 256 × 16 (16,777,216) ROW ADDRESS BUFFER ROW ADDRESS REGISTER ROW ADDRESS DECODER SENSE AMP DATA OUTPUT BUFFER CE A-1 A1 A2 A3 A4 A5 A6 A17 A7 DATA INPUT BUFFER COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR CE1 CE2 LB CE UB R/W OE BYTE DATA OUTPUT BUFFER DATA INPUT BUFFER 2002-08-29 2/14 TC55VBM416AFTN55 OPERATING MODE MODE CE1 CE2 H H H H H H H H H H H H * L * OE R/W H H H H L L L L H H H H * * * BYTE L H H H L H H H L H H H H or L H or L H LB * L H L * L H L * L H L * * H UB I/O1~I/O8 Output Output High-Z Output Input Input High-Z Input High-Z High-Z High-Z High-Z High-Z High-Z High-Z I/O9~I/O15 High-Z Output Output High-Z High-Z Input Input High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z A-1 I/O16 POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS IDDS IDDS L Read L L L L Write L L L L Output Deselect L L L H Standby * * * = don't care H = logic high L = logic low L L L L * * * * H H H H * * * * L L H * L L H * L L H * * H Output Output High-Z A-1 Input Input High-Z A-1 High-Z High-Z High-Z High-Z High-Z High-Z MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE −0.3~4.2 −0.3*~4.2 −0.5~VDD + 0.5 0.6 260 −55~150 −40~85 UNIT V V V W °C °C °C *: −2.0 V when measured at a pulse width of 20ns DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) SYMBOL VDD VIH VIL VDH PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage VDD = 2.3 V~2.7 V VDD = 2.7 V~3.6 V MIN 2.3 2.0 2.2 −0.3* 1.5   VDD × 0.24 3.6 V V TYP   MAX 3.6 VDD + 0.3 UNIT V V *: −2.0 V when measured at a pulse width of 20ns 2002-08-29 3/14 TC55VBM416AFTN55 DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current VIN = 0 V~VDD VOH = VDD − 0.5 V VOL = 0.4 V CE1 = VIH or CE2 = VIL or LB = UB = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE1 = VIL and CE2 = VIH and R/W = VIH, LB = UB = VIL, IOUT = 0 mA, Other Input = VIH/VIL CE1 = 0.2 V and CE2 = VDD − 0.2 V and R/W = VDD − 0.2 V, LB = UB = 0.2 V, IOUT = 0 mA, Other Input = VDD − 0.2 V/0.2 V TEST CONDITION MIN  −0.5 2.1  MIN tcycle 1 µs MIN tcycle 1 µs TYP     MAX ±1.0   ±1.0 35 UNIT µA mA mA µA                0.9   lDDO1 Operating Current lDDO2 mA 8 30 mA 3 1 mA IDDS1 1) CE1 = VIH or CE2 = VIL (at BYTE ≥ VDD − 0.2 V or ≤ 0.2 V) 2) LB = UB = VIH (at BYTE ≥ VDD − 0.2 V) 1) CE1 = VDD − 0.2 V, CE2 = VDD = Ta = −40~85°C VDD − 0.2 V (at BYTE ≥ VDD 3.3 V ± 0.3 V − 0.2 V or ≤ 0.2 V) Ta = 25°C 2) CE2 = 0.2 V (at BYTE ≥ VDD − 0.2 V or ≤ 0.2 V) VDD = 3.0 V Ta = −40~40°C 3) LB = UB = VDD − 0.2 V, CE1 = 0.2 V, CE2 = VDD − 0.2 Ta = −40~85°C V (at BYTE ≥ VDD − 0.2 V) 15  µA 3 8 Standby Current IDDS2 CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF This parameter is periodically sampled and is not 100% tested. 2002-08-29 4/14 TC55VBM416AFTN55 (Ta = −40° to 85°C, VDD = 2.7 to 3.6 V) READ CYCLE SYMBOL tRC tACC tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time PARAMETER MIN 55      5 0 5    10 MAX  55 55 55 30 55    25 25 25  ns UNIT AC CHARACTERISTICS AND OPERATING CONDITIONS WRITE CYCLE SYMBOL tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH Note: Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time PARAMETER MIN 55 40 45 45 0 0  0 25 0 MAX       25    ns UNIT tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-29 5/14 TC55VBM416AFTN55 (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) READ CYCLE SYMBOL tRC tACC tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Read Cycle Time Address Access Time Chip Enable( CE1 ) Access Time Chip Enable(CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time PARAMETER MIN 70      5 0 5    10 MAX  70 70 70 35 70    30 30 30  ns UNIT AC CHARACTERISTICS AND OPERATING CONDITIONS WRITE CYCLE SYMBOL tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH Note: Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time PARAMETER MIN 70 50 55 55 0 0  0 30 0 MAX       30    ns UNIT tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-29 6/14 TC55VBM416AFTN55 AC TEST CONDITIONS PARAMETER Input pulse level t R, t F Timing measurements Reference level Output load TEST CONDITION 0.2 V, VDD × 0.7 V + 0.2 V 1V / ns(Fig.1) VDD × 0.5 VDD × 0.5 30 pF + 1 TTL Gate(Fig.2) Fig.1 : Input rise and fall time Fig.2 : Output load VTM VDD Typ GND 10% 1 V/ns tR 90% 90% 10% 1 V/ns tF R1 Dout R1 = 810 Ω R2 = 1610 Ω VTM = 2.3 V R2 30 pF BYTE FUNCTION SYMBOL tBS tBR BYTE Setup Time BYTE Recovery Time PARAMETER MIN 5 5 MAX   UNIT ms ms TIMING DIAGRAMS BYTE CE2 CE1 tBS BYTE tBR 2002-08-29 7/14 TC55VBM416AFTN55 READ CYCLE (See Note 1) tRC Address A0~A19 (Word Mode) A-1~A19 (Byte Mode) tACC tCO1 CE1 tOH tCO2 CE2 tOE OE tOD tBA UB , LB tODO DOUT I/O1~16 (Word Mode) I/O1~8 (Byte Mode) tBE tOEE Hi-Z tCOE tBD VALID DATA OUT Hi-Z WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address A0~A19 (Word Mode) A-1~A19 (Byte Mode) tAS R/W tCW CE1 tWP tWR tCW CE2 tBW UB , LB tODW DOUT I/O1~16 (Word Mode) I/O1~8 (Byte Mode) tOEW Hi-Z tDS tDH (See Note 5) (See Note 3) (See Note 2) DIN I/O1~16 (Word Mode) I/O1~8 (Byte Mode) (See Note 5) VALID DATA IN 2002-08-29 8/14 TC55VBM416AFTN55 WRITE CYCLE 2 ( CE1 CONTROLLED) (See Note 4) tWC Address A0~A19 (Word Mode) A-1~A19 (Byte Mode) tAS R/W tCW CE1 tWP tWR tCW CE2 tBW UB , LB tBE DOUT I/O1~16 (Word Mode) I/O1~8 (Byte Mode) tODW Hi-Z tDS tDH Hi-Z tCOE DIN I/O1~16 (Word Mode) I/O1~8 (Byte Mode) (See Note 5) VALID DATA IN WRITE CYCLE 3 (CE2 CONTROLLED) (See Note 4) tWC Address A0~A19 (Word Mode) A-1~A19 (Byte Mode) tAS R/W tCW CE1 tWP tWR tCW CE2 tBW UB , LB tBE DOUT I/O1~16 (Word Mode) I/O1~8 (Byte Mode) tODW Hi-Z tDS tDH Hi-Z tCOE DIN I/O1~16 (Word Mode) I/O1~8 (Byte Mode) (See Note 5) VALID DATA IN 2002-08-29 9/14 TC55VBM416AFTN55 WRITE CYCLE 4 ( UB, LB CONTROLLED) (See Note 4) tWC Address A0~A19 (Word Mode) tAS R/W tCW CE1 tWP tWR tCW CE2 tBW UB , LB tBE DOUT I/O1~16 (Word Mode) Hi-Z tODW Hi-Z tDS tDH tCOE DIN I/O1~16 (Word Mode) (See Note 5) VALID DATA IN Note: (1) (2) (3) (4) (5) R/W remains HIGH for the read cycle. If CE1 (or UB or LB ) goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE1 (or UB or LB ) goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 2002-08-29 10/14 TC55VBM416AFTN55 DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL VDH PARAMETER Data Retention Supply Voltage VDH = 3.6 V Ta = −40~85°C IDDS2 Standby Current VDH = 3.0 V Ta = −40~40°C Ta = −40~85°C MIN 1.5    0 5 TYP       MAX 3.6 15 3 8   ns ms µA UNIT V tCDR tR Chip Deselect to Data Retention Mode Time Recovery Time CE1 CONTROLLED DATA RETENTION MODE VDD (See Note 1) VDD 2.3 V DATA RETENTION MODE (See Note 2) VIH tCDR CE1 (See Note 2) VDD − 0.2 V tR GND CE2 CONTROLLED DATA RETENTION MODE VDD (See Note 3) VDD 2.3 V DATA RETENTION MODE CE2 VIH VIL GND tCDR 0.2 V tR UB , LB CONTROLLED DATA RETENTION MODE VDD (See Note 4) VDD 2.3 V DATA RETENTION MODE (See Note 5) VIH tCDR UB , LB (See Note 5) VDD − 0.2 V tR GND 2002-08-29 11/14 TC55VBM416AFTN55 Note: (1) (2) (3) (4) (5) In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V or CE2 ≥ VDD − 0.2 V. When CE1 is operating at the VIH(min.) level, the operating current is given by IDDS1 during the transition of VDD from 2.3(2.7) to 2.2V(2.4 V). In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V. In UB (or LB ) controlled data retention mode, minimum standby current mode is entered when CE1 ≤ 0.2 V or CE1 ≥ VDD − 0.2 V, CE2 ≤ 0.2 V or CE2 ≥ VDD − 0.2 V. When UB (or LB ) is operating at the VIH(min.) level, the operating current is given by IDDS1 during the transition of VDD from 2.3(2.7) to 2.2V(2.4 V). 2002-08-29 12/14 TC55VBM416AFTN55 PACKAGE DIMENSIONS TSOPⅠ48-P-1220-0.50 0.08 M Unit:mm 1 0.22 0.08 48 12.0 0.1 12.4max 24 18.4 0.1 20.0 0.2 25 0.25 typ 0.5 1.0 0.1 1.2max 0.1 0.05 0.145 0.055 0.5 0.1 Weight:0.51 g (typ) 0~10 2002-08-29 0.1 13/14 TC55VBM416AFTN55 RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 2002-08-29 14/14