TC74AC112F

TC74AC112P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC112P,TC74AC112F,TC74AC112FN Dual J-K Flip Flop with Preset and Clear Note: The TC74AC112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. In accordance with the logic level given J and K input this device changes state on negative going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage. xxxFN (JEDEC SOP) is not available in Japan. TC74AC112P TC74AC112F Features • • • • High speed: fmax = 170 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 4 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω • • • transmission lines. Balanced propagation delays: tpLH ∼ tpHL − Wide operating voltage range: VCC (opr) = 2 to 5.5 V Pin and function compatible with 74F112 TC74AC112FN Pin Assignment Weight DIP16-P-300-2.54A SOP16-P-300-1.27A SOL16-P-150-1.27 : 1.00 g (typ.) : 0.18 g (typ.) : 0.13 g (typ.) 1 2007-10-01 TC74AC112P/F/FN IEC Logic Symbol Truth Table Inputs CLR Outputs K X X X L H L H X CK PR J X X X L L H H X Q L H H Qn L H Qn Q Function Clear Preset L H L H H H H H H L L H H H H H X X X H L H Qn No Change H L Qn Qn Toggle No Change Qn X: Don’t care System Diagram 2 2007-10-01 TC74AC112P/F/FN Absolute Maximum Ratings (Note 1) Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating −0.5 to 7.0 −0.5 to VCC + 0.5 −0.5 to VCC + 0.5 ±20 ±50 ±50 ±100 500 (DIP) (Note 2)/180 (SOP) −65 to 150 Unit V V V mA mA mA mA mW °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be applied up to 300 mW. Operating Ranges (Note) Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time Symbol VCC VIN VOUT Topr dt/dV Rating 2.0 to 5.5 0 to VCC 0 to VCC −40 to 85 0 to 100 (VCC = 3.3 ± 0.3 V) 0 to 20 (VCC = 5 ± 0.5 V) Unit V V V °C ns/V Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 3 2007-10-01 TC74AC112P/F/FN Electrical Characteristics DC Characteristics Test Condition Characteristics Symbol VCC (V) 2.0 High-level input voltage VIH ⎯ 3.0 5.5 2.0 Low-level input voltage VIL ⎯ 3.0 5.5 2.0 IOH = −50 μA High-level output voltage VOH VIN = VIH or IOH = −4 mA VIL IOH = −24 mA IOH = −75 mA IOL = 50 μA Low-level output voltage VOL VIN = VIH or IOL = 12 mA VIL IOL = 24 mA IOL = 75 mA Input leakage current Quiescent supply current IIN ICC VIN = VCC or GND VIN = VCC or GND (Note) (Note) 3.0 4.5 3.0 4.5 5.5 2.0 3.0 4.5 3.0 4.5 5.5 5.5 5.5 Min 1.50 2.10 3.85 ⎯ ⎯ ⎯ 1.9 2.9 4.4 2.58 3.94 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Ta = 25°C Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2.0 3.0 4.5 ⎯ ⎯ ⎯ 0.0 0.0 0.0 ⎯ ⎯ ⎯ ⎯ ⎯ Max ⎯ ⎯ ⎯ 0.50 0.90 1.65 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.1 0.1 0.1 0.36 0.36 ⎯ ±0.1 4.0 Ta = −40 to 85°C Min 1.50 2.10 3.85 ⎯ ⎯ ⎯ 1.9 2.9 4.4 2.48 3.80 3.85 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max ⎯ ⎯ ⎯ 0.50 0.90 1.65 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.1 0.1 0.1 0.44 0.44 1.65 ±1.0 40.0 μA μA V V V V Unit Note: This spec indicates the capability of driving 50 Ω transmission lines. One output should be tested at a time for a 10 ms maximum duration. 4 2007-10-01 TC74AC112P/F/FN Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) Minimum pulse width ( CK ) Ta = 25°C Limit Ta = −40 to 85°C Limit Unit tW (L) tW (H) tW (L) ⎯ 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 7.5 5.0 7.0 5.0 11.0 6.0 0.0 0.0 3.0 2.0 7.5 5.0 7.0 5.0 11.0 6.0 0.0 0.0 3.0 2.0 ns Minimum pulse width ( CLR , PR ) Minimum set-up time ⎯ ns ts ⎯ ns Minimum hold time Minimum removal time ( CLR , PR ) th ⎯ ns trem ⎯ ns AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns) Characteristics Propagation delay time ( CK -Q, Q ) Propagation delay time ( CLR , PR -Q, Q ) Maximum clock frequency Input capacitance Power dissipation capacitance Symbol Test Condition VCC (V) tpLH tpHL tpLH tpHL fmax CIN CPD (Note) ⎯ Ta = 25°C Min ⎯ ⎯ ⎯ ⎯ Ta = −40 to 85°C Max 15.5 9.4 14.6 8.3 ⎯ ⎯ Unit Typ. 9.1 6.5 8.6 5.8 90 150 5 85 Min 1.0 1.0 1.0 1.0 45 80 ⎯ ⎯ Max 17.8 10.8 16.8 9.6 ⎯ ⎯ 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 ⎯ ⎯ ns ⎯ ns ⎯ 45 80 ⎯ ⎯ MHz pF pF 10 ⎯ 10 ⎯ Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC/2 (per F/F) 5 2007-10-01 TC74AC112P/F/FN Package Dimensions Weight: 1.00 g (typ.) 6 2007-10-01 TC74AC112P/F/FN Package Dimensions Weight: 0.18 g (typ.) 7 2007-10-01 TC74AC112P/F/FN Package Dimensions (Note) Note: This package is not available in Japan. Weight: 0.13 g (typ.) 8 2007-10-01 TC74AC112P/F/FN RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 20070701-EN GENERAL • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 9 2007-10-01