TC74AC166P

TC74AC166P/F/FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC166P,TC74AC166F,TC74AC166FN 8-Bit Shift Register (P-IN, S-OUT) Note: The TC74AC166 is an advanced high speed CMOS 8-BIT PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It consists of parallel-in or serial-in, serial-out 8-bit shift register with a gated clock input and an overriding clear input. The parallel-in or serial-in modes are controlled by the SHIFT/ LOAD input. When the SHIFT/ LOAD input is held high, the serial data input is enabled and the eight flip-flops perform serial shifting on each clock pulse. When held low, the parallel data inputs are enabled and synchronous loading occurs on the next clock pulse. Clocking is accomplished on the low-to-high transition of the clock pulse. The CLOCK-INHIBIT input should be shifted high only while the CLOCK input is held high. A direct clear input overrides all other inputs, including the clock, and sets all the flip-flops to zero. Functional details are shown in the truth table and the timing charts. All inputs are equipped with protection circuits against static discharge or transient excess voltage. xxxFN (JEDEC SOP) is not available in Japan. TC74AC166P TC74AC166F TC74AC166FN Features • • • • High speed: fmax = 170 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 8 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω • • • transmission lines. Balanced propagation delays: tpLH ∼ tpHL − Wide operating voltage range: VCC (opr) = 2 to 5.5 V Pin and function compatible with 74HC166 Weight DIP16-P-300-2.54A SOP16-P-300-1.27A SOL16-P-150-1.27 : 1.00 g (typ.) : 0.18 g (typ.) : 0.13 g (typ.) Pin Assignment 1 2007-10-01 TC74AC166P/F/FN IEC Logic Symbol Truth Table Inputs Internal Output Output CLR L H H H H H SHIFT/ LOAD CK INH. X X L L L H CK X SERIAL IN X X X H L PARALLEL A･･････H X X a･･････h X X X QA L QB L QH L X X L H H X No Change a b h QGn QGn H QAn L QAn X X No Change X: Don’t care a･･････h: The level of steady state input voltage at inputs A through H respectively 2 2007-10-01 TC74AC166P/F/FN Timing Chart 3 2007-10-01 TC74AC166P/F/FN System Diagram Absolute Maximum Ratings (Note 1) Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating −0.5 to 7.0 −0.5 to VCC + 0.5 −0.5 to VCC + 0.5 ±20 ±50 ±50 ±100 Unit V V V mA mA mA mA mW °C 500 (DIP) (Note 2)/180 (SOP) −65 to 150 Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be applied up to 300 mW. 4 2007-10-01 TC74AC166P/F/FN Operating Ranges (Note) Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time Symbol VCC VIN VOUT Topr dt/dV Rating 2.0 to 5.5 0 to VCC 0 to VCC −40 to 85 Unit V V V °C ns/V 0 to 100 (VCC = 3.3 ± 0.3 V) 0 to 20 (VCC = 5 ± 0.5 V) Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Electrical Characteristics DC Characteristics Test Condition Characteristics Symbol VCC (V) 2.0 High-level input voltage VIH ⎯ Ta = 25°C Min 1.50 2.10 3.85 ⎯ ⎯ ⎯ Ta = −40 to 85°C Max ⎯ ⎯ ⎯ Unit Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Min 1.50 2.10 3.85 ⎯ ⎯ ⎯ Max ⎯ ⎯ ⎯ 3.0 5.5 2.0 V 0.50 0.90 1.65 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.50 0.90 1.65 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Low-level input voltage VIL ⎯ 3.0 5.5 2.0 V 1.9 2.9 4.4 2.58 3.94 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2.0 3.0 4.5 ⎯ ⎯ ⎯ 1.9 2.9 4.4 2.48 3.80 3.85 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IOH = −50 μA High-level output voltage VOH VIN = VIH or IOH = −4 mA VIL IOH = −24 mA IOH = −75 mA IOL = 50 μA Low-level output voltage VOL VIN = VIH or IOL = 12 mA VIL IOL = 24 mA IOL = 75 mA Input leakage current Quiescent supply current IIN ICC VIN = VCC or GND VIN = VCC or GND (Note) (Note) 3.0 4.5 3.0 4.5 5.5 2.0 3.0 4.5 3.0 4.5 5.5 5.5 5.5 V 0.0 0.0 0.0 ⎯ ⎯ ⎯ ⎯ ⎯ 0.1 0.1 0.1 0.36 0.36 ⎯ ±0.1 0.1 0.1 0.1 0.44 0.44 1.65 ±1.0 μA μA V 8.0 80.0 Note: This spec indicates the capability of driving 50 Ω transmission lines. One output should be tested at a time for a 10 ms maximum duration. 5 2007-10-01 TC74AC166P/F/FN Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) Minimum pulse width (CK) Minimum pulse width ( CLR ) Minimum set-up time (SI, PI) Minimum set-up time ( S/L ) Minimum hold time (SI, PI) Minimum hold time ( S/L ) Minimum removal time ( CLR ) tW (H) tW (L) tW (L) ⎯ Ta = 25°C Limit 7.0 5.0 8.0 5.0 8.0 4.0 7.0 4.0 0.5 0.5 1.0 1.0 4.0 1.5 Ta = −40 to 85°C Limit 7.0 5.0 8.0 5.0 8.0 4.0 7.0 4.0 0.5 0.5 1.0 1.0 4.0 1.5 Unit 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 ns ⎯ ns ts ⎯ ns ts ⎯ ns th ⎯ ns th ⎯ ns trem ⎯ ns AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns) Characteristics Propagation delay time (CK-QH) Propagation delay time ( CLR -QH) Maximum clock frequency Input capacitance Power dissipation capacitance fmax CIN CPD (Note) ⎯ ⎯ ⎯ Symbol Test Condition VCC (V) Min ⎯ ⎯ ⎯ ⎯ Ta = 25°C Typ. 9.4 6.6 9.2 6.4 105 150 5 67 Max 16.1 10.0 15.2 9.6 ⎯ ⎯ Ta = −40 to 85°C Min 1.0 1.0 1.0 1.0 55 90 ⎯ ⎯ Unit Max 18.3 11.4 17.4 10.9 ⎯ ⎯ tpLH tpHL ⎯ 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 ns tpHL ⎯ ns 55 90 ⎯ ⎯ MHz pF pF 10 ⎯ 10 ⎯ Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC 6 2007-10-01 TC74AC166P/F/FN Package Dimensions Weight: 1.00 g (typ.) 7 2007-10-01 TC74AC166P/F/FN Package Dimensions Weight: 0.18 g (typ.) 8 2007-10-01 TC74AC166P/F/FN Package Dimensions (Note) Note: This package is not available in Japan. Weight: 0.13 g (typ.) 9 2007-10-01 TC74AC166P/F/FN RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 20070701-EN GENERAL • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 10 2007-10-01